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Patent Application 17874327 - METHOD OF FABRICATING MAGNETIC TUNNELING - Rejection

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Patent Application 17874327 - METHOD OF FABRICATING MAGNETIC TUNNELING

Title: METHOD OF FABRICATING MAGNETIC TUNNELING JUNCTION DEVICE

Application Information

  • Invention Title: METHOD OF FABRICATING MAGNETIC TUNNELING JUNCTION DEVICE
  • Application Number: 17874327
  • Submission Date: 2025-05-12T00:00:00.000Z
  • Effective Filing Date: 2022-07-27T00:00:00.000Z
  • Filing Date: 2022-07-27T00:00:00.000Z
  • National Class: 438
  • National Sub-Class: 173000
  • Examiner Employee Number: 100778
  • Art Unit: 2812
  • Tech Center: 2800

Rejection Summary

  • 102 Rejections: 0
  • 103 Rejections: 4

Cited Patents

The following patents were cited in the rejection:

Office Action Text


    Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based upon an application filed in TAIWAN on 07/06/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/27/2022.  The submission is in compliance with the provisions of 37 CFR 1.97.  Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract of the disclosure is objected to because there are multiple spaces between subsequent sentences.  A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is further objected to because of the following informalities: there are multiple instances of multiple spaces between subsequent sentences throughout the specification.  
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities: 
Claim 1, line 12: “The protective layer" should read “the first protective layer”.
Claims 2-11 are objected to due to their dependency on the objected claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary.  Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2 and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0151502 A1; Kim et al.; 05/2021; (hereinafter “Kim”) in view of US 9705071 B2; Annunziata et al.; 07/2017; (hereinafter “Annunziata”).
Regarding Claim 1, Kim teaches a method of fabricating a magnetic tunneling junction (MTJ) device (Figure 1, [0005] magnetoresistive random access memory (MRAM) device with MTJ structure), comprising: 
forming a first via (#110, Figure 4, a lower electrode contact) in a first dielectric layer (#106, Figure 4, #110 forms within an insulating interlayer); 
forming a first electrode layer (#112, Figure 4, lower electrode layer) on the first dielectric layer and the first via (Figure 4, #112 disposes on top of #106 and #110); 
forming an MTJ stack layer (#114, Figure 4, MTJ layers) on the first electrode layer (Figure 4, #114 forms on top of #112); 
forming a patterned second electrode layer (#118a, Figure 5, the pattern mask #130a is used to transfer its pattern to #118) on the MTJ stack layer (#118a disposes on top of #114); 
using the patterned second electrode layer as a mask, performing a first ion beam etching (IBE) process ([0074], Figure 6, #118a is used as etching mask in an reactive ion etching (RIE) process which is a specific etching method recited in claim 6 of instant application) to etch the patterned second electrode layer and pattern the MTJ stack layer and the first electrode layer ([0074 & 0078], Figure 6, RIE removes a portion of #118a, #114 and #112) to form a second electrode, an MTJ stack structure and a first electrode (Figure 6, etching process results in a stack structure of upper electrode #118a, MTJ structure #136 and lower electrode #112a); 
Kim does not teach forming a first protective layer to cover a top surface and a sidewall of the second electrode and a sidewall of the MTJ stack structure, and using the protective layer as a mask, performing a second ion beam etching to remove at least a portion of the MTJ stack structure and at least a portion of the first electrode.
However, Annunziata teaches a method of fabricating an MTJ device (Figure 2C-D, col. 1, ln. 45-47, a method of making of an MRAM device with forming at least an MTJ structure #205 on a bottom contact electrode #201). The method comprises forming a first protective layer (#240, Figure 2B, a sacrificial dielectric film) to cover a top surface and a sidewall of the second electrode (#210, Figure 2B, #240 covers the top surface and sidewall of a hard mask structure of conductive materials) and a sidewall of the MTJ stack structure (Figure 2B, #240 covers sidewalls of #205). Furthermore, Annunziata further teaches using the protective layer as a mask, performing a second ion beam etching to remove at least a portion of the MTJ stack structure and at least a portion of the first electrode (col. 7, ln. 5-9, Figure 2C, a directional etching or IBE uses the sacrificial dielectric film #240 as mask to etch at least a portion of the sidewalls of #205). 
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine teaching of Annunziata with Kim so that the method comprised forming a first protective layer to cover a top surface and a sidewall of the second electrode and a sidewall of the MTJ stack structure, and using the protective layer as a mask, performing a second ion beam etching to remove at least a portion of the MTJ stack structure and at least a portion of the first electrode in order to remove the metal redeposition (Annunziata, col. 6, ln. 62-66) formed on the sidewalls of the MTJ stack and the first electrode of Kim in view of Annunziata during the first IBE etching process and prevent electrical shorting in the device units (Annunziata, col. 3, ln. 33-38). 
Regarding Claim 2, Kim in view of Annunziata teaches the method of fabricating an MTJ device as described in claim 1.
Kim does not teach the first protective layer further covers a sidewall of the first electrode and a top surface of the first dielectric layer.
However, Annunziata teaches the first protective layer (#240, Figure 2D, a sacrificial dielectric film) further covers a sidewall of the first electrode (#201, Figure 2D, #240 covers at least the top surface of the bottom contact electrode according to col. 5, ln. 60-62) and a top surface of the first dielectric layer (according to [0059], a dielectric material is deposited as an intermediate layer between the substrate and the electrode and MTJ. Since #240 covers #201, it also covers the top surface of the first dielectric layer).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to form a first protective layer on the MTJ structure of Kim (see claim 1 rejection) as was done in Annunziata that would further cover the sidewalls of the patterned first electrode of Kim and the first dielectric layer, on which the first electrode forms, for the reasons set forth in the rejection of claim 1.
Regarding Claim 5, Kim in view of Annunziata teaches the method of fabricating an MTJ device as described in claim 1.
Kim does not teach the first protective layer comprises a dielectric material.
However, Annunziata teaches the first protective layer comprises a dielectric material (#240, Figure 2D, a sacrificial dielectric film).
It would been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to deposit a first protective layer comprising dielectric material as was done in Annunziata on the MTJ structure of Kim for the reasons set forth in the rejection of claim 1.
Regarding Claim 6, Kim in view of Annunziata teaches the method of fabricating an MTJ device as described in Claim 1, wherein Kim further teaches the first ion beam etching process comprises a reactive ion etching (RIE) process (Kim, [0072]).
Kim does not explicitly teach the first ion beam etching and the second ion beam etching process comprise an RIE process.
However, Annunziata teaches the first ion beam etching process comprises an RIE process (col. 5, ln. 33-38, the MTJ stack #205 can be etched using an RIE) and the second ion beam etching process comprises an RIE process (col. 7, ln. 5-9, a directional etching process is used to remove the sidewalls of the MTJ #205, wherein the directional etching is known to comprise an IBE or RIE process).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine the teaching of Annunziata with Kim so that the first ion beam etching and the second ion beam etching process comprised an RIE process, as it would merely make a simple substitution of one known method (IBE process of Kim) for another (RIE process of Annunziata) to obtain predictable results of successfully etching the MTJ structure. (See MPEP 2143(I)(B))
Regarding Claim 7, Kim in view of Annunziata teaches the method of fabricating an MTJ device as described in Claim 1, wherein Kim further teaches a difference between a lower width (#W4, Figure 1 of Kim annotated) and an upper width (#W3, Figure 1 of Kim annotated) of the first electrode (#112a, Figure 1 of Kim annotated) is smaller than a difference between a lower width (#W2, Figure 1 of Kim annotated) and an upper width (#W1, Figure 1 of Kim annotated) of the second electrode (#118a, Figure 1 annotated).

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Regarding Claim 8, Kim in view of Annunziata teaches the method of fabricating an MTJ device as described in Claim 1, wherein Kim further teaches when the first ion beam etching process (see Figure 6 of Kim) is performed, top corners (Kim, #C1, Figure 1 of Kim annotated) of the patterned second electrode layer (Kim, #118a, Figure 1 of Kim annotated) are chamfered (Kim, Figure 1 of Kim annotated, #C1 has a rounded shape).
Regarding Claim 9, Kim in view of Annunziata teaches the method of fabricating an MTJ device as described in Claim 1, wherein Kim further teaches forming a second protective layer (Kim, #140, Figure 7, a capping layer forms to prevent damage to the stack structure of MTJ and electrodes #138 according to [0036]) on the first protective layer (see claim 1 rejection for forming a first protective layer on the electrode and MTJ structure during prior processes) and the first dielectric layer (Kim, #106, Figure 7, insulating interlayer).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0151502 A1; Kim et al.; 05/2021; (hereinafter “Kim”) in view of US 9705071 B2; Annunziata et al.; 07/2017; (hereinafter “Annunziata”) and further in view of US 9,515,250 B2; Ha, Ga-Young; 12/2016; (hereinafter “Ha”).
Regarding Claim 3, Kim in view of Annunziata teaches the method of fabricating the MTJ device of claim 1.
Kim in view of Annunziata does not teach the first protective layer is formed to have an overhang.
However, Ha teaches the method for fabricating an MTJ device unit (see Figure 2 of Ha annotated below, a semiconductor memory unit with variable resistance patterns that comprise of MTJ structure according to col. 1, ln. 42-47) which includes at least forming a protective layer (#119, Figure 2 of Ha annotated, a protective layer comprises a combination of a first layer #117 and a second layer #118 of the same material according to col. 8, ln. 33-35) to have an overhang on its upper portion (col. 8, ln. 20-23) that covers the electrodes and MTJ structure.
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to consider forming the protective layer with overhang portions as was done in Ha on the second electrode of Kim in view of Annunziata in order to further prevent damage to the electrode during subsequent processes (Ha teaches #119 to have an overhang portion to prevent the variable resistance patterns #116 from damage during the oxidization process according to col. 8, ln. 16-32).
Regarding Claim 4, Kim in view of Annunziata teaches the method for fabricating the MTJ device of claim 1. 
Kim in view of Annunziata does not teaches the first protective layer is formed so that a thickness of an upper sidewall of the second electrode is greater than a thickness of a lower sidewall of the second electrode.
However, Ha teaches the first protective layer (#119, Figure 2 of Ha annotated) is formed so that a thickness of an upper sidewall (#T1, Figure 2 of Ha annotated, thickness of the protective layer #119 on an upper sidewall) of the second electrode (#115, Figure 2 of Ha annotated, top electrode) is greater than (see col.8, ln. 23-27) a thickness of a lower sidewall (#T2, Figure 2 of Ha annotated, thickness of #119 on a lower sidewall) of the second electrode (#115, Figure 2 of Ha annotated, top electrode).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to form the first protective layer of Kim in view of Annunziata (see claim 1 rejection) to have a thickness of an upper sidewall of the second electrode greater than a thickness of a lower sidewall of the second electrode as was done in Ha for the reasons set forth in the rejection of claim 3.

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Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0151502 A1; Kim et al.; 05/2021; (hereinafter “Kim”) in view of US 9705071 B2; Annunziata et al.; 07/2017; (hereinafter “Annunziata”) and further in view of US 2022/0131070 A1; Lin et al.; 04/2022; (hereinafter “Lin”).
Regarding Claim 10, Kim in view of Annunziata teaches the method of fabricating an MTJ device as described in Claim 9 further comprising: 
forming a second dielectric layer (Kim, #142, Figure 1, a second insulating interlayer) on the second protective layer (#140, Kim, Figure 1, #142 forms on #140); 
forming a third dielectric layer (Kim, #144, Figure 1, a third insulating interlayer) on the second dielectric layer (Kim, Figure 1, #144 forms on #142); and 
forming a second via (Kim, #150, Figure 1, a bit line comprises of metal and barrier patterns) in the third dielectric layer (Kim, Figure 1, #150 forms in #144), wherein the second via is electrically connected to the second electrode (Kim, Figure 1, #150 forms on top of and contacts the upper electrode #118a according to [0048]).
Kim in view of Annunziata does not teach planarizing the second dielectric layer. 
However, Lin teaches a method of fabricating MTJ device (Figure 2-3, [0026, 0030], method of fabricating MJT pillars structure includes at least etching the MTJ layers #111-#113 to form MTJ #130 and forming protection layers #109 to cover the MTJ). Lin further teaches planarizing the second dielectric layer (Figure 7, a planarization process is conducted on the second dielectric layer #602 which results in #602 being coplanar with the top surface of #601 or the top electrode #107 according to [0046]).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine the teaching of Kim in view of Annunziata with Lin so that the method comprises planarizing the second dielectric layer, as it would merely substitute a known method (initial forming of a flat dielectric layer) for another (subsequent planarizing the deposited dielectric layer) to obtain predictable results. (See MPEP 2143(I)(B))
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0151502 A1; Kim et al.; 05/2021; (hereinafter “Kim”) in view of US 9705071 B2; Annunziata et al.; 07/2017; (hereinafter “Annunziata”) and further in view of US 2017/0069834 A1; Annapragada et al.; 03/2017; (hereinafter “Annapragada”).
Regarding Claim 11, Kim in view of Annunziata teaches the method of fabricating an MTJ device as described in Claim 1. 
Kim in view of Annunziata does not teach repeating forming the first protective layer and performing the second ion beam etching process at least once.
However, Annapragada teaches a method for fabricating MTJ device ([0007], a method comprises etching an MTJ stack on a bottom electrode to form MTJ device), wherein the method further comprises repeating forming the first protective layer (Figure 3B, a sacrificial dielectric layer #16 is formed over the MTJ #12 and the bottom electrode #10) and performing the second ion beam etching process (Figure 3C-D, a second IBE process is used to remove the redeposition #18 on the sidewall of MTJ and the bottom electrode caused by the first IBE process) at least once (the process of depositing #16 followed by an IBE process is repeated multiple times to remove all sidewall redeposition according to [0032]).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine the teaching of Kim in view of Annunziata with Annapragada so that the method comprises repeating forming the first protective layer and performing the second ion beam etching process at least once for the reason set forth in rejection of claim 1 (also see [0022] of Annapragada).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
	US 20210074907 – Figure 10
US 20140042567 – Figure 24
US 20150340593 – Paragraph [0059]
US 20180033957 – Paragraph [0041]
US 20210175412 – Figure 8-9 
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIEN TRAN whose telephone number is (571)272-6967. The examiner can normally be reached Monday-Friday 8:30 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE S KIM can be reached on (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.





/TIEN TRAN/Examiner, Art Unit 2812                                                                                                                                                                                                        
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812                                                                                                                                                                                                        


    
        
            
        
            
        
            
        
            
        
            
        
            
        
            
        
            
        
            
        
            
        
            
        
            
    


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