Patent Application 17816055 - NOVEL METHOD OF FORMING WAFER-TO-WAFER BONDING

Title: NOVEL METHOD OF FORMING WAFER-TO-WAFER BONDING STRUCTURE
Application Information

Invention Title: NOVEL METHOD OF FORMING WAFER-TO-WAFER BONDING STRUCTURE
Application Number: 17816055
Submission Date: 2025-05-15T00:00:00.000Z
Effective Filing Date: 2022-07-29T00:00:00.000Z
Filing Date: 2022-07-29T00:00:00.000Z
National Class: 257
National Sub-Class: 459000
Examiner Employee Number: 98071
Art Unit: 2898
Tech Center: 2800
Rejection Summary

102 Rejections: 0
103 Rejections: 9
Cited Patents

The following patents were cited in the rejection:
Office Action Text



    DETAILED ACTION

Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Election/Restrictions
Applicant’s election without traverse of Group I Species 2 in the reply filed on 07 April 2025 is acknowledged.

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.


Claims 1-2, 5-6, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zvi Or-Bach et al. (US 2015/0348945 A1; hereinafter Or-Bach) in view of Sinan Goktepeli (US 10420171 B2; hereinafter Goktepeli).

Regarding Claim 1, Or-Bach teaches a method of forming a semiconductor structure, the method comprising: 
obtaining a composite wafer comprising a substrate (Fig. 7A; 700; ¶0137), an insulation layer (Fig. 7A; 701; ¶0137) on the substrate (700), and a first active layer (Fig. 7A; 702; ¶0137) on the insulation layer (701); 
forming a first device (Fig. 7A; NMOS devices comprising 707+705+704+706; ¶0137 which may be NMOS, PMOS, or CMOS devices; hereinafter NMOS for clarity) on a top surface of the first active layer (702) (as shown in Fig. 7A); 
attaching a first carrier (Fig. 7C; 720) over the first device with a first oxide-to-oxide bonding structure (Fig. 7C; 716; ¶0139); 
thinning the substrate (Fig. 7D; 700 is thinned; ¶0140) to expose a second active layer (exposed portion of 700 in Fig. 7D is the active layer for transistor formation; ¶0140); 
performing an alignment process (Fig. 7E; ¶0141) on a bottom surface of the second active layer (700) (as described in ¶0141 wherein the PMOS devices will be formed on the bottom are aligned to the top NMOS devices due to the shared substrate possessing the same alignment marks), the bottom surface of the second active layer (Fig. 7E; bottom of 700) and the top surface of the first active layer (Fig. 7E; top of 702) being at opposite sides of the insulation layer (701) (as shown in Fig. 7E); 
forming a second device (Fig. 7E; PMOS devices comprising 737+735+734+736; ¶0141; hereinafter PMOS for clarity) on the bottom surface of the second active layer (700; as shown in Fig. 7E), and a second interconnection structure (Fig. 7G; interconnect structure comprising 744 and 743; ¶0143; hereinafter ICS-2) below and coupled to the second device (as shown in Fig. 7G); 
attaching a second carrier (Fig. 7H; 108; ¶0144 and ¶0093) to the second interconnection structure (ICS-2) with a second oxide bonding structure (Fig. 7H; 748; ¶0143-¶0144); 
removing the first carrier (720) and the first oxide-to-oxide bonding structure (716) (as shown in Figs. 7I-7J); 
forming a via cavity (Fig. 7I; 747 via and metallization; ¶0143) through the first active layer (702), through the insulation layer (701), through the second active layer (700), and to one conductive feature of the second interconnection structure (to pad at bottom of 747); 
filling the via cavity with a metal material to form a via structure (as described in ¶0143, a via and metallization is process is performed in forming 747); and 
forming a first interconnection structure over and coupled to the first device (NMOS) (as shown in Fig. 7J and ¶0146; interconnect for NMOS comprising 763, 764, and 767; hereinafter ICS-1).

	Or-Bach is silent regarding implanting ions into the substrate (700) to form an etch stop layer in the substrate, and wherein thinning the substrate exposes the second active layer (exposed portion of 700 from Fig. 7D) that was between the insulation layer (701) and the etch stop layer.
	In the same field of endeavor, Goktepeli teaches a similar method of forming semiconductor devices on opposing sides of a substrate with interconnections (Fig. 4G) including obtaining a composite wafer comprising a substrate (Fig. 4A; 404+406+408), an insulation layer (Fig. 4A; 302) on the substrate, and a first active layer (Fig. 4A; 401) on the insulation layer (302), and forming an etch stop layer (Fig. 4A; 406) by ion implantation (Goktepeli; ¶0059), and thinning the substrate to expose a second active layer (Fig. 4C-4E; 404 is the second active layer) that was originally between the insulation layer (302) and the etch stop layer (406) (as shown in Figs. 4D-4E). 
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the etch stop layer of Goktepeli in the method of Or-Bach in order to protect the second active layer from damage during previous manufacturing steps. 
 
	Or-Bach is silent regarding wherein the second bonding structure (748) is an oxide-to-oxide bonding structure, but states in ¶0143 that (748) is an oxide layer deposited for bonding to the second carrier (108), and in ¶0139 that oxide layer (716) is used for oxide-to-oxide bonding of the first carrier (720).
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use oxide-to-oxide bonding for oxide layer (748) in the same manner as the oxide-to-oxide bonding of oxide layer (716), because they are both oxide layers with art recognized suitability for being used to bond the device to a carrier wafer.

	Or-Bach is silent regarding wherein the via structure connects the first device (NMOS) to the second device (PMOS). 
In the same field of endeavor, Goktepeli teaches in Fig. 6 connecting a frontside device (612; ¶0086) to a backside device (614; ¶0086) with a metallization structure (634; ¶0086) that extends through the insulation layer (BOX) of the dual side configured device (Fig. 6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to connect the frontside (NMOS) devices to the backside (PMOS) devices of Or-Bach in the manner of Goktepeli in order to form a high performance CMOS device.  

Regarding Claim 2, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, wherein: 
the first active layer (702) has a first back surface opposite the top surface of the first active layer, the second active layer (700) has a second back surface opposite the bottom surface of the second active layer, and 
the insulation layer (701) is located between and in contact with the first back surface and the second back surface to isolate the first device (NMOS) formed on the first active layer (702) and the second device (PMOS) formed on the second active layer (700) (as shown in Or-Bach Fig. 7J).

Regarding Claim 5, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, but Goktepeli is silent regarding wherein the etch stop layer (Goktepeli; Fig. 4A; 406) comprises silicon germanium (SiGe), and the ions implanted into the substrate to form the etch stop layer include germanium ions.
However, Or-Bach teaches the generic process in Fig. 2, including forming a heavily dopes 1e20 atoms/cm3 SiGe layer as an etch stop layer in the ion-cut process flow in various configurations (Or-Bach ¶0109).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Goktepeli and Or-Bach to use germanium ions to form the SiGe etch stop layer because of the art recognized suitability for the intended use as an etch stop layer in a wafer bonding and dual side device formation method (Goktepeli; Fig. 4A; ¶0059-¶0066 and Or-Bach; Fig. 2; ¶0109). 

Regarding Claim 6, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, wherein thinning the substrate comprises: removing a portion of the substrate under the etch stop layer (as modified by Goktepeli; portion 408 under the etch stop layer 406 is removed exposing 406, Fig. 4D); and removing the etch stop layer (Goktepeli; 406; Fig. 4E) so that a remaining portion of the substrate (Goktepeli; 404; Fig. 4E) constitutes the second active layer and the bottom surface of the second active layer (404) is exposed (as shown in Fig. 4E and ¶0068 of Goktepeli).

Regarding Claim 13, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, wherein the first device or the second device comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAAFET), a diode, a capacitor, a resistor, or an inductor (as described in Or-Bach ¶0148).

Claim 3-4, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach in view of Goktepeli and Michael J. Ries et al. (US 2017/0025307 A1; hereinafter Ries).

Regarding Claim 3, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, wherein obtaining the composite wafer comprises: 
providing a first wafer (Or-Bach; Fig. 7B; first wafer 700 below 701) and a second wafer (Fig. 7B; wafer above 701 comprising the layer 702), 
implanting hydrogen ions (Or-Bach; Fig. 7B; 710; ¶0138) into the first wafer (700) to embrittle the first wafer beneath the oxide layer (701) (as described in ¶0138-¶0140); and 
splitting the first wafer (700) at a peak location (712) of the implanted hydrogen ions (710), wherein the second wafer (702), the oxide layer (701) on the second wafer and a remaining portion of the first wafer (remaining portion of 700 as shown in Fig. 7D) constitute the substrate, the insulation layer and the first active layer of the composite wafer, respectively (as shown in Figs. 7A to 7D).
Or-Bach is silent regarding wherein an oxide layer is formed around the first wafer (700), bonding the first wafer to the second wafer (702) through the oxide layer (701), and splitting the first wafer at (712) by using an annealing process. 
In the same field of endeavor, Ries teaches in Figs. 1-4 a wafer bonding and layer separation process comprising forming an oxide layer (¶0021, 15 may be a native oxide formed by exposure to atmosphere and therefore is formed around the wafer) on a first wafer (12; ¶0020) implanted with hydrogen ions (¶0024-¶0026) to weaken the first wafer beneath the oxide (15), then bonding the first wafer (12) to a second wafer (Fig. 3; 10; ¶0033-¶0039), and splitting the first wafer (12) at the weakened portion (17) by an annealing process (¶0040-¶0044) to leave a device layer (Fig. 4; 25; ¶0042). 
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the details of Ries in the method of Or-Bach in order to reduce thermal voids at the bond interface and reduce cost (Ries; ¶0016).

Regarding Claim 4, modified Or-Bach teaches the method as claimed in claim 3, but does not expressly disclose wherein implanting the ions into the substrate to form the etch stop layer (Goktepeli; Fig. 4A; 406) is performed after bonding the first wafer to the second wafer.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try implanting the ions into the substrate with one of only two options of (before or after) bonding the substrates with reasonable chance of success at obtaining the configuration of Fig. 4A of Goktepeli without undue experimentation (MPEP 2143 I E). 

Regarding Claim 21, Or-Bach teaches a method of forming a semiconductor structure, the method comprising:
obtaining a composite wafer comprising a substrate (Fig. 7A; 700; ¶0137), an insulation layer (Fig. 7A; 701; ¶0137) on the substrate (700), and a first active layer (Fig. 7A; 702; ¶0137) on the insulation layer (701), wherein obtaining the composite wafer comprises:
providing a first wafer (Or-Bach; Fig. 7B; first wafer 700 below 701) and a second wafer (Fig. 7B; wafer above 701 comprising the layer 702), wherein an oxide (7091 is an oxide layer) layer is formed on the first wafer;
implanting hydrogen ions (Or-Bach; Fig. 7B; 710; ¶0138) into the first wafer (700) to embrittle the first wafer beneath the oxide layer (701) (as described in ¶0138-¶0140); and
splitting the first wafer (700) at a peak location (712) of the implanted hydrogen ions (710), wherein the second wafer (702), the oxide layer (701) on the second wafer and a remaining portion of the first wafer (remaining portion of 700 as shown in Fig. 7D) constitute the substrate, the insulation layer and the first active layer of the composite wafer, respectively (as shown in Figs. 7A to 7D);
forming a first device (Fig. 7A; NMOS devices comprising 707+705+704+706; ¶0137 which may be NMOS, PMOS, or CMOS devices; hereinafter NMOS for clarity) on a top surface of the first active layer (702) (as shown in Fig. 7A);
attaching a first carrier (Fig. 7C; 720) over the first device (NMOS; as shown in Fig. 7C);
removing a portion of the substrate (700) so that a remaining portion of the substrate under the insulation layer (701) forms a second active layer (exposed portion of 700 in Fig. 7D is the active layer for transistor formation; ¶0140);
forming a second device (Fig. 7E; PMOS devices comprising 737+735+734+736; ¶0141; hereinafter PMOS for clarity) on a bottom surface of the second active layer (700; as shown in Fig. 7E), and a second interconnection structure (Fig. 7G; interconnect structure comprising 744 and 743; ¶0143; hereinafter ICS-2) below and coupled to the second device (as shown in Fig. 7G);
attaching a second carrier (Fig. 7H; 108; ¶0144 and ¶0093) over the second interconnection structure (ICS-2) (as shown in Fig. 7H);
removing the first carrier (720) (as shown in Figs. 7I-7J);
forming a via structure (Fig. 7I-7J; 747+767 via and metallization; ¶0143) extending through the first active layer (702), the insulation layer (701) and the second active layer (700) and coupled to one conductive feature of the second interconnection structure (bottom pad of 747 in ICS-2); and
forming a first interconnection structure over and coupled to the first device (NMOS) (as shown in Fig. 7J and ¶0146; interconnect for NMOS comprising 763, 764, and 767; hereinafter ICS-1).

Or-Bach is silent regarding wherein an oxide layer is formed around the first wafer (700), bonding the first wafer to the second wafer (702) through the oxide layer (701), and splitting the first wafer at (712) by using an annealing process. 
In the same field of endeavor, Ries teaches in Figs. 1-4 a wafer bonding and layer separation process comprising forming an oxide layer (¶0021, 15 may be a native oxide formed by exposure to atmosphere and therefore is formed around the wafer) on a first wafer (12; ¶0020) implanted with hydrogen ions (¶0024-¶0026) to weaken the first wafer beneath the oxide (15), then bonding the first wafer (12) to a second wafer (Fig. 3; 10; ¶0033-¶0039), and splitting the first wafer (12) at the weakened portion (17) by an annealing process (¶0040-¶0044) to leave a device layer (Fig. 4; 25; ¶0042). 
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the details of Ries in the method of Or-Bach in order to reduce thermal voids at the bond interface and reduce cost (Ries; ¶0016).

Or-Bach is silent regarding implanting ions into the substrate (700) to form an etch stop layer in the substrate, and wherein thinning the substrate exposes the second active layer (exposed portion of 700 from Fig. 7D) that was between the insulation layer (701) and the etch stop layer.
	In the same field of endeavor, Goktepeli teaches a similar method of forming semiconductor devices on opposing sides of a substrate with interconnections (Fig. 4G) including obtaining a composite wafer comprising a substrate (Fig. 4A; 404+406+408), an insulation layer (Fig. 4A; 302) on the substrate, and a first active layer (Fig. 4A; 401) on the insulation layer (302), and forming an etch stop layer (Fig. 4A; 406) by ion implantation (Goktepeli; ¶0059), and thinning the substrate to expose a second active layer (Fig. 4C-4E; 404 is the second active layer) that was originally between the insulation layer (302) and the etch stop layer (406) (as shown in Figs. 4D-4E). 
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the etch stop layer of Goktepeli in the method of Or-Bach in order to protect the second active layer from damage during previous manufacturing steps. 

Or-Bach is silent regarding wherein the via structure connects the first device (NMOS) to the second device (PMOS). 
In the same field of endeavor, Goktepeli teaches in Fig. 6 connecting a frontside device (612; ¶0086) to a backside device (614; ¶0086) with a metallization structure (634; ¶0086) that extends through the insulation layer (BOX) of the dual side configured device (Fig. 6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to connect the frontside (NMOS) devices to the backside (PMOS) devices of Or-Bach in the manner of Goktepeli in order to form a high performance CMOS device.  

Regarding Claim 23, modified Or-Bach teaches the method as claimed in claim 21, wherein:
the first active layer (702) has a first back surface opposite the top surface of the first active layer, the second active layer (700) has a second back surface opposite the bottom surface of the second active layer, and 
the insulation layer (701) is located between and in contact with the first back surface and the second back surface to isolate the first device (NMOS) formed on the first active layer (702) and the second device (PMOS) formed on the second active layer (700) (as shown in Or-Bach Fig. 7J).


Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach in view of Goktepeli and Cheng-Ying Ho et al. (US 2016/0020170 A1; hereinafter Ho).

Regarding Claim 7, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, further comprising: forming a first oxide layer (Fig. 7C; 716) over the first device (NMOS) on the top surface of the first active layer (702); but does not expressly disclose forming a second oxide layer over the first carrier (720); and placing the first carrier (720) over the first device (NMOS) so that the first oxide layer (716) is in contact with the second oxide layer to form the first oxide-to-oxide bonding structure (¶0139 described oxide-to-oxide bonding between the carrier and device).
	In the same field of endeavor, Ho teaches bonding two device wafers (Fig. 1; 110 and 210) together in an oxide-to-oxide bonding process, wherein the surface layers of each device are oxide layers (Ho; ¶0020).
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have an oxide layer on the surface of each wafer (as in Ho; ¶0020) in the method of Or-Bach in order to facilitate the oxide-to-oxide bonding disclosed by Or-Bach (¶0139) to make a good oxide bond.

Regarding Claim 10, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, but does not expressly disclose further comprising: forming a third oxide layer on the second interconnection structure (ICS-2 which is the lower interconnect structure); forming a fourth oxide layer over the second carrier (108); and placing the second carrier (108) under the second interconnection structure (ICS-2) (as shown in Fig. 7H) so that the third oxide layer is in contact with the fourth oxide layer to form the second oxide-to-oxide bonding structure (oxide layer 748 is between the carrier 108 and ICS-2 to facilitate bonding as described in ¶0143).
In the same field of endeavor, Ho teaches bonding two device wafers (Fig. 1; 110 and 210) together in an oxide-to-oxide bonding process, wherein the surface layers of each device/wafer comprise oxide layers (Ho; ¶0020).
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have an oxide layer on the surface of each wafer (Or-Bach; ICS-2 and 108) (as in Ho; ¶0020) in the method of Or-Bach in order to facilitate the oxide-to-oxide bonding disclosed by Or-Bach (¶0139) to make a good oxide bond.


Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach in view of Goktepeli, Ho, and Andrew M. Bayless (US 2021/0183803 A1; hereinafter Bayless).

Regarding Claim 8, modified Or-Bach teaches the method as claimed in claim 7, but does not expressly disclose further comprising: forming a de-bonding layer over the first carrier (720) before the second oxide layer is formed over the first carrier; and decomposing the de-bonding layer before the first carrier (720) and the first oxide-to-oxide bonding structure (716) are removed from the first device (NMOS).
In the same field of endeavor; Bayless teaches a method of forming a debonding layer (Bayless; Fig. 4; 112; ¶0020 and ¶0028) before forming an oxide layer (Fig. 4; 114) over a first carrier wafer (Fig. 4 in view of Fig. 1A; 110), and decomposing the de-bonding layer (112 and as described in ¶0056) before removing the carrier (110) and the oxide-to-oxide bonding structure (114; ¶0032 and ¶0040 and as shown in Fig. 5-7).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the de-bonding layer of Bayless in the method of Or-Bach in order to facilitate easy removal of the first carrier while protecting the IC device (Bayless; ¶0057).


Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach in view of Goktepeli and John F. McDonald (US 2015/0145144 A1; hereinafter McDonald).

Regarding Claim 9, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, but does not expressly disclose the details of wherein performing the alignment process on the bottom surface of the second active layer (700) comprises: obtaining a position of a first active region (702 NMOS) on the top surface of the first active layer (702) using an optical method from the bottom surface of the second active layer (700); and determining a position of a second active region (700 PMOS) on the bottom surface of the second active layer using the optical method, wherein the second active region (700 PMOS) is aligned with the first active region (702 NMOS) (as shown in Fig. 7E and ¶0141), and wherein the first device (NMOS) is formed in the first active region (702 NMOS) and the second device (PMOS) is formed in the second active region (702 PMOS).
Or-Bach does not expressly disclose using an optical method for the alignment (in the embodiment of Fig. 7A-7K) of the PMOS region (bottom) to the NMOS region from the bottom, but does acknowledge using optical alignment in ¶0121. 
	In the same field of endeavor, McDonald teaches in Fig. 3C bonding two device  stacks together (301 and 311 by bonding layer 320) and thinning one of the substrates (310; ¶0034) to improve transparency in order to aid in optical alignment of the two device stacks for bonding/processing through the substrate. 
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the optical alignment method of McDonald in the method of Or-Bach, because Or-Bach acknowledges use of optical alignment methods (Or-Bach; ¶0121) and thins the substrate (Fig. 7C; 700 thinned along 712) in a similar manner as McDonald. This is an obvious substitution of one known method for its art recognized suitability for aligning two devices/stacks through a substrate. 


Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach in view of Goktepeli and Chun-Wen Cheng et al. (US 2015/0329351 A1; hereinafter Cheng).

Regarding Claim 11, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, but does not expressly disclose further comprising: forming a polymer layer over the first interconnection structure, wherein the polymer layer has a plurality of openings exposing contact pads of the first interconnection structure; and forming a plurality of conductive connectors over the polymer layer and in the openings to connect the contact pads.
In the same field of endeavor, Cheng teaches a method of forming external interconnections to a device comprising: forming a polymer layer (Fig. 14; 1401; ¶0037) over the first interconnection structure (501 including the interconnections; ¶0023), wherein the polymer layer (1401) has a plurality of openings (1402) exposing contact pads (Fig. 14; contacts 1303; ¶0036) of the first interconnection structure (501); and forming a plurality of conductive connectors (1Fig. 15; 1505+1503; ¶0037) over the polymer layer (1401) and in the openings (1402) to connect the contact pads (1303) (as shown in Cheng Fig. 15).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the external connection features of the CMOS device of Cheng in the CMOS device of Or-Bach in order to provide a good external connection for the device package. 

Regarding Claim 12, Or-Bach modified by Goktepeli teaches the method as claimed in claim 1, but does not expressly disclose further comprising: removing the second carrier (108) and the second oxide-to-oxide bonding structure (748) from the second interconnection structure (ICS-2); forming a polymer layer below the second interconnection structure, wherein the polymer layer has a plurality of openings exposing contact pads of the second interconnection structure; and forming a plurality of conductive connectors below the polymer layer and in the openings to connect the contact pads.
In the same field of endeavor, Cheng teaches a method of forming external interconnections to a device comprising: forming a polymer layer (Fig. 14; 1401; ¶0037) over the first interconnection structure (501 including the interconnections; ¶0023), wherein the polymer layer (1401) has a plurality of openings (1402) exposing contact pads (Fig. 14; contacts 1303; ¶0036) of the first interconnection structure (501); and forming a plurality of conductive connectors (1Fig. 15; 1505+1503; ¶0037) over the polymer layer (1401) and in the openings (1402) to connect the contact pads (1303) (as shown in Cheng Fig. 15).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to remove the second carrier (108) and second oxide-to-oxide bonding structure (748) to form the external connection features of the CMOS device of Cheng in the CMOS device of Or-Bach in order to provide a good external connection for the device package. 


Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach in view of Goktepeli, Ho, and McDonald.

Regarding Claim 14, Or-Bach teaches a method of forming a semiconductor structure, the method comprising: 
obtaining a composite wafer comprising a substrate (Fig. 7A; 700; ¶0137), an insulation layer (Fig. 7A; 701; ¶0137) on the substrate (700), and a first active layer (Fig. 7A; 702; ¶0137) on the insulation layer (701); 
forming a first device (Fig. 7A; NMOS devices comprising 707+705+704+706; ¶0137 which may be NMOS, PMOS, or CMOS devices; hereinafter NMOS for clarity) in a first active region (region of 702 comprising 706+707) on a top surface of the first active layer (portions of device on top comprise 705+704 Fig. 7A); 
forming a second oxide layer (Fig. 7C; 716; ¶0139) over a first carrier (Fig. 7C; 720; ¶0139), and attaching the first carrier (720) over the first device through a bonding of the second oxide layer (716) (as shown in Fig. 7C and described as oxide-to-oxide bonding in ¶0139); 
removing a portion of the substrate (700) so that a remaining portion of the substrate (700) under the insulation layer (701) forms a second active layer (as shown in Fig. 7D; 700 is the remaining portion and is an active layer to form PMOS devices; ¶0140-¶0141); 
obtaining a position of the first active region (of NMOS) of the first active layer using an alignment method from a bottom surface of the second active layer (as described in ¶0141 and Fig. 7D-7E), and determining a position of a second active region (Fig. 7E; second active region comprising 136+737 of PMOS transistors) on the bottom surface of the second active layer using the alignment method (¶0141), wherein the second active region is aligned with the first active region (as shown in Fig. 7E; the active regions of the NMOS {top} transistors and PMOS {bottom} transistors are aligned); 
forming a second device (Fig. 7E; PMOS device comprising 736+737+735+734; hereinafter PMOS) in the second active region on the bottom surface of the second active layer (as shown in Fig. 7E), and a second interconnection structure below and coupled to the second device (as shown in Fig. 7G; wherein the second interconnect structure coupled to PMOS comprises 744+743; hereinafter ICS-2); 
forming a third oxide layer (Fig. 7G; 748; ¶0143 used to prepare for bonding) below the second interconnection structure (as shown in Fig. 7G); 
providing a second carrier (Fig. 7H; 108; ¶0144 and ¶0093), and attaching the second carrier (108) to the second interconnection structure (ICS-2) through a bonding of the third oxide layer (748 as shown in Fig. 7H); 
removing the first carrier (720; as shown in Fig. 7H to 7I), and the second oxide layer (716) (as shown in Fig. 7I and 7J); forming a via cavity through the first active layer (702), through the insulation layer (701), through the second active layer (700), and to one conductive feature (bottom pad of 747) of the second interconnection structure (ICS-2) (via cavity and metallization performed to form 747 as described in ¶0143-¶0146); 
filling the via cavity with a metal material (¶0143-0146) to form a via structure (747+767); and 
forming a first interconnection structure over and coupled to the first device (Fig. 7J; first interconnect structure {hereinafter ICS-1} comprises 764+763 and is coupled to the NMOS devices).

Or-Bach is silent regarding wherein an etch stop layer is formed in the substrate at a distance from a bottom surface of the substrate.
In the same field of endeavor, Goktepeli teaches a similar method of forming semiconductor devices on opposing sides of a substrate with interconnections (Fig. 4G) including obtaining a composite wafer comprising a substrate (Fig. 4A; 404+406+408), an insulation layer (Fig. 4A; 302) on the substrate, and a first active layer (Fig. 4A; 401) on the insulation layer (302), and forming an etch stop layer (Fig. 4A; 406) by ion implantation (Goktepeli; ¶0059), and thinning the substrate to expose a second active layer (Fig. 4C-4E; 404 is the second active layer) that was originally between the insulation layer (302) and the etch stop layer (406) (as shown in Figs. 4D-4E). 
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the etch stop layer of Goktepeli in the method of Or-Bach in order to protect the second active layer from damage during previous manufacturing steps. 

Or-Bach is silent regarding forming two oxide layers (one over each first/second device and first/second carrier) for bonding a first/second carrier to the NMOS/PMOS devices/wafers, respectively.
In the same field of endeavor, Ho teaches bonding two device wafers (Fig. 1; 110 and 210) together in an oxide-to-oxide bonding process, wherein the surface layers of each device comprise oxide layers (Ho; ¶0020).
	It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have an oxide layer on the surface of each wafer (carrier and NMOS/PMOS side) (as in Ho; ¶0020) in the method of Or-Bach in order to facilitate the oxide-to-oxide bonding disclosed by Or-Bach (¶0139) to make a good oxide bond between the carrier and the respective side of the device wafer.

Or-Bach does not expressly disclose using an optical method for the alignment (in the embodiment of Fig. 7A-7K) of the PMOS region (bottom) to the NMOS region (top) from the bottom, but does acknowledge using optical alignment in ¶0121. 
In the same field of endeavor, McDonald teaches in Fig. 3C bonding two device  stacks together (301 and 311 by bonding layer 320) and thinning one of the substrates (310; ¶0034) to improve transparency in order to aid in optical alignment of the two device stacks for bonding/processing through the substrate. 
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the optical alignment method of McDonald in the method of Or-Bach, because Or-Bach acknowledges use of optical alignment methods (Or-Bach; ¶0121) and thins the substrate (Fig. 7C; 700 thinned along 712) in a similar manner as McDonald. This is an obvious substitution of one known method for its art recognized suitability for aligning two devices/stacks through a substrate. 

Or-Bach is silent regarding the via structure connects the first device (NMOS) and the second device (PMOS).
In the same field of endeavor, Goktepeli teaches in Fig. 6 connecting a frontside device (612; ¶0086) to a backside device (614; ¶0086) with a metallization structure (634; ¶0086) that extends through the insulation layer (BOX) of the dual side configured device (Fig. 6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to connect the frontside (NMOS) devices to the backside (PMOS) devices of Or-Bach in the manner of Goktepeli in order to form a high performance CMOS device.  

Regarding Claim 15, modified Or-Bach teaches the method as claimed in claim 14, further comprising: forming a first inter-layer dielectric (ILD) layer (Fig. 7A; 708; ¶0137) covering the first device (NMOS) prior to forming the first oxide layer (716) (as shown in Fig. 7A and 7C); and forming a second inter-layer dielectric layer (Fig. 7E; 738; ¶0141) covering the second device (PMOS) prior to forming the third oxide layer (748) (as shown in Fig. 7E and 7G).

Regarding Claim 16, modified Or-Bach teaches the method as claimed in claim 15, wherein the via structure (747+767) also passes through the first inter-layer dielectric layer (708) and the second inter-layer dielectric layer (738) (as shown in Fig. 7G and 7J).


Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach in view of Goktepeli, Ho, McDonald, and Cheng.

Regarding Claim 17, modified Or-Bach teaches the method as claimed in claim 14, but does not expressly disclose further comprising: forming a polymer layer over the first interconnection structure (ICS-1), wherein the polymer layer has a plurality of openings exposing contact pads of the first interconnection structure; and forming a plurality of conductive connectors over the polymer layer and in the openings to connect the contact pads.
In the same field of endeavor, Cheng teaches a method of forming external interconnections to a device comprising: forming a polymer layer (Fig. 14; 1401; ¶0037) over the first interconnection structure (501 including the interconnections; ¶0023), wherein the polymer layer (1401) has a plurality of openings (1402) exposing contact pads (Fig. 14; contacts 1303; ¶0036) of the first interconnection structure (501); and forming a plurality of conductive connectors (1Fig. 15; 1505+1503; ¶0037) over the polymer layer (1401) and in the openings (1402) to connect the contact pads (1303) (as shown in Cheng Fig. 15).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the external connection features of the CMOS device of Cheng in the CMOS device of Or-Bach in order to provide a good external connection for the device package. 


Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach in view of Goktepeli, Ries, and McDonald.

Regarding Claim 22, modified Or-Bach teaches the method as claimed in claim 21, further comprising:
performing an alignment process (Fig. 7E; ¶0141), comprising:
obtaining a position of a first active region (of NMOS) on the top surface of the first active layer using a method from the bottom surface of the second active layer (as described in ¶0141 and Fig. 7D-7E); and
determining a position of a second active region (Fig. 7E; second active region comprising 136+737 of PMOS transistors) on the bottom surface of the second active layer using the method, wherein the second active region is aligned with the first active region (as shown in Fig. 7E; the active regions of the NMOS {top} transistors and PMOS {bottom} transistors are aligned), and wherein the first device (NMOS) is formed in the first active region and the second device (PMOS) is formed in the second active region (as shown in Fig. 7J).
Or-Bach does not expressly disclose using an optical method for the alignment (in the embodiment of Fig. 7A-7K) of the PMOS region (bottom) to the NMOS region from the bottom, but does acknowledge using optical alignment in ¶0121. 
	In the same field of endeavor, McDonald teaches in Fig. 3C bonding two device  stacks together (301 and 311 by bonding layer 320) and thinning one of the substrates (310; ¶0034) to improve transparency in order to aid in optical alignment of the two device stacks for bonding/processing through the substrate. 
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the optical alignment method of McDonald in the method of Or-Bach, because Or-Bach acknowledges use of optical alignment methods (Or-Bach; ¶0121) and thins the substrate (Fig. 7C; 700 thinned along 712) in a similar manner as McDonald. This is an obvious substitution of one known method for its art recognized suitability for aligning two devices/stacks through a substrate.


Conclusion
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NATHAN PRIDEMORE
Examiner
Art Unit 2898



/NATHAN PRIDEMORE/Examiner, Art Unit 2898                                                                                                                                                                                                        /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898