Patent Application 17750417 - METHOD OF FORMING SEMICONDUCTOR PACKAGES HAVING

Title: METHOD OF FORMING SEMICONDUCTOR PACKAGES HAVING THERMAL THROUGH VIAS (TTV)
Application Information

Invention Title: METHOD OF FORMING SEMICONDUCTOR PACKAGES HAVING THERMAL THROUGH VIAS (TTV)
Application Number: 17750417
Submission Date: 2025-04-10T00:00:00.000Z
Effective Filing Date: 2022-05-23T00:00:00.000Z
Filing Date: 2022-05-23T00:00:00.000Z
National Class: 438
National Sub-Class: 110000
Examiner Employee Number: 97904
Art Unit: 2898
Tech Center: 2800
Rejection Summary

102 Rejections: 1
103 Rejections: 2
Cited Patents

The following patents were cited in the rejection:
US 0322330🔗
US 0304910🔗
Office Action Text


    DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 02/18/2025 has been entered. Applicant's amendment to the Claims have overcome the 112(b) rejection previously set forth in the Non-Final Office Action dated on 11/19/2024.  
Claim status
Claims 1-20 are pending.

	Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the "Amendment/Req. Reconsideration-After Non-Final Reject" filed on 02/18/2025, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with US 2016/0322330 A1 to Lin reference, of the record and a new reference, US 2019/0304910 A1 to Fillion, being used in the current rejection, see detail below.	

Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.


Claims 1-4, 6, 15-17 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al. (US 2016/0322330 A1, hereinafter Lin, of the record).
Regarding independent claim 1, Lin teaches a method of forming a semiconductor package (200, Fig. 4), comprising: 
forming a redistribution layer structure (108A, B, C RDLs in [0021, 0022], Fig. 4) over a first die (102 a die in [0013], Fig. 4) and a dummy die (106 a dummy die in [0016], Fig. 4), wherein the redistribution layer structure (108A, C) is directly electrically connected (108A, C, 108A connected to 102, Fig. 4) to the first die (102); 
forming an insulating layer (124-101B molding compound in 101B in [0013], Fig. 4, Lin), wherein the insulating layer (124-101B) is disposed opposite (as showed in Fig. 6f) to the redistribution layer structure (108A, C, 124-101B opposite to 108A, Fig. 4) with respect to the first die (102); and 
forming at least one thermal through via (TIVs in 101B in [0022]) in the insulating layer (124-101B), wherein the at least one thermal through via (TIVs) extends ([0022]) from a topmost surface of the insulating layer (124-101B) to a bottommost surface of the insulating layer (124-101B).

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Lin’s Figure 4-Annotated.

Regarding claim 2, Lin discloses the method as claimed in claim 1, wherein the dummy die (106) is electrically connected (106 connected to 102 through 108A, Fig. 4) to the first die (102) through the redistribution layer structure (108A, C).
Regarding claim 3, Lin discloses the method as claimed in claim 1, further comprising forming at least one through via (126 a TIVs via extending through molding compound 124 in 101A in [0017], Fig. 4) aside the first die (102) between (126 between 108A and TIVs, Fig. 4) the redistribution layer structure (108A, C) and the at least one thermal through via (TIVs in 101B).
Regarding claim 4, Lin discloses the method as claimed in claim 1, further comprising forming connectors (120 external connectors in [0020], Fig. 4) over the redistribution layer structure (108A, C).
Regarding claim 6, Lin discloses the method as claimed in claim 1, further comprising forming other redistribution layer structure (108B RDLs in [0021], Fig. 4) between the insulating layer (124-101B) and the first die (102) and the dummy die (106), wherein the at least one thermal through via (TIVs in 101B) is electrically connected to the redistribution layer structure (108A, C) through the other redistribution layer structure (108B).

Regarding independent claim 15, Lin teaches a method of forming a semiconductor package, comprising: 
forming at least one first through via (126 a TIVs via extending through molding compound 124 in 101A in [0017], Fig. 4) on a redistribution layer structure (108A, B, C RDLs in [0021, 0022], Fig. 4) over a carrier (carrier a carrier over 108C in [0029]); 
encapsulating (TIVs via extending through molding compound 124 in [0017], Fig. 3F) the at least one first through via (126) with an encapsulant (124-101A) over the carrier (carrier); and 
forming at least one thermal through via (TIVs in 101B in [0022]) over the redistribution layer structure (108A, B, C, over 108C) and the encapsulant (124-101A), wherein the redistribution layer structure (108A, B, C) is electrically connected (in [0021,0022]) to the at least one first through via (126) and the at least one thermal through via (TIVs in 101B).
Regarding claim 16, Lin discloses the method as claimed in claim 15, further comprising forming a die (102 a die in [0017], Fig. 14) aside the at least one first through via (126) in the encapsulant (124-101A), wherein the at least one thermal through via (TIVs) is electrically connected (TIVs is connected to 102 through 108B, 108A and 126, Fig. 6g) to the die (102) through the at least one first through via (126).
Regarding claim 17, Lin discloses the method as claimed in claim 16, further comprising forming a die attach film (118 a die attach film in [0021], Fig. 4) between the die (102) and the at least one thermal through via (TIVs formed in 101B, in [0022]).
Regarding claim 20, Lin discloses the method as claimed in claim 15, wherein surfaces of the at least one first through via (126) and the encapsulant (124-101A) are substantially coplanar (as showed in Fig. 4).

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.


Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin.
Regarding claim 5, Lin discloses the method as claimed in claim 4, 
Lin does not disclose wherein the first die is disposed in a first region, the dummy die is disposed in a second region, a density of the connectors in the first region is equal to the number of the connectors in the first region divided by an area of the first region, a density of the connectors in the second region is equal to the number of the connectors in the second region divided by an area of the second region, and the density of the connectors in the second region is larger than the density of the connectors in the first region.
However, the Applicant has not presented persuasive evidence that the claimed
“density of the connectors in the second region larger than the density of the connectors in the first region” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed density of the connectors in the second region larger than the density of the connectors in the first region). Also, the applicant has not shown that the claimed “difference of density of the connectors in the second region respect to the density of the connectors in the first region” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Lin discloses “a density of the connectors in the second region similar to the density of the connectors in the first region”, Fig. 4, therefore, the density is a result effective variable. It has been held that is not inventive to discover the optimum density of the connectors in the second region respect to the density of the connectors in the first region by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II). Thus, it would have been obvious to add the density of the connectors in the second region is larger than the density of the connectors in the first region to include more electronic devices.	
Regarding claim 7, Lin discloses the method as claimed in claim 4, 
Lin does not disclose wherein the first die is disposed in a first region, the dummy die is disposed in a second region, a density of the at least one thermal through via in the first region is equal to the number of the at least one thermal through via in the first region divided by an area of the first region, a density of the at least one thermal through via in the second region is equal to the number of the at least one thermal through via in the second region divided by an area of the second region, and the density of the at least one thermal through via in the first region is larger than the density of the at least one thermal through via in the second region.
However, the Applicant has not presented persuasive evidence that the claimed
“density of the at least one thermal through via in the first region larger than the density of the at least one thermal through via in the second region” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed density of the at least one thermal through via in the first region larger than the density of the at least one thermal through via in the second region). Also, the applicant has not shown that the claimed “difference of density of the at least one thermal through via in the first region respect to the density of the at least one thermal through via in the second region” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Lin discloses “a density of thermal through via in 101B”, Fig. 4-Annotated, therefore, the density is a result effective variable. It has been held that is not inventive to discover the optimum density of the at least one thermal through via in the first region respect to the density of the at least one thermal through via in the second region by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II). Thus, it would have been obvious to add density of the at least one thermal through via in the first region larger than the density of the at least one thermal through via in the second region to include more electronic devices.	
Claims 8-14 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Fillion et al. (US 2019/0304910 A1, hereinafter Fillion).
Regarding independent claim 8, Lin discloses a method of forming a semiconductor package, comprising: 
providing a first die (102 a die in [0013], Fig. 4) with paste (118 glue layer in [0021], Fig. 4) thereon; and 
forming at least one thermal through via (TIVs in 101B in [0022]) over the first die (102) and the paste (118), wherein the paste (118) is disposed between the first die (102) and the at least one thermal through via (351), and the at least one thermal through via (TIVs in 101B) is electrically connected to the first die (102) through the 0 paste (118).
Lin does not expressly disclose wherein the paste (118) is a conductive paste.
However, in the same semiconductor device field of endeavor, Fillion discloses a conductive joining layer (125 made of silver paste in [0075], Fig. 21) between the die (12 in [0075]) and the electrical interconnect structure (138 in [0075]).
It would have been obvious to one of ordinary skill in the art, at the time the invention was filed to make the Lin’s paste layer a conductive paste layer according to Fillion’s method to make flexible thermal connection.
Regarding claim 9, Lin modified by Fillion discloses the method as claimed in claim 8, wherein the conductive paste (118’s Lin after applied Fillion) is in direct contact (as showed in Fig. 4) with the first die (102).
Regarding claim 10, Lin modified by Fillion discloses the method as claimed in claim 8, further comprising forming a dummy die (106 a dummy die in [0016], Fig. 4) aside the first die (102).
Regarding claim 11, Lin modified by Fillion discloses the method as claimed in claim 10, wherein the conductive paste (118’s Lin after applied Fillion) is further in direct contact (Fig. 4) with the dummy die (106’s Lin).
Regarding claim 12, Lin modified by Fillion discloses the method as claimed in claim 8, further comprising forming a redistribution layer structure (108A, B, C RDLs in [0021, 0022], Fig. 4, Lin) electrically connected (as showed in Fig. 4) to the first die (102, Lin), wherein the redistribution layer structure (108A, B, C, Lin) and the at least one thermal through via (TIVs, Lin) are disposed at opposite sides (as showed in Fig. 4) of the first die (102).
Regarding claim 13, Lin modified by Fillion discloses the method as claimed in claim 12, wherein further comprising forming a plurality of connectors (120 external connectors in [0020], Fig. 4), wherein the redistribution layer structure (108A, B, C, Lin) is disposed between the connectors (120) and the first die (102).
Regarding claim 14, Lin modified by Fillion discloses the method as claimed in claim 8, further comprising forming an insulating layer (124 molding compound in 101B in [0013], Fig. 4, Lin) surrounding the at least one thermal through via (TIVs, Lin).
Regarding claim 18, Lin discloses the method as claimed in claim 16, 
further comprising forming an adhesive layer (118 in [0030], Fig. 4) between (as showed in Figs. 6c-6g) the die (102) and the redistribution layer structure (108C).
Lin does not disclose that the adhesive layer (118) is a conductive paste.
However, in the same semiconductor device field of endeavor, Fillion discloses a conductive joining layer (125 made of silver paste in [0075], Fig. 21) between the die (12 in [0075]) and the electrical interconnect structure (138 in [0075]).
It would have been obvious to one of ordinary skill in the art, at the time the invention was filed to make the Lin’s paste layer a conductive paste layer according to Fillion’s method to make flexible thermal connection.
Regarding claim 19, Lin modified by Fillion discloses the method as claimed in claim 18, wherein the conductive paste (118’s Lin after applied Fillion) is in direct contact (118 in direct contact with 108B and 102 as showed in Fig. 4, Lin) with the die (102) and the redistribution layer structure (108A, B, C, Fig. 4).
	
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 7:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898                                                                                                                                                                                                        
/AJAY OJHA/Supervisory Patent Examiner, Art Unit 2898