Patent Application 17519163 - SYNAPSE ARRAY OF A NEUROMORPHIC DEVICE INCLUDING - Rejection
Patent Application 17519163 - SYNAPSE ARRAY OF A NEUROMORPHIC DEVICE INCLUDING
Title: SYNAPSE ARRAY OF A NEUROMORPHIC DEVICE INCLUDING A SYNAPSE ARRAY HAVING A PLURALITY OF FERROELECTRICITY FIELD EFFECT TRANSISTORS
Application Information
- Invention Title: SYNAPSE ARRAY OF A NEUROMORPHIC DEVICE INCLUDING A SYNAPSE ARRAY HAVING A PLURALITY OF FERROELECTRICITY FIELD EFFECT TRANSISTORS
- Application Number: 17519163
- Submission Date: 2025-05-19T00:00:00.000Z
- Effective Filing Date: 2021-11-04T00:00:00.000Z
- Filing Date: 2021-11-04T00:00:00.000Z
- National Class: 706
- National Sub-Class: 029000
- Examiner Employee Number: 89261
- Art Unit: 2144
- Tech Center: 2100
Rejection Summary
- 102 Rejections: 0
- 103 Rejections: 1
Cited Patents
The following patents were cited in the rejection:
Office Action Text
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 11/4/2021 for application number 17/519,163.
Claims 1-10 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2018/0012123 A1) in view of Li et al. (US 5,444,821 A).
In reference to claim 1, Han teaches a synapse array of a neuromorphic device comprising: a first input neuron; a second input neuron (plurality of input neurons, like pre-neurons i 12 and j 14 in fig. 2, para. 0037-39; pre-neurons 1-9 in fig. 6, para. 0051); an output neuron (post-neurons 32 and 34, fig. 1, para. 0037-39 and post-neurons 502 in fig. 6, para. 0051); and a synapse (synapse network, para. 0051, fig. 6), wherein the synapse comprises a plurality of … ferroelectric field effect transistors electrically connected to each other in parallel (synapse comprises a plurality of FeFETs connected in parallel, see figs. 1 and 6, para. 0051, 0058-59), wherein each of the plurality of … ferroelectric field effect transistors comprises a first ferroelectric field effect transistor and a second ferroelectric field effect transistor (plurality of FeFETs, fig. 6, para. 0061).
However, Han does not explicitly teach a plurality of pairs of ferroelectric field effect transistors; wherein each of the plurality of pairs of ferroelectric field effect transistors comprises a first ferroelectric field effect transistor and a second ferroelectric field effect transistor, and wherein the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are electrically connected to each other in series.
Li teaches a plurality of pairs of ferroelectric field effect transistors; wherein each of the plurality of pairs of ferroelectric field effect transistors comprises a first ferroelectric field effect transistor and a second ferroelectric field effect transistor, and wherein the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are electrically connected to each other in series (pairs of transistors 102 and 106 are connected in series, see fig. 1, col. 2, line 55 to col. 3, line 66).
It would have been obvious to one of ordinary skill in art, having the teachings of Han and Li before the earliest effective filing date, to modify the single FeFET as disclosed by Han to include the pairs of FETs as taught by Li.
One of ordinary skill in the art would have been motivated to modify the single FeFET to include the pairs of FETs of Li because the pairs allow for both excitatory and inhibitory weights in the synapse (Li, col. 2, line 5 – col 4, line 39).
In reference to claim 2, Han and Li teach the synapse array of the neuromorphic device of claim 1, wherein the first ferroelectric field effect transistor includes a drain electrode electrically connected to the first input neuron (Han teaches a FeFET, para. 0058, and Li teaches excitatory transistor 102 has its drain electrode connected to a power source voltage, which is the input neuron, col. 2, lines 55-57; i.e. see this spec. para. 0060 as filed).
In reference to claim 3, Han and Li teach the synapse array of the neuromorphic device of claim 2, wherein the first ferroelectric field effect transistor includes a source electrode electrically connected to the output neuron (Han teaches a FeFET, para. 0058, and Li teaches excitatory transistor 102 has its source electrode connected to the output 30, col. 2, lines 55-57).
In reference to claim 4, Han teaches the synapse array of the neuromorphic device of claim 3, wherein the first ferroelectric field effect transistor includes a body electrically connected to the source electrode of the first ferroelectric field effect transistor (FeFETs have a body that is electrically connected to the other terminals, para. 0058, 0042, 0063).
In reference to claim 5, Han and Li teach the synapse array of the neuromorphic device of claim 1, wherein the second ferroelectric field effect transistor includes a source electrode electrically connected to the second input neuron (Han teaches a FeFET, para. 0058, and Li teaches the inhibitory transistor 106 has its source electrode connected to a ground reference voltage, col. 2, line 67 – col. 3, line 4, i.e. see this spec. para. 0060 as filed).
In reference to claim 6, Han and Li teach the synapse array of the neuromorphic device of claim 5, wherein the second ferroelectric field effect transistor includes a drain electrode electrically connected to the output neuron (Han teaches a FeFET, para. 0058, and Li teaches the inhibitory transistor 106 has its drain electrode connected to the output, col. 2, line 67 – col. 3, line 4).
In reference to claim 7, Han teaches the synapse array of the neuromorphic device of claim 6, wherein the second ferroelectric field effect transistor includes a body electrically connected to the drain electrode of the second ferroelectric field effect transistor (FeFETs have a body that is electrically connected to the other terminals, para. 0058, 0042, 0063).
In reference to claim 8, Han teaches the synapse array of the neuromorphic device of claim 1, wherein the first ferroelectric field effect transistor includes a first gate electrode and the second field effect transistor includes a second gate electrode, and wherein the first gate electrode and the second gate electrode are electrically connected to a common gating controller (gates of first and second FeFETs are connected to common feedback line 120, para. 0038 and fig. 2).
In reference to claim 9, Han teaches the synapse array of the neuromorphic device of claim 1, wherein the first ferroelectric field effect transistor comprises an n-type ferroelectric field effect transistor, and wherein the second ferroelectric field effect transistor comprises a p-type ferroelectric field effect transistor (first and second FeFETs can be n-type and p-type, para. 0045).
In reference to claim 10, Li teaches the synapse array of the neuromorphic device of claim 1, wherein the first input neuron provides a first reference voltage to the synapse, and the second input neuron provides a second reference voltage to the synapse, and wherein the first reference voltage is greater than the second reference voltage (first neuron provides reference power supply voltage, and second neuron provides ground voltage, so first neuron voltage is greater than second ground voltage, col. 2, lines 55 – col. 3, line 4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited generally teach background information on neuromorphic devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew T. Chiusano whose telephone number is (571)272-5231. The examiner can normally be reached M-F, 10am-6pm.
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/ANDREW T CHIUSANO/Primary Examiner, Art Unit 2144
