Patent Application 16143212 - NOVEL WAFER LEVEL CHIP SCALE PACKAGE WLCSP

Title: NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE PACKAGE (FCCSP), AND FAN OUT SHIELDING CONCEPTS

Application Information

Invention Title: NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE PACKAGE (FCCSP), AND FAN OUT SHIELDING CONCEPTS
Application Number: 16143212
Submission Date: 2025-04-10T00:00:00.000Z
Effective Filing Date: 2018-09-26T00:00:00.000Z
Filing Date: 2018-09-26T00:00:00.000Z
National Class: 257
National Sub-Class: 659000
Examiner Employee Number: 87574
Art Unit: 2899
Tech Center: 2800

Rejection Summary

102 Rejections: 0
103 Rejections: 3

Cited Patents

The following patents were cited in the rejection:

Office Action Text

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Claim Interpretation
Regarding Claim 1, the term “a dielectric” is interpreted in include non-dielectric materials in addition to a dielectric material, as the originally filed specification defines “dielectric” as “the dielectric 102 may be silicon bulk….the dielectric 102 may be the bottommost layer of the WLCSP 100 and may include, but is not limited to, a metallic material, an adhesive layer/film/tape, or any other core material” (Paragraph 34).

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

Claim 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (2016/0307835) in view of Feng et al. (U.S. 2009/0194880).
Regarding Claim 1, Chang (Fig 1B-J) discloses a wafer level chip scale package (WLCSP), comprising:
a first doped region on a second doped region, wherein the first doped region has a plurality of sidewalls, a top surface, and a bottom surface that is opposite to the top surface, the plurality of sidewalls extending from the top surface to the bottom surface (first doped region 116, second doped region 118, Paragraph 40);
a dielectric on a redistribution layer, wherein the dielectric is between the redistribution layer and the first and second doped region (dielectric 128/130, RDL 152 and/or 140);
a shield over the first and second doped region, the dielectric, and the redistribution layer, wherein the shield is directly on the top surface of the first doped region and along and directly on one or more of the plurality of sidewalls of the first doped region, on one or more sidewalls of the dielectric, and on one or more sidewalls of the redistribution layer from the top surface of the first doped region to a bottom surface of the redistribution layer (shield 154/190/170);
a plurality of interconnects coupled to the second doped region and the redistribution layer, wherein the plurality of interconnects is in direct contact with the second doped region, and the second doped region is in direct contact with the first doped region (interconnects 122/124/126) ; and
a plurality of solder balls coupled to a side of the redistribution layer opposite the plurality of interconnects, the plurality of solder balls having a bottommost surface below a bottommost surface of the shield (solder balls 160).
However, they do not explicitly disclose that the shield is a single continuous material in cross-section. Feng et al. discloses a similar device where a drain electrode/shield is formed over the backside of a chip as a single, continuous material in cross-section (Feng et al., shield 216/218, Figure 2m). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form the shield as a single, continuous material in Chang in view of Feng in order to facilitate simple, efficient and cost effective wafer level chip scale packaging of semiconductor devices (Feng et al., Paragraph 30).
Regarding Claim 1, Chang in view of Feng et al. further discloses wherein the shield is a five-sided shield (Feng et al., shield 216/218, Figure 1a).
Claim 3 is are rejected under 35 U.S.C. 103 as being unpatentable over Chang (2016/0307835) in view of Feng et al. (U.S. 2009/0194880), as applied to claim 1, further in view of Ishio et al. (U.S. 6,838,748).
Regarding Claim 3, Chang in view of Feng et al. disclose the device of claim 1 and further disclose wherein the shield is a conductive shield and wherein the shield is directly coupled to the redistribution layer and the first doped region (Chang, shield 190/154/170, first doped region 116, redistribution layer 152/140, Figure 1J, Paragraphs 44 and 47). However, they do not explicitly disclose wherein the conductive shield is conductively coupled to ground. Ishio et al. discloses a similar device wherein a shield on a backside of semiconductor chip is conductively coupled to ground (Ishio et al., chip 60, shield 4, dielectric 3, RDL 51, interconnect 2, bump 71, Figure 17). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to conductively couple the shield to ground Chang in view of Feng et al., further in view of Ishio et al. in order to increase the effect of blocking EM waves and prevent malfunction (Ishio et al., Column 17, Lines 29-40 and 50-53).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (2016/0307835) in view of Feng et al. (U.S. 2009/0194880), as applied to claim 1, further in view of Grebs et al. (U.S. 2010/0155839)
Regarding Claim 5, Chang in view of Feng et al. discloses the WLCSP of claim 1, wherein the first doped region includes a highly doped n-type material (Chang, Paragraph 40) However, they do not explicitly disclose that the second doped region includes at least one highly doped n-type material. Grebs et al. discloses a similar device wherein a second doped region directly contacts a first doped region, wherein the first and second doped region include a plurality of highly doped n-type materials (Grebs et al., first doped region 24, second doped region 26/38, Figure 1a). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form the second doped region to include at least one highly-doped n-type material in Chang in view of Feng et al., further in view of Grebs et al. in order to maintain the dopant concentration and control the breakdown voltage of the device (Paragraphs 35 and 37).

Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.

Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.

Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899