Patent Application 15980189 - MULTILAYER CAPACITOR AND CIRCUIT BOARD - Rejection
Appearance
Patent Application 15980189 - MULTILAYER CAPACITOR AND CIRCUIT BOARD
Title: MULTILAYER CAPACITOR AND CIRCUIT BOARD CONTAINING THE SAME
Application Information
- Invention Title: MULTILAYER CAPACITOR AND CIRCUIT BOARD CONTAINING THE SAME
- Application Number: 15980189
- Submission Date: 2025-04-08T00:00:00.000Z
- Effective Filing Date: 2018-05-15T00:00:00.000Z
- Filing Date: 2018-05-15T00:00:00.000Z
- National Class: 361
- National Sub-Class: 301400
- Examiner Employee Number: 76204
- Art Unit: 2848
- Tech Center: 2800
Rejection Summary
- 102 Rejections: 0
- 103 Rejections: 5
Cited Patents
The following patents were cited in the rejection:
Office Action Text
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/7/2024 has been entered. Response to Arguments Applicantâs arguments with respect to claim(s) 1-6, 11-17, and 22-29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-6, 12-15, 22-23, 25-26, and 29, is/are rejected under 35 U.S.C. 103 as being unpatentable over Arnold et al. (US 4,831,494) in view of Roy (US 2007/0019364) and Li (US 2004/0124511). PNG media_image1.png 270 402 media_image1.png Greyscale PNG media_image2.png 320 588 media_image2.png Greyscale Regarding claim 1, Arnold et al. disclose in fig. 4-5, a multilayer capacitor (title) comprising: a main body containing a first set of alternating dielectric layers (16) and internal electrode layers (114 - C:7, L: 50-60) and a second set of alternating dielectric layers (16) and internal electrode layers (opposite 114 - C: 7, L: 50-60), wherein the first set (fig. 5) is separated (50) from the second set (fig. 5) by a distance greater than the thickness of at least one dielectric layer (C: 8, L: 38-43) in a set (upper or lower set) and wherein the first set is separated from the second set by dielectric layers (C: 8, L: 44-47), each set of alternating dielectric layers (16) and internal electrode layers (114 â opposite 114) containing a first internal electrode layer (114) and a second internal electrode layer (opposite 114), each internal electrode layer including a top edge (top), a bottom edge (bottom) opposite the top edge (top), and two side edges (left, right) extending between the top edge and the bottom edge that define a main body of the internal electrode layer (114 â opposite 114), each internal electrode layer containing at least one lead tab (20) extending from the top edge of the main body of the internal electrode layer and at least one lead tab (43) extending from the bottom edge of the main body of the internal electrode layer, external terminals (fig. 5 â 34) electrically connected to the internal electrode layers, wherein the external terminals (34) are formed only on a top surface (top) of the capacitor and a bottom surface (bottom) of the capacitor opposing the top surface (top) of the capacitor, the external terminals (34) comprising a first set of external terminals (fig. 5) and a second set of external terminals (fig. 5) wherein the first set of alternating dielectric layers (16) and internal electrode layers is electrically connected to the first set of external terminals (34) and wherein the second set of alternating dielectric layers (16) and internal electrode layers is electrically connected to the second set of external terminals (34), wherein the external electrodes are thin films (C: 7, L: 33-50): and wherein the capacitor has an inductance of less than 1 nanohenry (C: 6, L: 60-65). Arnold et al. disclose the claimed invention except for each of the at least one lead tab extending from the top edge of the main body and each of the at least one lead tab extending from the bottom edge of the main body is offset from the two side edges of the main body of the internal electrode layer, wherein at least one lateral edge of the at least one lead tab on the top edge is substantially aligned with at least one lateral edge of the at least one lead tab on the bottom edge. PNG media_image3.png 424 604 media_image3.png Greyscale Roy discloses a multilayer capacitor having improved internal electrodes (42A, 42B), wherein each internal electrode layer (42A, 42B) contains at least one lead tab (46A, 46B) that extends from the top edge of the main body of the internal electrode layer (top) and at least one lead tab (45A, 45B) that extends from the bottom edge (bottom) of the main body of the internal electrode layer, wherein each of the at least one lead tab (46A, 46B) extends from the top edge of the main body and each of the at least one lead tab (45A, 45B) extends from the bottom edge of the main body is offset from the two side edges (left-right) of the main body of the internal electrode layer (42A, 42B), wherein at least one lateral edge of the at least one lead tab on the top edge is substantially aligned with at least one lateral edge of the at least one lead tab on the bottom edge. It would have been obvious to a person of ordinary skill in the internal electrode art to modify the multilayer capacitor of Arnold et al. (fig. 4) by replacing the internal electrodes with the electrodes of Roy, where each of the at least one lead tab extending from the top edge of the main body and each of the at least one lead tab extending from the bottom edge of the main body is offset from the two side edges of the main body of the internal electrode layer, wherein at least one lateral edge of the at least one lead tab on the top edge is substantially aligned with at least one lateral edge of the at least one lead tab on the bottom edge, since such a modification would further reduce the inductance of the capacitor. Arnold discloses the claimed invention except for the multilayer capacitor is formed in a component, wherein the component comprises a printed circuit board and an integrated circuit package, wherein the external electrodes are directly connected to the circuit board or the integrated circuit package. PNG media_image4.png 216 588 media_image4.png Greyscale Li discloses a capacitor (62, 64) that is directly connected to a circuit board (34) and an integrated circuit package (22). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the capacitor of Arnold et al. so that it directly connects between a circuit board and an integrated circuit package, since such a modification would form a device comprising a low inductance capacitor where electrical shorting is prevented. Regarding claims 2, 3, and 22, the modified Arnold et al. disclose the inductance is less than 1 picohenry. Claims 2, 3, and 22 recite a feature that has to be certified with specialized testing equipment, not at the disposal of the Office. However, as noted in the rejection of claim 1 above, the modified Arnold et al. reference discloses the claimed internal electrode structure. When the structure recited in the references is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. MPEP 2112.01 I states: âWhere the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). "When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (Claims were directed to a titanium alloy containing 0.2-0.4% Mo and 0.6-0.9% Ni having corrosion resistance. A Russian article disclosed a titanium alloy containing 0.25% Mo and 0.75% Ni but was silent as to corrosion resistance. The Federal Circuit held that the claim was anticipated because the percentages of Mo and Ni were squarely within the claimed ranges. The court went on to say that it was immaterial what properties the alloys had or who discovered the properties because the composition is the same and thus must necessarily exhibit the properties.). See also In re Ludtke, 441 F.2d 660, 169 USPQ 563 (CCPA 1971) (Claim 1 was directed to a parachute canopy having concentric circumferential panels radially separated from each other by radially extending tie lines. The panels were separated "such that the critical velocity of each successively larger panel will be less than the critical velocity of the previous panel, whereby said parachute will sequentially open and thus gradually decelerate." The court found that the claim was anticipated by Menget. Menget taught a parachute having three circumferential panels separated by tie lines. The court upheld the rejection finding that applicant had failed to show that Menget did not possess the functional characteristics of the claims.); Northam Warren Corp. v. D. F. Newfield Co., 7 F. Supp. 773, 22 USPQ 313 (E.D.N.Y. 1934) (A patent to a pencil for cleaning fingernails was held invalid because a pencil of the same structure for writing was found in the prior art.). Regarding claim 4, Arnold et al. disclose the first internal electrode layer (114, 122) and the second internal electrode layer (opposite 114, opposite 122) are interleaved in an opposed relation and dielectric layer (16) is positioned between the first internal electrode layer and the second internal electrode layer, Regarding claim 5, the modified Arnold et al. disclose each internal electrode layer includes at least two lead tabs (Roy - fig. 5-6) extending from the top edge (top), the bottom edge (bottom), or both the top edge and the bottom edge. Regarding claim 6, the modified Arnold et al. (Roy) disclose both lateral edges of the lead tab (46A, 46B) on the top edge is substantially aligned with at least one lateral edge of the lead tab on the bottom edge (45A, 45B). Regarding claims 12-13, Arnold et al. disclose the external terminals include a thin metal layer (a metallized layer â C: 7, L: 32-28). The language, term, or phrase âthe external terminals include an electroplated layer/electroless plated layerâ, is directed to towards the process of forming the external electrodes. The method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. In re STEPHENS, WENZL, AND BROWNE, 145 USPQ 656 (CCPA 1965) Regarding claims 14-15, Arnold et al. disclose the external electrode comprises three thin metal layers (C: 7, L:65-50). The language, term, or phrase âthe external terminals include an electroplated layer/electroless plated layer, is directed to towards the process of forming the external electrodes. The method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. In re STEPHENS, WENZL, AND BROWNE, 145 USPQ 656 (CCPA 1965) Regarding claim 23, Arnold et al. disclose the external terminals (84, 46) are formed only on the top surface of the capacitor and the bottom surface of the capacitor opposing the top surface of the capacitor. Regarding claim 25, Arnold et al. disclose the external terminals are provided in at least two rows and at least two columns (see fig. 5). Regarding claim 26, Arnold et al. disclose each adjacent external terminal (34) is of an opposite polarity (see fig. 4). Regarding claim 29, Arnold et al. disclose the external electrodes are thin films (C: 7, L: 33-50). Applicant is reminded that the limitation, âthe external terminals consist essentially of one or more electroplate terminals , one or more electroless plated terminals or a combination thereofâ is directed towards the process of forming the external electrodes. The method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. In re STEPHENS, WENZL, AND BROWNE, 145 USPQ 656 (CCPA 1965) Claim(s) 11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arnold et al. (US 4,831,494), Roy (US 2007/0019364), and Li (US 2004/0124511), as applied to claim 1 above, and further in view of applicantâs admitted prior art (AAPA). Regarding claim 11, Arnold et al. disclose the claimed invention except for the top edge and the bottom edge include a different number of lead tabs. AAPA discloses that it is known in the art to form a multilayer ceramic capacitor where the top edge and the bottom edge include a different number of tabs (external electrodes). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the multilayer ceramic capacitor of Arnold et al. so that the top edge and the bottom edge include a different number of lead tabs, since such a modification would form a capacitor element having desired electrical properties (ESL). It would have been obvious to a person of ordinary skill in the art to form the top edge (or bottom edge) having more electrical connections than the bottom edge (or top edge). Regarding claim 17, Arnold et al. disclose the sets are separated by a dielectric having a thickness of greater than the thickness of the dielectric contained in each set. Arnold et al. disclose the claimed invention except for the capacitor includes a third set of dielectric and electrode layers, wherein the third set is separated from the second set by a distance greater than the thickness of dielectric contained in the set. AAPA discloses forming more a laminate multilayer ceramic capacitor having more than two sets of alternating dielectric layers and internal electrode layers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor of Arnold et al. so that it includes a third set of dielectric and internal electrode layers that is separated from the second set by a distance greater than the thickness of at least one dielectric in the set, since such a modification would form a multilayer capacitor having an additional capacitor element that is contained within the laminate. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arnold et al. (US 4,831,494), Roy (US 2007/0019364), and Li (US 2004/0124511), as applied to claim 15 above, and further in view of Ritter et al. (US 2004/0257748). Regarding claim 16, Arnold et al. disclose the claimed invention except for the first electroless plated layer includes copper, the second electroplated layer includes nickel, and the third electroplated layer includes tin. Ritter et al. disclose a multilayer ceramic capacitor having a terminal that comprises a first copper plating layer, a second nickel-plating layer and a third tin plating layer [0136]. It would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to form the external terminals of the Arnold et al. to include a first copper plating layer, a second nickel-plating layer and a third tin plating layer, since such a modification would form extremely thin film external electrodes having high conductivity. 10. Claim(s) 24 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arnold et al. (US 4,831,494), Roy (US 2007/0019364), and Li (US 2004/0124511), as applied to claim 1 above, and further in view of Lee et al. (US 2015/0016016). Regarding claims 24 and 27, Arnold et al. disclose the claimed invention except for the first set is separated from the second set by a distance at least five times greater than the thickness of at least one dielectric layer in a set. Lee discloses a first capacitor set (127) that is separated from a second capacitor set (125) by a distance greater than five times greater (115) than the thickness of at least one dielectric layer in a set. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the multilayer ceramic capacitor so that the first set is separated from the second set by a distance of greater than five times that of the thickness of at least one dielectric layer in a set, since such a modification would form a multilayer ceramic capacitor where the external electrodes are completely isolated from one another and the ceramic capacitor can be used on a printed circuit board. 11. Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arnold et al. (US 4,831,494), Roy (US 2007/0019364), and Li (US 2004/0124511), as applied to claim 1 above, and further in view of Ritter et al. (US 2007/0014075). Regarding claim 28, Arnold et al. disclose the claimed invention except for the pitch between the external terminals is 0.1 mm to 2.0 mm. Ritter et al. disclose a pitch between external electrodes being between 0.1 mm to 2.0 mm [0106]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the pitch between the external electrodes of Arnold et al. to be between 0.1 mm to 2.0 mm, since such a modification would form a multilayer ceramic capacitor having a desired level of ESL. Conclusion 13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC THOMAS whose telephone number is (571)272-1985. The examiner can normally be reached Monday-Friday, 6:00 AM-2:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examinerâs supervisor, Timothy Dole can be reached on 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC W THOMAS/Primary Examiner, Art Unit 2848 ERIC THOMAS Primary Examiner Art Unit 2848