NVIDIA Corporation patent applications on November 14th, 2024
Patent Applications by NVIDIA Corporation on November 14th, 2024
NVIDIA Corporation: 14 patent applications
NVIDIA Corporation has applied for patents in the areas of G06F11/34 (3), G06F9/50 (2), H05K7/20 (2), G06F9/30 (2), H04N19/91 (1) G01R1/20 (1), G06F8/441 (1), G06F8/65 (1), G06F9/3004 (1), G06F9/5044 (1)
With keywords such as: texture, data, rack, computing, query, systems, cooling, textures, registers, and bev in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Frans Johannes Fourie of Portland OR (US) for nvidia corporation, Ryan Kelsey Albright of Beaverton OR (US) for nvidia corporation, Akhilesh Sandeep Thakur of Portland OR (US) for nvidia corporation, Kevin Matthew Hoser of Portland OR (US) for nvidia corporation, Grant Michael Skidmore of Portland OR (US) for nvidia corporation, Zachary Jacob Watkins of Hillsboro OR (US) for nvidia corporation, Audrey Grace Cummings of Hillsboro OR (US) for nvidia corporation, Jose Eduardo Barcenas of Portland OR (US) for nvidia corporation, Jorian Matias Bruslind of Beaverton OR (US) for nvidia corporation, Daniel Garanton of Hillsboro OR (US) for nvidia corporation
IPC Code(s): G01R1/20, G01R31/52
CPC Code(s): G01R1/20
Abstract: approaches presented herein provide for a short circuit testing fixture in which a switch arm is associated with a switch bridge and with a trigger mechanism to enable testing of electrical shorts in high powered dc circuits. the trigger mechanism causes the switch arm to contact the switch bridge and close an energized circuit to cause a short. the switch arm maintains the closed energized circuit after the short until the circuit is deenergized.
20240378035. COMPILATION TECHNIQUE USING METRICS_simplified_abstract_(nvidia corporation)
Inventor(s): David Allan Berson of Portland OR (US) for nvidia corporation
IPC Code(s): G06F8/41
CPC Code(s): G06F8/441
Abstract: apparatuses, systems, and techniques to allocate and/or assign registers. in at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.
20240378041. SOFTWARE MODIFICATION TECHNIQUE USING METRICS_simplified_abstract_(nvidia corporation)
Inventor(s): David Allan Berson of Portland OR (US) for nvidia corporation
IPC Code(s): G06F8/65, G06F8/71, G06F11/34
CPC Code(s): G06F8/65
Abstract: apparatuses, systems, and techniques to allocate and/or assign registers. in at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.
20240378054. MEMORY MODIFICATION TECHNIQUE USING METRICS_simplified_abstract_(nvidia corporation)
Inventor(s): David Allan Berson of Portland OR (US) for nvidia corporation
IPC Code(s): G06F9/30, G06F9/48, G06F11/34
CPC Code(s): G06F9/3004
Abstract: apparatuses, systems, and techniques to allocate and/or assign registers. in at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.
20240378089. REGISTER CONFIGURATION TECHNIQUE USING METRICS_simplified_abstract_(nvidia corporation)
Inventor(s): David Allan Berson of Portland OR (US) for nvidia corporation
IPC Code(s): G06F9/50, G06F9/30
CPC Code(s): G06F9/5044
Abstract: apparatuses, systems, and techniques to allocate and/or assign registers. in at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.
Inventor(s): Shekhar Dwivedi of Santa Clara CA (US) for nvidia corporation, Rahul Choudhury of Livermore CA (US) for nvidia corporation
IPC Code(s): G06F9/50, G06F11/30, G06F11/34, G06F16/901
CPC Code(s): G06F9/5083
Abstract: apparatuses, systems, and techniques to collect performance data for one or more computations tasks executed by a plurality of nodes of a computational pipeline and enable optimization of distribution of task execution among the plurality of nodes.
Inventor(s): Ruthie D. Lyle of Durham NC (US) for nvidia corporation
IPC Code(s): G06F21/62, G06N20/00
CPC Code(s): G06F21/6218
Abstract: a first query having a first privacy status is received. a response to the first query is obtained based on output(s) of one or more machine learning (ml) models of an open domain dialog system. each ml model is trained to predict responses to queries having the first privacy status. data associated with the first query and the response is provided as training data for the ml models, in view of the first privacy status. a second query having a second privacy status is received. a closed domain dialog system associated with a context of the second query and having a privacy status corresponding to the second privacy status is identified. the second query is forwarded to the closed domain dialog system for obtaining a response to the second query. data associated with the second query is not provided to train the ml models of the open domain dialog system.
20240378759. DECOMPRESSION OF COMPRESSED TEXTURE SETS_simplified_abstract_(nvidia corporation)
Inventor(s): Karthik Vaidyanathan of Oakland CA (US) for nvidia corporation, Marco Salvi of Seattle WA (US) for nvidia corporation, Bartlomiej Wronski of Brooklyn NY (US) for nvidia corporation, Tomas Akenine-Moller of Lund (SE) for nvidia corporation, Johan Pontus Ebelin of LUND (SE) for nvidia corporation, Aaron Eliot Lefohn of Kirkland WA (US) for nvidia corporation, John Matthew Burgess of Austin TX (US) for nvidia corporation, Steven James Heinrich of Madison AL (US) for nvidia corporation, Michael Alan Fetterman of Lancaster MA (US) for nvidia corporation, Shirish Gadre of Fremont CA (US) for nvidia corporation, Mark Alan Gebhart of Round Rock TX (US) for nvidia corporation, Yury Uralsky of Los Gatos CA (US) for nvidia corporation
IPC Code(s): G06T9/00, G06T15/00
CPC Code(s): G06T9/00
Abstract: in computer graphics, texture refers to a type of surface, including the material characteristics, that can be applied to an object in an image. a texture may be defined using numerous parameters, such as color(s), roughness, glossiness, etc. in some implementations, a texture may be represented as an image that can be placed on a three-dimensional (3d) model of an object to give surface details to the 3d object. to reduce a size of textures (e.g. for storage and transmission), textures in a texture set may be compressed together. the present disclosure provides for decompression of at least a portion of a single texture representation of a set of textures into at least a portion of a plurality of textures included in the set of textures.
Inventor(s): Ryan Albright of Beaverton OR (US) for nvidia corporation, Jordan Levy of Portland OR (US) for nvidia corporation, William Mecham of Elk Grove CA (US) for nvidia corporation, William Ryan Weese of Portland OR (US) for nvidia corporation, Benjamin Goska of Portalnd OR (US) for nvidia corporation, Aaron Carkin of Hillsboro OR (US) for nvidia corporation, Michael Thompson of Wilsonville OR (US) for nvidia corporation
IPC Code(s): G06T11/00, H04L41/22
CPC Code(s): G06T11/00
Abstract: systems, methods, and computer program products are provided for asset identification and visualization. an example method includes receiving a request for asset visualization that is associated with a plurality of distributed datacenter computing components associated with disparate physical datacenter installations and determining location data for the distributed datacenter computing components. the method further includes generating the asset visualization for presentation to a user associated with the request. the asset visualization is a digital representation of the disparate physical datacenter installations including a visual representation of a presence of the distributed datacenter computing components associated with each disparate physical datacenter installation. the method may render the asset visualization in a virtual reality (vr) environment and/or as an augmented reality (ar) overlay via a user device associated with the user.
Inventor(s): Karthik Vaidyanathan of Oakland CA (US) for nvidia corporation, Marco Salvi of Seattle WA (US) for nvidia corporation, Bartlomiej Wronski of Brooklyn NY (US) for nvidia corporation, Tomas Akenine-Moller of Lund (SE) for nvidia corporation, Johan Pontus Ebelin of LUND (SE) for nvidia corporation, Aaron Eliot Lefohn of Kirkland WA (US) for nvidia corporation, John Matthew Burgess of Austin TX (US) for nvidia corporation, Steven James Heinrich of Madison AL (US) for nvidia corporation, Michael Alan Fetterman of Lancaster MA (US) for nvidia corporation, Shirish Gadre of Fremont CA (US) for nvidia corporation, Mark Alan Gebhart of Round Rock TX (US) for nvidia corporation, Yury Uralsky of Los Gatos CA (US) for nvidia corporation
IPC Code(s): G06T15/04, G06V10/44, H04N19/40, H04N19/91
CPC Code(s): G06T15/04
Abstract: in computer graphics, texture refers to a type of surface, including the material characteristics, that can be applied to an object in an image. a texture may be defined using numerous parameters, such as color(s), roughness, glossiness, etc. in some implementations, a texture may be represented as an image that can be placed on a three-dimensional (3d) model of an object to give surface details to the 3d object. to reduce a size of textures (e.g. for storage and transmission), textures in a texture set may be compressed together. the present disclosure provides for transcoding a compressed texture set to textures with a hardware-supported compression format.
Inventor(s): Zhiqi Li of Shanghai (CN) for nvidia corporation, Zhiding Yu of Santa Clara CA (US) for nvidia corporation, Animashree Anandkumar of Pasadena CA (US) for nvidia corporation, Jose Manuel Alvarez Lopez of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06T15/20, G06T7/11, G06T7/50, G06V20/58
CPC Code(s): G06T15/205
Abstract: in various examples, bi-directional projection techniques may be used to generate enhanced bird's-eye view (bev) representations. for example, a system(s) may generate one or more bev features associated with a bev of an environment using a projection process that associates 2d image features to one or more first locations of a 3d space. at least partially using the bev feature(s), the system(s) may determine one or more second locations of the 3d space that correspond to one or more regions of interest in the environment. the system(s) may then generate one or more additional bev features corresponding to the second location(s) using a different projection process that associates the second location(s) from the 3d space to at least a portion of the 2d image features. the system(s) may then generate an updated bev of the environment based at least on the bev feature(s) and/or the additional bev feature(s).
Inventor(s): William Mecham of Elk Grove CA (US) for nvidia corporation, Ryan Albright of Beaverton OR (US) for nvidia corporation, William Ryan Weese of Portland OR (US) for nvidia corporation, Benjamin Goska of Portland OR (US) for nvidia corporation, Aaron Carkin of Hillsboro OR (US) for nvidia corporation, Michael Thompson of Wilsonville OR (US) for nvidia corporation, Tahir Cader of Spokane Valley WA (US) for nvidia corporation, Jordan Levy of Portland OR (US) for nvidia corporation
IPC Code(s): G10K11/16, H05K7/20
CPC Code(s): G10K11/161
Abstract: thermal management systems and associated methods are provided with acoustic isolation. an example system includes a computing device that defines a first housing supporting one or more processing units and a thermal management system. the thermal management system includes a pressure generation mechanism and one or more cooling conduits operably coupled with the pressure generation mechanism, and the one or more cooling conduits provide fluid communication between the computing device and the pressure generation mechanism. the pressure generation mechanism causes circulation of cooling fluid to the computing device via the one or more cooling conduits so as to dissipate heat generated by the one or more processing units, and the pressure generation mechanism is acoustically isolated from the computing device.
Inventor(s): Padam Jain of Santa Jose CA (US) for nvidia corporation, Shantanu Kalchuri of San Jose CA (US) for nvidia corporation
IPC Code(s): H01L27/08, H01F27/28, H01F41/02, H01L23/498
CPC Code(s): H01L28/10
Abstract: a process for manufacturing inductors for use in integrated circuits includes embedding ferromagnetic material in a bulk silicon substrate, forming a plurality of vias in the bulk silicon substrate such that the vias bracket a volume of the bulk silicon substrate that includes the ferromagnetic material, slicing the bulk silicon substrate to form a silicon wafer, and configuring traces between top metal pads of the vias and between bottom metal pads of the vias to form a continuous path for current to flow circumferentially from a first end of the volume to a second end of the volume.
20240381582. INTELLIGENT COMPONENTS OF A DATA CENTER_simplified_abstract_(nvidia corporation)
Inventor(s): Siddha Ganju of Santa Clara CA (US) for nvidia corporation, Fred Devoir of Pilot Point TX (US) for nvidia corporation, Elad Mentovich of Tel Aviv (IL) for nvidia corporation, Ryan Albright of Beaverton OR (US) for nvidia corporation, Tahir Cader of Spokane Valley WA (US) for nvidia corporation, Kenneth Misin of Campbell CA (US) for nvidia corporation, William Mecham of Elk Grove CA (US) for nvidia corporation, Benjamin Goska of Portland OR (US) for nvidia corporation, Jordan Levy of Portland OR (US) for nvidia corporation, Aaron Carkin of Hillsboro OR (US) for nvidia corporation, Michael Thompson of Wilsonville OR (US) for nvidia corporation, William Ryan Weese of Portland OR (US) for nvidia corporation, Ran Rakovsky of Ganei Tiqwa (IL) for nvidia corporation, Rotem Barzilay of Shimshit (IL) for nvidia corporation, Itamar Frenkel of Kiryat Bialik (IL) for nvidia corporation, Yaakov Gridish of Yoqneam (IL) for nvidia corporation
IPC Code(s): H05K7/20, H05K7/14
CPC Code(s): H05K7/20745
Abstract: some embodiments described herein provide intelligent movable racks for a data center and a central system for monitoring and directing the positioning of such racks within the data center. for example, a rack may include computing equipment as well as a power system, a cooling system, and a cabling system (e.g., for data communication). the rack may include a controller in communication with the computing equipment, the power system, the cooling system, and the cabling system. the rack may also include a rack interface for physically supporting the rack and operatively connecting the systems of the rack to power, cooling, and cabling infrastructure of the data center. the rack interface may receive an autonomous robot for moving the rack within the data center. the controller may control the power system and the cooling system based in part on the autonomous movement of the rack.
NVIDIA Corporation patent applications on November 14th, 2024
- NVIDIA Corporation
- G01R1/20
- G01R31/52
- CPC G01R1/20
- Nvidia corporation
- G06F8/41
- CPC G06F8/441
- G06F8/65
- G06F8/71
- G06F11/34
- CPC G06F8/65
- G06F9/30
- G06F9/48
- CPC G06F9/3004
- G06F9/50
- CPC G06F9/5044
- G06F11/30
- G06F16/901
- CPC G06F9/5083
- G06F21/62
- G06N20/00
- CPC G06F21/6218
- G06T9/00
- G06T15/00
- CPC G06T9/00
- G06T11/00
- H04L41/22
- CPC G06T11/00
- G06T15/04
- G06V10/44
- H04N19/40
- H04N19/91
- CPC G06T15/04
- G06T15/20
- G06T7/11
- G06T7/50
- G06V20/58
- CPC G06T15/205
- G10K11/16
- H05K7/20
- CPC G10K11/161
- H01L27/08
- H01F27/28
- H01F41/02
- H01L23/498
- CPC H01L28/10
- H05K7/14
- CPC H05K7/20745
