NVIDIA Corporation patent applications on May 8th, 2025
Patent Applications by NVIDIA Corporation on May 8th, 2025
NVIDIA Corporation: 14 patent applications
NVIDIA Corporation has applied for patents in the areas of G06N20/00 (3), H04J14/02 (2), G06T7/50 (2), F16F1/18 (1), G06T7/90 (1) F16F1/185 (1), G02C9/00 (1), G06F21/6218 (1), G06F21/85 (1), G06N3/084 (1)
With keywords such as: computation, data, distributed, signal, peripheral, based, optical, include, latency, and computing in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Shengli WANG of Shenzhen CN for nvidia corporation, Qiang CHEN of Shenzhen City CN for nvidia corporation, Yifei DOU of Shenzhen CN for nvidia corporation, John Harold DREW of San Jose CA US for nvidia corporation
IPC Code(s): F16F1/18, H05K7/20
CPC Code(s): F16F1/185
Abstract: a leaf spring for coupling a heat sink to an integrated circuit includes a central portion that has an aperture; a first spring arm that is formed on a first side of the central portion and includes a first through-hole for a first fastener; a second spring arm that is formed on a second side of the central portion and includes a second through-hole for a second fastener; a first bending axis that passes through the first side and is substantially perpendicular to a longitudinal axis of the leaf spring that passes through the first through-hole and the second through-hole; and a second bending axis that passes through the second side and is substantially perpendicular to the longitudinal axis of the leaf spring.
20250147344. MODULAR PRESCRIPTION AUGMENTED REALITY DISPLAY_simplified_abstract_(nvidia corporation)
Inventor(s): Jonghyun Kim of Palo Alto CA US for nvidia corporation, Benjamin Boudaoud of Efland NC US for nvidia corporation, Michael Stengel of Cupertino CA US for nvidia corporation, Josef Bo Spjut of Durham NC US for nvidia corporation, Morgan Samuel McGuire of Waterloo CA for nvidia corporation
IPC Code(s): G02C9/00, G02B27/01
CPC Code(s): G02C9/00
Abstract: in an embodiment, a modular augmented reality display is provided that incorporates prescription eyewear that can be used separately by the wearer. in an embodiment, an image is generated from a removable display attached to the eyewear and directed into the edge of a prescription lens, which acts as a waveguide. the image is internally reflected within the prescription lens, and is directed to the wearer by an image combiner embedded within the prescription lens. in an embodiment, the augmented reality display includes a wearable belt pouch that includes a battery and support electronics connected to the eyewear so that the weight on the eyewear is reduced.
20250148110. KEY DISTRIBUTION SYSTEM_simplified_abstract_(nvidia corporation)
Inventor(s): Ron Keidar of San Diego CA US for nvidia corporation, Akash Singh of Bengaluru IN for nvidia corporation, DurgaPrasad Potnuru of Bangalore IN for nvidia corporation
IPC Code(s): G06F21/62
CPC Code(s): G06F21/6218
Abstract: systems and methods are directed toward key distribution systems and methods. a key distribution system may include a policy table and a key table to develop different policy regions for various associated managers and then map memory address locations to table locations for the policy regions. the policy regions may be established using different parameters and then locked after activation to prevent further editing or modification after creation. when activated, users and owners may then access the associated memory addresses associated with authorized active policy regions.
Inventor(s): Igor Mitsyanko of San Carlos CA US for nvidia corporation, Aki Petteri Niemi of Vancouver CA for nvidia corporation, Junghyun Kim of Dublin CA US for nvidia corporation
IPC Code(s): G06F21/85, G06F21/60
CPC Code(s): G06F21/85
Abstract: a controller device includes a memory storing instructions, an interface bus coupled to peripheral devices and configured to operate with a multi-target interface protocol, and a processor coupled to the memory and the interface bus. the processor broadcasts initialization data, according to the multi-target interface protocol, to the peripheral devices. the processor generates, from the initialization data, using at least one cryptographic function, an authentication tag for each peripheral device. each authentication tag can be specific to a corresponding peripheral device. the processor creates client objects corresponding to each of the peripheral devices, each client object configured to unicast an authentication tag to the corresponding peripheral device based on a specific address. the processor unicasts, according to the multi-target interface protocol, using the client objects, each authentication tag to the corresponding peripheral device of the peripheral devices.
Inventor(s): Hao Wu of Santa Clara CA US for nvidia corporation
IPC Code(s): G06N3/084
CPC Code(s): G06N3/084
Abstract: machine learning systems that implement neural networks typically operate in an inference mode or a training mode. in the training mode, inference operations are performed to help guide the training process. inference mode operation typically involves forward propagation and intensive access to certain sparse matrices, encoded as a set of vectors. back propagation and intensive access to transposed versions of the same sparse matrices provide training refinements. generating a transposed version of a sparse matrix can consume significant additional memory and computation resources. in one embodiment, two additional encoding vectors are generated, providing efficient operations on sparse matrices and also on transposed representations of the same sparse matrices. in a neural network the efficient operations can reduce the amount of memory needed for backpropagation and reduce power consumption.
Inventor(s): Bing Xu of Kirkland WA US for nvidia corporation
IPC Code(s): G06N5/04, G06N20/00
CPC Code(s): G06N5/04
Abstract: a peer-to-peer signal node may include a communication interface in communication with a plurality of client machines via a network. the communication interface may receive a client request message identifying a designated computing model and input data on which to execute the designated computing model. the peer-to-peer signal node may also include a computation node registry maintaining access information for a plurality of distributed computation nodes accessible via the network. the peer-to-peer signal node may also include a work scheduler, which may select a distributed computation node and transmit a computation request message to the selected node identifying the designated computing model and the input data and establishing a communication session between the distributed computation node and the client machine through which the distributed computation node transmits a result obtained based on executing the computing model using the input data.
20250148349. DISTRIBUTED COMPUTING MODEL EXECUTION SYSTEM_simplified_abstract_(nvidia corporation)
Inventor(s): Bing Xu of Kirkland WA US for nvidia corporation
IPC Code(s): G06N20/00, G06F9/50
CPC Code(s): G06N20/00
Abstract: a distributed computation model execution gateway may include a communication interface receiving a client request message identifying a computing model and input data on which to execute the computing model. the distributed computation model execution gateway may also include a worker registry maintaining access information for distributed computation workers. the distributed computation model execution gateway may also include a work scheduler that selects from the worker registry a distributed computation worker based on the client request message and transmits to the distributed computation worker a worker request message identifying the designated computing model and the input data. the work scheduler may also receive from the distributed computation worker a worker response message that includes a result obtained based on executing the computing model using the input data. the distributed computation model execution gateway may also include a transaction database storing records reflecting execution of the designated computing model.
20250148627. DISTANCE MEASUREMENT OF PIXELS IN IMAGES_simplified_abstract_(nvidia corporation)
Inventor(s): John Christian Russ, III of Asheville NC US for nvidia corporation, Minhan Huai of Shanghai CN for nvidia corporation
IPC Code(s): G06T7/50, G06T7/13
CPC Code(s): G06T7/50
Abstract: apparatuses, systems, and methods are to cause a minimum distance between pixels in an image to be calculated. in at least one embodiment, a minimum distance between a first pixel within an object and one or more edge pixels of said object are calculated based, at least in part, on one or more edge pixels within one or more columns of pixels between two edge pixels of said object within a same row of pixels as said first pixel.
Inventor(s): Maksim Aizenshtein of Sammamish WA US for nvidia corporation
IPC Code(s): G06T15/06, G06T7/40, G06V10/54
CPC Code(s): G06T15/06
Abstract: approaches presented herein provide for removal or reduction of anti-aliasing artifacts, such as moirďż˝ patterns or staircasing, in an image to be rendered. in many instances, these artifacts correspond to regular texture patterns with fine detail, and the addition of randomization in sampling position can help to remove the impact of the regularity of the pattern. in at least one embodiment, a first order approximation can be used that introduces a random amount of shifting determined using texture coordinate derivatives. the random amount can account for any jitter offset, and shift the texture coordinates by the determined random amount, such that sample selected for that pixel will select from a sample location that corresponds to the random shift but is constrained to be within the bounds of the pixel.
20250148703. 3D OBJECT RECONSTRUCTION_simplified_abstract_(nvidia corporation)
Inventor(s): Angel Javier Gamazo Tejero of Berne CH for nvidia corporation, Mahdi Azizian of San Jose CA US for nvidia corporation, Sean DuCharme Huver of Ridgefield CT US for nvidia corporation
IPC Code(s): G06T15/50, G06T7/50, G06T7/90, G06V10/77, G06V10/82
CPC Code(s): G06T15/506
Abstract: apparatuses, systems, and techniques of using one or more neural networks to generate one or more three-dimensional (â3dâ) objects based, at least in part, on reflectivity information. in at least one embodiment, one or more images is processed using a neural network to generate one or more 3d objects that represent objects in said one or more images.
Inventor(s): Jason Conrad Roche of Santa Clara CA US for nvidia corporation, Niranjan Avadhanam of Saratoga CA US for nvidia corporation
IPC Code(s): G06V20/59, G06F3/01, G06N3/02, G06N20/00
CPC Code(s): G06V20/597
Abstract: in various examples, systems and methods are disclosed herein for a vehicle command operation system that may use technology across multiple modalities to cause vehicular operations to be performed in response to determining a focal point based on a gaze of an occupant. the system may utilize sensors to receive first data indicative of an eye gaze of an occupant of the vehicle. the system may utilize sensors to receive second data indicative of other data from the occupant. the system may then calculate a gaze vector based on the data indicative of the eye gaze of the occupant. the system may determine a focal point based on the gaze vector. in response to determining the focal point, the system causes an operation to be performed in the vehicle based on the second data.
Inventor(s): Liron Gantz of Haifa IL for nvidia corporation, Shai Cohen of Haifa IL for nvidia corporation, Dor Oz of Tel Aviv IL for nvidia corporation, Alon Gabbay of Yokneam IL for nvidia corporation, Idan Yokev of Ra'anana IL for nvidia corporation
IPC Code(s): H04B10/2581, G02B6/42, H04J14/02
CPC Code(s): H04B10/2581
Abstract: a system can include a unit cell of a ring modulator of a coarse wavelength division multiplexing (cwdm) optical link. the unit cell includes a ring resonator including a ring waveguide configured to receive, via a first bus waveguide, an optical signal, and modulate the optical signal to generate a modulated optical signal. the unit cell further includes a multiplexer, disposed between the first bus waveguide and a second bus waveguide, configured to filter the modulated optical signal.
Inventor(s): Liron Gantz of Haifa IL for nvidia corporation, Shai Cohen of Haifa IL for nvidia corporation, Alon Gabbay of Yokneam IL for nvidia corporation
IPC Code(s): H04J14/02
CPC Code(s): H04J14/0283
Abstract: a system can include a unit cell of a ring modulator of a dense wavelength division multiplexing (dwdm) optical link. the unit cell includes a set of ring waveguides, each ring waveguide of the set of ring waveguides being configured to generate a portion of a modulated optical signal based on a portion of an optical signal received via a first bus waveguide. the unit cell further includes a multiplexer, operatively coupled to a second bus waveguide, configured to filter the portion of the modulated optical signal to generate a portion of a filtered optical signal.
Inventor(s): David Lim of Cupertino CA US for nvidia corporation, Hsien-Li Lin of Taipei City TW for nvidia corporation, Tom Jozef Denis Verbeure of Sunnyvale CA US for nvidia corporation, Gerrit Slavenburg of Hayward CA US for nvidia corporation, Seth Schneider of San Jose CA US for nvidia corporation
IPC Code(s): H04L43/0852, G06F3/14, H04L43/065, H04L43/106
CPC Code(s): H04L43/0858
Abstract: in various examples, latency of human interface devices (hids) may be accounted for in determining an end-to-end latency of a system. for example, when an input is received at an hid, an amount of time for the input to reach a connected device may be computed by the hid and included in a data packet transmitted by the hid device to the connected device. the addition of the peripheral latency to the end-to-end latency determination may provide a more comprehensive latency result for the system and, where the peripheral latency of an hid is determined to have a non-negligible contribution to the end-to-end latency, a new hid component may be implemented, a configuration setting associated with the hid component may be updated, and/or other actions may be taken to reduce the contribution of the peripheral latency to the overall latency of the system.
- NVIDIA Corporation
- F16F1/18
- H05K7/20
- CPC F16F1/185
- Nvidia corporation
- G02C9/00
- G02B27/01
- CPC G02C9/00
- G06F21/62
- CPC G06F21/6218
- G06F21/85
- G06F21/60
- CPC G06F21/85
- G06N3/084
- CPC G06N3/084
- G06N5/04
- G06N20/00
- CPC G06N5/04
- G06F9/50
- CPC G06N20/00
- G06T7/50
- G06T7/13
- CPC G06T7/50
- G06T15/06
- G06T7/40
- G06V10/54
- CPC G06T15/06
- G06T15/50
- G06T7/90
- G06V10/77
- G06V10/82
- CPC G06T15/506
- G06V20/59
- G06F3/01
- G06N3/02
- CPC G06V20/597
- H04B10/2581
- G02B6/42
- H04J14/02
- CPC H04B10/2581
- CPC H04J14/0283
- H04L43/0852
- G06F3/14
- H04L43/065
- H04L43/106
- CPC H04L43/0858