NVIDIA Corporation patent applications on March 6th, 2025
Patent Applications by NVIDIA Corporation on March 6th, 2025
NVIDIA Corporation: 25 patent applications
NVIDIA Corporation has applied for patents in the areas of B25J9/16 (2), G06N20/00 (2), H01F27/28 (2), H01F27/24 (2), G06V10/77 (2) H01F27/24 (2), B25J9/163 (1), G06V10/764 (1), H04N23/84 (1), H04N19/159 (1)
With keywords such as: data, systems, core, images, pattern, color, processing, eight, figure, and based in patent application abstracts.
Patent Applications by NVIDIA Corporation
20250073897. TRAJECTORY TRACKING USING PATH SIGNATURES_simplified_abstract_(nvidia corporation)
Inventor(s): Motoya Ohnishi of Seattle WA (US) for nvidia corporation, Iretiayo Akinola of Gig Harbor WA (US) for nvidia corporation, Ajay Uday Mandlekar of Cupertino CA (US) for nvidia corporation, Jie Xu of Bellevue WA (US) for nvidia corporation, Fabio Tozeto Ramos of Seattle WA (US) for nvidia corporation
IPC Code(s): B25J9/16, B60W60/00
CPC Code(s): B25J9/163
Abstract: apparatuses, systems, and techniques to determine a trajectory of an object along a path. in at least one embodiment, one or more path signatures are used to identify one or more actions to be performed by an object to track a reference path.
Inventor(s): Ajay Uday Mandlekar of Cupertino CA (US) for nvidia corporation, Soroush Nasiriany of Austin TX (US) for nvidia corporation, Bowen Wen of Bellevue WA (US) for nvidia corporation, Iretiayo Akinola of Gig Harbor WA (US) for nvidia corporation, Yashraj Shyam Narang of Mountain View CA (US) for nvidia corporation, Linxi Fan of San Jose CA (US) for nvidia corporation, Yuke Zhu of Austin TX (US) for nvidia corporation, Dieter Fox of Seattle WA (US) for nvidia corporation
IPC Code(s): B25J9/16, B25J19/02
CPC Code(s): B25J9/1664
Abstract: apparatuses, systems, and techniques to generate data to train a robotic device to perform tasks. in at least one embodiment, one or more first videos of a robotic device performing a task is used to generate one or more second videos of the robotic device performing the task differently than depicted in the one or more first videos.
Inventor(s): Ofek Abadi of Nahariya (IL) for nvidia corporation, Naor Peretz of Kfar Yona (IL) for nvidia corporation
IPC Code(s): G01K15/00, G01K1/02, G01K7/00
CPC Code(s): G01K15/005
Abstract: an integrated circuit includes a plurality of thermal sensors integrated within digital domain circuitry and powered by a digital supply voltage. an activation register receives activation data from a tester unit. control logic, in response to the activation register being written with the activation data, enters a thermal calibration mode, deactivates a plurality of digital logic units of the digital domain circuitry, and causes a reference clock received from the tester to drive the plurality of the thermal sensors.
20250077280. THERMAL AWARE THREAD SCHEDULING_simplified_abstract_(nvidia corporation)
Inventor(s): Sreedhar Narayanaswamy of Sunnyvale CA (US) for nvidia corporation, Jun Xu of Foster City CA (US) for nvidia corporation, Krishna Sitaraman of Campbell CA (US) for nvidia corporation, Manish Saini of Cupertina CA (US) for nvidia corporation, Aleksandr Frid of San Francisco CA (US) for nvidia corporation
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4893
Abstract: apparatuses, systems, and techniques to control utilization of a combination of processing cores. in at least one embodiment, utilization of a combination of processing cores is controlled based, at least in part, on historic thermal characteristics of the combination of the processing cores.
20250077444. POST-SEND SUBMISSION COALESCING_simplified_abstract_(nvidia corporation)
Inventor(s): Pak Markthub of Tokyo (JP) for nvidia corporation, James Dinan of Westford MA (US) for nvidia corporation
IPC Code(s): G06F13/16, G06F9/50
CPC Code(s): G06F13/1642
Abstract: a system is described having an input/output (io) device and a processing unit coupled with the io device. the processing unit is enabled to elect a thread from among a plurality of threads to atomically update a queue head pointer, uses the queue head pointer to reserve space in a plurality of memory registers for work queue elements belonging to the plurality of threads, and submit the work queue elements to the io device.
Inventor(s): Manan PATEL of Santa Jose CA (US) for nvidia corporation, Jack CHOQUETTE of Palo Alto CA (US) for nvidia corporation, Alexander L. MINKIN of Los Altos CA (US) for nvidia corporation, Maciej Tyrlik of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F17/15, G06F17/16
CPC Code(s): G06F17/153
Abstract: systems and methods for efficient convolution based on matrix multiply and add (mma) are described. an example processor having a plurality of processing lanes is configured to perform convolution of a matrix of activation elements and a filter matrix in accordance with a configurable series of instructions including a plurality of mma instructions and shift instructions while reusing activation elements already loaded to the processor or associated memory over a plurality of mma operations. the filter elements are held stationary at inputs to the processor for multiple cycles for multiple mma operations while activations are streamed in. associated methods are also described.
Inventor(s): Marc LAW of Toronto (CA) for nvidia corporation, Karsten Julian KREIS of Vancouver (CA) for nvidia corporation, Haggai MARON of Rehvot (IL) for nvidia corporation
IPC Code(s): G06F18/20, G06F18/214
CPC Code(s): G06F18/29
Abstract: in various examples, systems and methods are disclosed relating to graph generation. one system includes one or more processing circuits configured to receive a first data structure including one or more relationships between a plurality of components. the one or more processing circuits are further configured to encode, using a predefined function, a second data structure determined based on the first data structure to generate a noisy representation of the second data structure. the one or more processing circuits are further configured to decode, using one or more models, the first data structure based on feature extraction and pattern analysis of the noisy representation.
20250077629. RIGHTS MANAGEMENT FOR DIGITAL ASSETS_simplified_abstract_(nvidia corporation)
Inventor(s): Michael Kass of Los Altos Hills CA (US) for nvidia corporation
IPC Code(s): G06F21/10, G06F21/64, H04L9/00
CPC Code(s): G06F21/1015
Abstract: approaches presented herein provide for the management of owned digital assets. an entity may obtain ownership of (or other rights to) a unique digital asset, and information regarding this ownership can be stored to a trusted registry, such as a blockchain. the only true copy of this digital asset is stored to a secure environment, with no identical copy of this digital being available outside this secure environment. a party may be able to obtain a copy, version, or view of this digital asset that will differ in at least some way from the true asset. for a 3d model asset, this may include providing only a 2d image of that 3d model that was rendered in a secure environment. in this way, a true reconstruction of the 3d model will be unable to be generated outside of the secure environment. if the asset was obtained through procedural generation, information about the generation (and ownership of one or more aspects of that generation) may be stored to the registry as well.
Inventor(s): Matthijs Jules VAN KEIRSBILCK of Berlin (DE) for nvidia corporation, Alexander Georg KELLER of Berlin (DE) for nvidia corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: one embodiment of a computer-implemented method includes executing at least one first operation on each component of one or more feature vectors along time and at least one second operation on one or more feature vectors along one or more feature dimensions, where the at least one first operation is based on an analytic function and the at least one second operation is based on a machine learned function.
20250078199. Unified Memory GPU with Localized Mode_simplified_abstract_(nvidia corporation)
Inventor(s): Wish GANDHI of Sunnyvale CA (US) for nvidia corporation, Ze LONG of San Jose CA (US) for nvidia corporation, Kun FANG of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T1/60
CPC Code(s): G06T1/60
Abstract: a gpu can selectively confine software function execution and associated data storage resources to locally-connected processing/storage components, thereby minimizing latency and other overhead that would otherwise be needed to access more remote resources. the gpu can selectively permit other software function execution and associated data storage resources to range across non-locally-connected processing/storage components when more processing and/or storage resources are required.
Inventor(s): Wangren Xu of San Jose CA (US) for nvidia corporation
IPC Code(s): G06T5/00, G06N3/0464, G06T5/50, G06T7/20, G06T11/00, G06V10/776, G06V10/96
CPC Code(s): G06T5/70
Abstract: disclosed are apparatuses, systems, and techniques for testing and training hardware devices and computer vision models using images augmented with noise. in one embodiment, the techniques include augmenting a plurality of images with noise to generate a plurality of sets of noise-augmented images (nais). individual sets of nais include noise of a respective noise level, applying one or more sets of nais of the plurality of sets of nais to determine one or more accuracy metrics characterizing performance of a computer vision (cv) model for one or more noise levels of respective one or more sets of nais, and publishing the cv model in association with the one or more accuracy metrics.
Inventor(s): Dae Jin Kim of Santa Clara CA (US) for nvidia corporation, Rajath Shetty of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T7/80, G01S7/497, G06T7/70, G06V20/56
CPC Code(s): G06T7/80
Abstract: in various examples, interior sensor calibration using exterior features for autonomous systems and applications is described herein. systems and methods are disclosed that use one or more features that are located exterior to a vehicle, such as one or more tags located in the environment surrounding the vehicle, to determine one or more values for one or more calibration parameters that calibrate an interior sensor of the vehicle with respect to a reference coordinate system of the vehicle. for instance, such as when the vehicle is located at a calibration station, the sensor may generate sensor data representing a sensor representation, where at least a portion of the sensor representation is associated with a feature that is visible through a transparent component (e.g., a window) of the vehicle. the sensor data may then be used to calibrate the sensor with respect to the coordinate system.
Inventor(s): Dmitriy Zhdan of Korolev (RU) for nvidia corporation, Evgeny Makarov of Moscow (RU) for nvidia corporation
IPC Code(s): G06T15/06, G06N20/00, G06T5/20, G06T5/70, G06T15/50
CPC Code(s): G06T15/06
Abstract: recurrent blurring may be used to render frames of a virtual environment, where the radius of a filter for a pixel is based on a number of successfully accumulated frames that correspond to that pixel. to account for rejections of accumulated samples for the pixel, ray-traced samples from a lower resolution version of a ray-traced render may be used to increase the effective sample count for the pixel. parallax may be used to control the accumulation speed along with an angle between a view vector that corresponds to the pixel. a magnitude of one or more dimensions of a filter applied to the pixel may be based on an angle of a view vector that corresponds to the pixel to cause reflections to elongate along an axis under glancing angles. the dimension(s) may be based on a direction of a reflected specular lobe associated with the pixel.
Inventor(s): Weiheng Chai of Santa Clara CA (US) for nvidia corporation, Anurag Singh of Santa Clara CA (US) for nvidia corporation, Yifang Xu of San Jose CA (US) for nvidia corporation
IPC Code(s): G06V10/764, G06V10/44, G06V10/774, G06V10/776, G06V10/778, G06V20/40
CPC Code(s): G06V10/764
Abstract: in various examples, data mining using group classifiers for autonomous and semi-autonomous systems and applications is described. for instance, systems and methods may train and use a classifier that is configured to determine whether data samples (e.g., images) represent objects associated with a group in various training and/or mining iterations. for instance, after each iteration, the classifier may become more accurate such that the classifier is able to better identify first data samples that are associated with the group (e.g., positive images) and/or second data samples that are not associated with the group (e.g., negative images). additionally, the systems and methods may use another classifier to determine classifications associated with objects represented by at least the first data samples that are associated with the group. the systems and method may then store these first data samples and the classifications in one or more databases.
Inventor(s): Bingyin ZHAO of Central SC (US) for nvidia corporation, Jose Manuel ALVAREZ LOPEZ of Mountain View CA (US) for nvidia corporation, Anima ANANDKUMAR of Pasadena CA (US) for nvidia corporation, Shi Yi LAN of San Jose CA (US) for nvidia corporation, Zhiding YU of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06V10/82, G06V10/77
CPC Code(s): G06V10/82
Abstract: one embodiment of the present invention sets forth a technique for training an image classifier. the technique includes training a first vision transformer model to generate patch labels for corresponding images patches of images, converting the patch labels to token labels, and training a second vision transformer model to classify images based on the token labels.
Inventor(s): Ruiqi ZHAO of Shanghai (CN) for nvidia corporation, Jonathan Edward BARKER of Boulder CO (US) for nvidia corporation, Tommi KOIVISTO of Espoo (FI) for nvidia corporation, Yu ZHANG of Sunnyvale CA (US) for nvidia corporation, Shuang WU of Fremont CA (US) for nvidia corporation, Yixuan LIN of San Jose CA (US) for nvidia corporation, Ge CONG of Pleasanton CA (US) for nvidia corporation, Andrew TAO of Los Altos CA (US) for nvidia corporation, Kezhao CHEN of Beijing (CN) for nvidia corporation
IPC Code(s): G06V20/56, G01S17/89, G06V10/764, G06V10/77, G06V10/774
CPC Code(s): G06V20/588
Abstract: in various examples, multimodal image data may be used to generate a set of top-down tile images, which are applied to a deep neural network generator architecture model to produce lane marking-specific heatmap images corresponding to the set of top-down tile images. the multimodal sensor data may include lidar-captured intensity channel data, lidar-captured feature height channel data, and optical color image channel data. the set of top-down tile images may be processed by the generator model to automatically detect lane boundaries and navigation boundaries to generate pixel-level heatmap images that may classify lane markings by marking characteristics such as line type and/or color. the generator model may comprise an encoder-decoder architecture, with multiscale feature extraction and/or context extraction functional layers intervening between the encoder model and the decoder model.
Inventor(s): Hainan XU of New York NY (US) for nvidia corporation, Boris GINSBURG of Sunnyvale CA (US) for nvidia corporation, Zhehuai CHEN of Odessa FL (US) for nvidia corporation, Fei JIA of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G10L15/187, G06F40/284, G10L15/02, G10L15/16
CPC Code(s): G10L15/187
Abstract: one or more embodiments include: receiving a first frame of acoustic input and one or more prior textual tokens associated with a prior frame of the acoustic input, wherein the prior textual token represents one or more spoken word included in the acoustic input; generating a multi-dimensional embedding associated with the prior textual token, wherein each dimension of the embedding represents a different characteristic of the prior textual token, and at least one dimension of the embedding represents pronunciation information associated with the prior textual token; and generating a textual token associated with the first frame based at least on an encoded representation of the first frame and the multi-dimensional embedding associated with the prior textual token.
Inventor(s): Taejin Park of San Jose CA (US) for nvidia corporation, Kunal Dhawan of San Jose CA (US) for nvidia corporation, Nithin Rao Koluguri of Milpitas CA (US) for nvidia corporation, Jagadeesh Balam of Campbell CA (US) for nvidia corporation
IPC Code(s): G10L17/06, G10L17/02
CPC Code(s): G10L17/06
Abstract: disclosed are apparatuses, systems, and techniques that leverage one or more language models (lms)—such as large language models (llms—for efficient multi-speaker speech recognition. the techniques include processing, using a speaker diarization model, an audio feature to generate a first association of the audio feature with one or more prospective speakers, the audio feature being representative of one or more spoken words. the techniques further include providing, to an lm, a first prompt requesting the lm to identify a second association of the one or more spoken words with the one or more prospective speakers and receiving, from the lm, a first response identifying the second association of the one or more spoken words with the one or more prospective speakers. the techniques further include determining, using the first association and the second association, one or more speakers that produced the one or more spoken words.
Inventor(s): Youssef Elasser of Trenton NJ (US) for nvidia corporation, Sudhir Kudva of Dublin CA (US) for nvidia corporation, Mostafa Mosa of San Jose CA (US) for nvidia corporation
IPC Code(s): H01F27/24, H01F27/28
CPC Code(s): H01F27/24
Abstract: a magnetic inductor core forms a three-dimensional figure eight pattern. an upper member of the core forms an upper half of the figure eight pattern, a lower member of the core forms a lower half of the figure eight pattern, and central portions of the upper and lower members are separated from one another in a depth dimension by a main gap that passes transversely through the core from left to right sides of the figure eight pattern. the upper and lower members are joined at top and bottom sides of the figure eight pattern by core members that extend in the depth dimension between the upper and lower members. coupled inductor components are be formed using the core such that magnetic flux associated with electrical current flowing in the inductor windings follows the figure eight pattern of the core in opposite directions, producing a flux cancelation effect inside the core.
Inventor(s): Youssef Elasser of Trenton NJ (US) for nvidia corporation, Sudhir Kudva of Dublin CA (US) for nvidia corporation, Mostafa Mosa of San Jose CA (US) for nvidia corporation
IPC Code(s): H01F27/24, H01F27/28
CPC Code(s): H01F27/24
Abstract: a magnetic inductor core forms a three-dimensional figure eight pattern. an upper member of the core forms an upper half of the figure eight pattern, a lower member of the core forms a lower half of the figure eight pattern, and central portions of the upper and lower members are separated from one another in a depth dimension by a main gap that passes transversely through the core from left to right sides of the figure eight pattern. the upper and lower members are joined at top and bottom sides of the figure eight pattern by core members that extend in the depth dimension between the upper and lower members. coupled inductor components are be formed using the core such that magnetic flux associated with electrical current flowing in the inductor windings follows the figure eight pattern of the core in opposite directions, producing a flux cancelation effect inside the core.
Inventor(s): Elad Mentovich of Tel Aviv (IL) for nvidia corporation, Dongji Xie of Gilroy CA (US) for nvidia corporation, Ron Chao of San Diego CA (US) for nvidia corporation
IPC Code(s): H01L23/00, H01L23/31, H01L23/538, H01L25/065, H01L25/16
CPC Code(s): H01L23/576
Abstract: a secure electronic component assembly is described herein for ensuring the physical integrity of an integrated circuit (ic). the secure electronic component assembly may comprise a printed circuit board (pcb), an integrated circuit (ic) mounted on the pcb, and a security chip that is operatively coupled to the ic. the ic may comprise a plurality of solder balls operatively coupled thereto and configured for physical and electrical connection between the ic and the pcb. the security chip is configured to detect a potential tampering of the ic.
20250080256. WIRELESS TRANSMISSION ERROR RATE PREDICTION_simplified_abstract_(nvidia corporation)
Inventor(s): Chengzhang Li of Blacksburg VA (US) for nvidia corporation, Yan Huang of Santa Clara CA (US) for nvidia corporation, Christian Ibars Casas of San Jose CA (US) for nvidia corporation, James Hansen Delfeld of Austin TX (US) for nvidia corporation, Nidhi Tomar of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H04B17/373, H04B17/336, H04B17/391
CPC Code(s): H04B17/373
Abstract: apparatuses, systems, and techniques to predict wireless transmission error rates. in at least one embodiment, a processor includes one or more circuits to predict one or more wireless transmission error rates based, at least in part, on one or more signal to noise ratio (snr) measurements.
Inventor(s): Fateh SABEH of Den Haag (NL) for nvidia corporation, Mohamadreza MARANDIAN HAGH of San Jose CA (US) for nvidia corporation, Varun VIJAYA KUMAR of San Jose CA (US) for nvidia corporation, Shridhar MAJALI of San Francisco CA (US) for nvidia corporation, Harsh MANIAR of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): H04N19/159, H04N19/154, H04N19/172, H04N19/65, H04N19/88
CPC Code(s): H04N19/159
Abstract: in various examples, systems, devices and methods are disclosed relating to enhancing the efficiency and reducing the delay of error resilience in multimedia communication systems. the systems, devices and methods can include a computer system determining a sliding frame window (or a sliding reference window) for a video stream. the size of the sliding frame window represents a minimum separation between reference frames and corresponding inter frames. the computer system can encode a plurality of video frames of the video stream according to the size of the sliding frame window, such that a separation between any pair of video frames of the plurality of video frames including a reference frame and a corresponding inter-frame is greater than or equal to the size of the sliding frame window.
20250080863. METHOD OF COLOR CORRECTION_simplified_abstract_(nvidia corporation)
Inventor(s): Chengwu Cui of Gig Harbor WA (US) for nvidia corporation, Sean Midthun Pieper of Waldport OR (US) for nvidia corporation, Du-Yong Ng of San Jose CA (US) for nvidia corporation, Douglas John Taylor of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H04N23/84, G06T7/00, G06T7/90, G06T11/00, G06V20/52
CPC Code(s): H04N23/84
Abstract: apparatuses, systems, and techniques for performing color correction are presented. in at least one embodiment, a color mapping model may be identified that maps colors, within a subspace of an input color space localized around a target color, to an adjusted color space and applied to an input image to adjust a value of one or more pixels of the input image that fall within the subspace. in at least one embodiment, a color mapping model may be initialized that maps colors, within a subspace of an input color space localized around a target color, to an adjusted color space. at least one parameter of the color mapping model may be adjusted to reduce an amount of visible artifacts produced by the color mapping model.
20250081349. SECURE ELECTRONIC COMPONENT ASSEMBLY_simplified_abstract_(nvidia corporation)
Inventor(s): Elad Mentovich of Tel Aviv (IL) for nvidia corporation, Dongji Xie of Gilroy CA (US) for nvidia corporation, Ron Chao of San Diego CA (US) for nvidia corporation, Ryan Albright of Beaverton OR (US) for nvidia corporation
IPC Code(s): H05K1/18, H05K1/02, H05K3/12, H05K3/28
CPC Code(s): H05K1/181
Abstract: a secure electronic component assembly is described herein for ensuring the physical integrity of an integrated circuit (ic). the secure electronic component assembly may comprise a printed circuit board (pcb), an integrated circuit (ic) mounted on the pcb, and an underfill material disposed between the ic and the pcb. the underfill material comprises a detection agent that is configured to change a state of the ic in response to exposure to an external environment, wherein the change in the state of the ic is indicative of a tamper condition.
- NVIDIA Corporation
- B25J9/16
- B60W60/00
- CPC B25J9/163
- Nvidia corporation
- B25J19/02
- CPC B25J9/1664
- G01K15/00
- G01K1/02
- G01K7/00
- CPC G01K15/005
- G06F9/48
- CPC G06F9/4893
- G06F13/16
- G06F9/50
- CPC G06F13/1642
- G06F17/15
- G06F17/16
- CPC G06F17/153
- G06F18/20
- G06F18/214
- CPC G06F18/29
- G06F21/10
- G06F21/64
- H04L9/00
- CPC G06F21/1015
- G06N20/00
- CPC G06N20/00
- G06T1/60
- CPC G06T1/60
- G06T5/00
- G06N3/0464
- G06T5/50
- G06T7/20
- G06T11/00
- G06V10/776
- G06V10/96
- CPC G06T5/70
- G06T7/80
- G01S7/497
- G06T7/70
- G06V20/56
- CPC G06T7/80
- G06T15/06
- G06T5/20
- G06T5/70
- G06T15/50
- CPC G06T15/06
- G06V10/764
- G06V10/44
- G06V10/774
- G06V10/778
- G06V20/40
- CPC G06V10/764
- G06V10/82
- G06V10/77
- CPC G06V10/82
- G01S17/89
- CPC G06V20/588
- G10L15/187
- G06F40/284
- G10L15/02
- G10L15/16
- CPC G10L15/187
- G10L17/06
- G10L17/02
- CPC G10L17/06
- H01F27/24
- H01F27/28
- CPC H01F27/24
- H01L23/00
- H01L23/31
- H01L23/538
- H01L25/065
- H01L25/16
- CPC H01L23/576
- H04B17/373
- H04B17/336
- H04B17/391
- CPC H04B17/373
- H04N19/159
- H04N19/154
- H04N19/172
- H04N19/65
- H04N19/88
- CPC H04N19/159
- H04N23/84
- G06T7/00
- G06T7/90
- G06V20/52
- CPC H04N23/84
- H05K1/18
- H05K1/02
- H05K3/12
- H05K3/28
- CPC H05K1/181