NVIDIA Corporation patent applications on March 20th, 2025
Patent Applications by NVIDIA Corporation on March 20th, 2025
NVIDIA Corporation: 21 patent applications
NVIDIA Corporation has applied for patents in the areas of B60W60/00 (3), G06T15/06 (3), G06F9/50 (3), G06T17/00 (2), G06N3/0455 (2) G06T15/06 (3), B60W60/001 (2), B25J9/1661 (1), H04N19/65 (1), H04L47/122 (1)
With keywords such as: neural, network, representation, input, into, based, device, ray, technique, and structure in patent application abstracts.
Patent Applications by NVIDIA Corporation
20250091207. MULTI-TASK GRASPING_simplified_abstract_(nvidia corporation)
Inventor(s): Wentao Yuan of Belleuve WA US for nvidia corporation, Adithyavairavan Murali of Seattle WA US for nvidia corporation, Arsalan Mousavian of Seattle WA US for nvidia corporation, Dieter Fox of Seattle WA US for nvidia corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/1661
Abstract: apparatuses, systems, and techniques to determine a grasp and placement of an object in an environment. in at least one embodiment, one or more neural networks are used to identify one or more grasping and placement masks used to manipulate an object.
Inventor(s): Katie Z. Luo of Ithaca NY US for nvidia corporation, Yue Wang of Los Angeles CA US for nvidia corporation, Xinshuo Weng of North York CA for nvidia corporation, Marco Pavone of Stanford CA US for nvidia corporation, Yan Wang of Santa Clara CA US for nvidia corporation
IPC Code(s): B60W60/00, G01C21/30
CPC Code(s): B60W60/001
Abstract: in the context of autonomous driving, the recognition of lane topologies is required for the vehicle to make well-informed and prudent decisions such as lane changes, navigation through intricate intersections, and smooth merging. current autonomous driving systems rely solely on sensor (e.g. camera) inputs to recognize lane topology. as a result, poor sensor data will have a direct negative impact on lane topology recognition. the present disclosure augments lane topology reasoning with a standard definition navigation map for use in autonomous driving applications.
Inventor(s): Kang Wang of Bellevue WA US for nvidia corporation, Yue Wu of Mountain View CA US for nvidia corporation, Minwoo Park of Saratoga CA US for nvidia corporation, Gang Pan of Fremont CA US for nvidia corporation
IPC Code(s): B60W60/00, B60W40/09, G06N3/02
CPC Code(s): B60W60/001
Abstract: in various examples, a 3d surface structure such as the 3d surface structure of a road (3d road surface) may be observed and estimated to generate a 3d point cloud or other representation of the 3d surface structure. since the estimated representation may be sparse, a deep neural network (dnn) may be used to predict values for a dense representation of the 3d surface structure from the sparse representation. for example, a sparse 3d point cloud may be projected to form a sparse projection image (e.g., a sparse 2d height map), which may be fed into the dnn to predict a dense projection image (e.g., a dense 2d height map). the predicted dense representation of the 3d surface structure may be provided to an autonomous vehicle drive stack to enable safe and comfortable planning and control of the autonomous vehicle.
Inventor(s): Yuxiao CHEN of Newark CA US for nvidia corporation, Kai-Chieh HSU of Princeton NJ US for nvidia corporation, Karen Yan Ming LEUNG of Seattle WA US for nvidia corporation, Marco PAVONE of Stanford CA US for nvidia corporation
IPC Code(s): B60W60/00
CPC Code(s): B60W60/0027
Abstract: in various examples, a trajectory prediction model provides interpretable trajectory predictions for autonomous and semi-autonomous systems and applications via counterfactual game-theoretic reasoning. model-based latent variables can be formulated through responsibility evaluations. responsibility can be broken into multiple components, such as safety and courtesy. responsibility can be quantified, for example, by answering a counterfactual question: could an agent have executed differently to respect other agents' safety and be more courteous to others' plans? the framework can be used to abstract computed responsibility sequences into different responsibility levels and ground latent levels into a trajectory prediction model able to render interpretable and accurate inferences about trajectory.
Inventor(s): David Paul Mohr of Houston TX US for nvidia corporation
IPC Code(s): G06F1/26, H02J7/00, H02J7/34
CPC Code(s): G06F1/263
Abstract: devices, apparatuses, systems, and methods for power delivery and management are provided. an example power delivery apparatus includes a first input electrically coupled with a first power source, an output electrically coupled with at least a first computing device, a primary power path electrically coupling the first input and the output, and a first energy storage path electrically coupling the first input and the output. the power delivery apparatus further includes an energy storage device electrically coupled with the first energy storage path that operates to store energy, and power supply units (psus) electrically coupled with the primary power path and the first energy storage path. the psus selectively route power received via the first input from the first power source to the primary power path for powering the first computing device or the first energy storage path for storage by the energy storage device.
Inventor(s): Yury URALSKY of Los Gatos CA US for nvidia corporation, Henry MORETON of Woodside CA US for nvidia corporation, Matthijs de SMEDT of San Jose CA US for nvidia corporation, Lei YANG of Santa Clara CA US for nvidia corporation
IPC Code(s): G06F9/50, G06T1/20, G06T1/60
CPC Code(s): G06F9/5038
Abstract: the present technology augments the gpu compute model to provide system-provided data marshalling characteristics of graphics pipelining to increase efficiency and reduce overhead. a simple scheduling model based on scalar counters (e.g., semaphores) abstract the availability of hardware resources. resource releases can be done programmatically, and a system scheduler only needs to track the states of such counters/semaphores to make work launch decisions. semantics of the counters/semaphores are defined by an application, which can use the counters/semaphores to represent the availability of free space in a memory buffer, the amount of cache pressure induced by the data flow in the network, or the presence of work items to be processed.
Inventor(s): Wonmin BYEON of Santa Cruz CA US for nvidia corporation, Sudarshan BABU of Chicago IL US for nvidia corporation, Shalini DE MELLO of San Francisco CA US for nvidia corporation, Jan KAUTZ of Lexington MA US for nvidia corporation
IPC Code(s): G06N3/0895
CPC Code(s): G06N3/0895
Abstract: one embodiment of the present invention sets forth a technique for training a transformer neural network. the technique includes inputting a first task token and a first set of samples into the transformer neural network and training the transformer neural network using a first set of losses between predictions generated by the transformer neural network from the first task token and first set of samples as well as a first set of labels. the technique also includes converting the first task token into a second task token that is larger than the first task token, inputting the second task token and a second set of samples into the transformer neural network, and training the transformer neural network using a second set of losses between predictions generated by the transformer neural network from the second task token and the second set of samples as well as a second set of labels.
Inventor(s): Wonmin BYEON of Santa Cruz CA US for nvidia corporation, Sudarshan BABU of Chicago IL US for nvidia corporation, Shalini DE MELLO of San Francisco CA US for nvidia corporation, Jan KAUTZ of Lexington MA US for nvidia corporation
IPC Code(s): G06N3/096, G06N3/0455
CPC Code(s): G06N3/096
Abstract: one embodiment of the present invention sets forth a technique for executing a transformer neural network. the technique includes executing a first attention unit included in the transformer neural network to convert a first input token into a first query, a first key, and a first plurality of values, where each value included in the first plurality of values represents a sub-task associated with the transformer neural network. the technique also includes computing a first plurality of outputs associated with the first input token based on the first query, the first key, and the first plurality of values. the technique further includes performing a task associated with an input corresponding to the first input token based on the first input token and the first plurality of outputs.
20250094825. NEURAL NETWORK ARCHITECTURE CONSTRUCTION_simplified_abstract_(nvidia corporation)
Inventor(s): Chong Yu of Shanghai CN for nvidia corporation
IPC Code(s): G06N3/0985, G06N3/0455
CPC Code(s): G06N3/0985
Abstract: apparatuses, systems, and techniques to construct a neural network architecture. in at least one embodiment, candidate neural components may be selected for the neural network by jointly updating performance metric masks attached to these candidate neural components and a union neural network comprising all candidate neural components.
Inventor(s): Po-An Tsai of Somerville MA US for nvidia corporation, Geonhwa Jeong of Atlanta GA US for nvidia corporation, Jeffrey Michael Pool of Chapel Hill NC US for nvidia corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: machine learning is a process that learns a model from a given dataset, where the model can then be used to make a prediction about new data. in order to reduce the size, computation, and latency of a machine learning model, a compression technique can be employed which includes model sparsification and quantization. to limit the extent to which the quality of the model is impacted when uniformly applying sparsification and quantization to all values of the model, the present disclosure provides for a hybrid sparsification and quantization of the model.
20250095126. TRAINING A NEURAL NETWORK USING LUMINANCE_simplified_abstract_(nvidia corporation)
Inventor(s): Sean Midthun Pieper of San Jose CA US for nvidia corporation, Robin Brian Jenkin of Santa Clara CA US for nvidia corporation
IPC Code(s): G06T5/92, G06T5/50, G06T7/80, G06T11/00
CPC Code(s): G06T5/92
Abstract: apparatuses, systems, and techniques to process luminance and/or radiance values of one or more images from one or more cameras using one or more neural networks to perform a machine vision task. in at least one embodiment, one or more neural networks determine detection difficulty levels of objects within the one or more images and performs a machine vision task based on the determined detection difficulty levels of objects within images associated with that ask.
Inventor(s): Zheng TANG of Bothell WA US for nvidia corporation, Sujit BISWAS of San Jose CA US for nvidia corporation, Ganapathy Seshadri Cadungude AIYER of San Jose CA US for nvidia corporation, Shuo WANG of San Jose CA US for nvidia corporation, Akshay AGRAWAL of Santa Clara CA US for nvidia corporation, Sameer Satish PUSEGAONKAR of San Francisco CA US for nvidia corporation
IPC Code(s): G06T7/292, G06V10/762
CPC Code(s): G06T7/292
Abstract: in various examples, multi-subject multi-camera tracking for high-density environments is provided. in some embodiments, an mtmc tracking system may associate previously initialized behavior states with currently generated behaviors clusters based on selecting between subject trajectory tracking and cluster matching algorithms. the system may receive image data comprising feeds from a plurality of optical images sensors. the system may generate behavior clusters and apply trajectory tracking to determine if the prior behavior states can be propagated based on a continuity of trajectory analysis. if behavior clusters cannot be associated based on trajectory tracking, a matching algorithm may be applied to the set of behavior clusters. for matched clusters, a matched a prior behavior state may be assigned to the cluster and propagated forward. if a cluster does not match with a prior behavior state, a new global id and behavior state may be initialized based on representations forming the cluster.
20250095229. SCENE GENERATION USING NEURAL RADIANCE FIELDS_simplified_abstract_(nvidia corporation)
Inventor(s): Yue Wang of Mountain View CA US for nvidia corporation, Jiawei Yang of Los Angeles CA US for nvidia corporation, Boris Ivanovic of Mountain View CA US for nvidia corporation, Xinshuo Weng of North York CA for nvidia corporation, Or Litany of Haifa IL for nvidia corporation, Danfei Xu of Atlanta GA US for nvidia corporation, Seung Wook Kim of Toronto CA for nvidia corporation, Sanja Fidler of Toronto CA for nvidia corporation, Marco Pavone of Stanford CA US for nvidia corporation, Boyi Li of Berkeley CA US for nvidia corporation, Tong Che of San Jose CA US for nvidia corporation
IPC Code(s): G06T11/00, G06T17/00, G06V10/44, H04N13/279
CPC Code(s): G06T11/001
Abstract: apparatuses, systems, and techniques to generate an image of an environment. in at least one embodiment, one or more neural networks are used to identify one or more static and dynamic features of an environment to be used to generate a representation of the environment.
Inventor(s): Zian Wang of Toronto CA for nvidia corporation, Tianchang Shen of Markham CA for nvidia corporation, Jun Gao of North York CA for nvidia corporation, Merlin Nimier-David of Nyon CH for nvidia corporation, Thomas Müller-Höhne of Baar CH for nvidia corporation, Alexander Keller of Berlin DE for nvidia corporation, Sanja Fidler of Toronto CA for nvidia corporation, Zan Gojcic of Uitikon Waldegg, Zurich CH for nvidia corporation, Nicholas Mark Worth Sharp of Seattle WA US for nvidia corporation
IPC Code(s): G06T15/06, G06V10/44
CPC Code(s): G06T15/06
Abstract: in various examples, images (e.g., novel views) of an object may be rendered using an optimized number of samples of a 3d representation of the object. the optimized number of the samples may be determined based at least on casting rays into a scene that includes the 3d representation of the object and/or an acceleration data structure corresponding to the object. the acceleration data structure may include features corresponding to characteristics of the object, and the features may be indicative of the number of samples to be obtained from various portions of the 3d representation of the object to render the images. in some examples, the 3d representation may be a neural radiance field that includes, as a neural output, a spatially varying kernel size predicting the characteristics of the object, and the features of the acceleration data structure may be related to the spatially varying kernel size.
Inventor(s): Gregory MUTHLER of Austin TX US for nvidia corporation, John BURGESS of Austin TX US for nvidia corporation
IPC Code(s): G06T15/06, G06F9/30, G06F9/50, G06T15/08, G06T17/00
CPC Code(s): G06T15/06
Abstract: enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. for example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. the per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.
Inventor(s): Gregory MUTHLER of Austin TX US for nvidia corporation, John BURGESS of Austin TX US for nvidia corporation, Ronald Charles BABICH of Murrysville CA US for nvidia corporation, William Parsons Newhall of Woosdie CA US for nvidia corporation
IPC Code(s): G06T15/06, G06F9/48, G06F9/50, G06T17/10
CPC Code(s): G06T15/06
Abstract: techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. the allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. when reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. the compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. one or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.
Inventor(s): Wonmin BYEON of Santa Cruz CA US for nvidia corporation, Sudarshan BABU of Chicago IL US for nvidia corporation, Shalini DE MELLO of San Francisco CA US for nvidia corporation, Jan KAUTZ of Lexington MA US for nvidia corporation
IPC Code(s): G06V10/82, G06V10/776
CPC Code(s): G06V10/82
Abstract: one embodiment of the present invention sets forth a technique for executing a machine learning model. the technique includes performing a first set of training iterations to convert a prediction learning network into a first trained prediction learning network based on a first support set associated with a first set of classes. the technique also includes executing a first trained representation learning network to convert a first data sample into a first latent representation, where the first trained representation learning network is generated by training a representation learning network using a first query set, a first set of self-supervised losses, and a first set of supervised losses. the technique further includes executing the first trained prediction learning network to convert the first latent representation into a first prediction of a first class that is not included in the second set of classes.
Inventor(s): Zhehuai Chen of Odessa FL US for nvidia corporation, He Huang of Greenville SC US for nvidia corporation, Oleksii Hrinchuk of Santa Clara CA US for nvidia corporation, Andrei Andrusenko of Yerevan AM for nvidia corporation, Venkata Naga Krishna Chaitanya Puvvada of San Jose CA US for nvidia corporation, Subhankar Ghosh of Sunnyvale CA US for nvidia corporation, Jing Yao Li of Ontario CA for nvidia corporation, Jagadeesh Balam of Campbell CA US for nvidia corporation, Boris Ginsburg of Sunnyvale CA US for nvidia corporation
IPC Code(s): G10L15/26, G06F40/58
CPC Code(s): G10L15/26
Abstract: disclosed are apparatuses, systems, and techniques that implement training and deployment of speech-augmented language models for efficient capturing and processing of speech inputs. the techniques include processing, using a speech model, an audio input in a first language to generate a first portion of an input into a language model (lm). a second portion of the input into the lm includes represents a text context associated with the audio input. the techniques further include receiving, from the lm, an output that includes a speech-to-text conversion of the audio input.
Inventor(s): John Martin Snyder of San Rafael CA US for nvidia corporation, Nan Jiang of Sudbury MA US for nvidia corporation, Dennis Charles Abts of Rochester MN US for nvidia corporation, Larry Robert Dennison of Mendon MA US for nvidia corporation
IPC Code(s): H04L47/122, H04L47/125
CPC Code(s): H04L47/122
Abstract: a process to manage congestion in a network involves converting traffic received from the local endpoints to a bandwidth demand for one or more destination endpoint in a remote group, and determining a sum over the destination endpoints of a minimum of a maximum bandwidth of a link and a bandwidth demand to one or more of the remote endpoints.
Inventor(s): Swapnil Jagdish Rathi of Maharashtra IN for nvidia corporation, Viranjan Vishwasrao Pager of Pune IN for nvidia corporation, Bhushan Rupde of Maharashtra IN for nvidia corporation, Kaustubh Purandare of San Jose CA US for nvidia corporation
IPC Code(s): H04N19/65, H04N19/172, H04N19/46
CPC Code(s): H04N19/65
Abstract: a processing device encodes a frame of a video. the processing device determines a reference checksum of the frame. the processing device adds the reference checksum to supplemental metadata associated with the encoded frame of the video. the processing device transmits the encoded frame and the supplemental metadata including the reference checksum to a recipient. the recipient is to use the reference checksum to verify an integrity of the frame.
Inventor(s): Tahir Cader of Spokane Valley WA US for nvidia corporation, David Copeland of Nederland CO US for nvidia corporation, Elad Mentovich of Tel Aviv IL for nvidia corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/20272
Abstract: devices, apparatuses, systems, and methods are provided for hybrid thermal management in computing modules. an example computing module includes a first computing component having a first operating temperature and a second computing component having a second operating temperature. the first operating temperature is greater than the second operating temperature. the example computing module further includes a hybrid thermal management system including a cooling delivery device configured to receive a cooling fluid. the cooling delivery device defines a first section configured to dissipate heat generated by the first computing component and a second section configured to dissipate heat generated by the second computing component. the first section of the cooling delivery device may be fluidically isolated from the second section of the cooling delivery device or the second section may be in fluid communication with the first section.
- NVIDIA Corporation
- B25J9/16
- CPC B25J9/1661
- Nvidia corporation
- B60W60/00
- G01C21/30
- CPC B60W60/001
- B60W40/09
- G06N3/02
- CPC B60W60/0027
- G06F1/26
- H02J7/00
- H02J7/34
- CPC G06F1/263
- G06F9/50
- G06T1/20
- G06T1/60
- CPC G06F9/5038
- G06N3/0895
- CPC G06N3/0895
- G06N3/096
- G06N3/0455
- CPC G06N3/096
- G06N3/0985
- CPC G06N3/0985
- G06N20/00
- CPC G06N20/00
- G06T5/92
- G06T5/50
- G06T7/80
- G06T11/00
- CPC G06T5/92
- G06T7/292
- G06V10/762
- CPC G06T7/292
- G06T17/00
- G06V10/44
- H04N13/279
- CPC G06T11/001
- G06T15/06
- CPC G06T15/06
- G06F9/30
- G06T15/08
- G06F9/48
- G06T17/10
- G06V10/82
- G06V10/776
- CPC G06V10/82
- G10L15/26
- G06F40/58
- CPC G10L15/26
- H04L47/122
- H04L47/125
- CPC H04L47/122
- H04N19/65
- H04N19/172
- H04N19/46
- CPC H04N19/65
- H05K7/20
- G06F1/20
- CPC H05K7/20272