NVIDIA Corporation patent applications on March 13th, 2025
Patent Applications by NVIDIA Corporation on March 13th, 2025
NVIDIA Corporation: 8 patent applications
NVIDIA Corporation has applied for patents in the areas of G06V10/82 (2), G06V10/25 (2), B25J9/16 (1), G06N3/045 (1), G06V10/764 (1) B25J9/163 (1), B60W60/0015 (1), G06F9/3838 (1), G06F11/008 (1), G06F11/3466 (1)
With keywords such as: safety, systems, failure, availability, robot, examples, analysis, neural, techniques, and various in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Nathan Donald RATLIFF of Seattle WA (US) for nvidia corporation, Karl VAN WYK of Issaquah WA (US) for nvidia corporation, Ankur HANDA of Seattle WA (US) for nvidia corporation, Viktor MAKOVIICHUK of Santa Clara CA (US) for nvidia corporation, Yijie GUO of Seattle WA (US) for nvidia corporation, Jie XU of Bellevue WA (US) for nvidia corporation, Tyler LUM of Seattle WA (US) for nvidia corporation, Balakumar SUNDARALINGAM of San Jose CA (US) for nvidia corporation, Jingzhou LIU of Oakville (CA) for nvidia corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/163
Abstract: in various examples, systems and methods are disclosed relating to geometric fabrics for accelerated policy learning and sim-to-real transfer in robotics systems, platforms, and/or applications. for example, a system can provide an input indicative of a goal pose for a robot to a model to cause the model to generate an output, the output representing a plurality of points along a path for movement of the robot to the goal pose; and generate one or more control signals for operation of the robot based at least on the plurality of points along the path and a policy corresponding to one or more criteria for the operation of the robot. in examples, the system can provide the one or more control signals to the robot to cause the robot to move toward the goal pose.
Inventor(s): Julia Ng of San Jose CA (US) for nvidia corporation, Sachin Pullaikudi Veedu of Santa Clara CA (US) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation, Hanne Buur of Boulder CO (US) for nvidia corporation, Hans Jonas Nilsson of Los Gatos CA (US) for nvidia corporation, Hon Leung Lee of Bellevue WA (US) for nvidia corporation, Yunfei Shi of Santa Clara CA (US) for nvidia corporation, Charles Jerome Vorbach, Jr. of Bronxville NY (US) for nvidia corporation
IPC Code(s): B60W60/00, B60W30/095, G06F9/50
CPC Code(s): B60W60/0015
Abstract: in various examples, a safety decomposition architecture for autonomous machine applications is presented that uses two or more individual safety assessments to satisfy a higher safety integrity level (e.g., asil d). for example, a behavior planner may be used as a primary planning component, and a collision avoidance feature may be used as a diverse safety monitoring componentâsuch that both may redundantly and independently prevent violation of safety goals. in addition, robustness of the system may be improved as single point and systematic failures may be avoided due to the requirement that two independent failuresâe.g., of the behavior planner component and the collision avoidance componentâoccur simultaneously to cause a violation of the safety goals.
20250085973. KERNEL LAUNCH DEPENDENCIES_simplified_abstract_(nvidia corporation)
Inventor(s): Ze Long of San Jose CA (US) for nvidia corporation, Stephen Anthony Bernard Jones of San Francisco CA (US) for nvidia corporation, Pradeep Moorthy of Folsom CA (US) for nvidia corporation, Mark Theng of San Jose CA (US) for nvidia corporation
IPC Code(s): G06F9/38, G06T1/20
CPC Code(s): G06F9/3838
Abstract: apparatuses, systems, and techniques to execute cuda programs. in at least one embodiment, one or more software kernels are caused to indicate one or more dependencies among two or more software kernels. in at least one embodiment, one or more software kernels are performed based on one or more kernel dependencies.
Inventor(s): Mohamed Saad Gaber Abdelhameed of Dachau (DE) for nvidia corporation, Vito Magnanimo of Munchen (DE) for nvidia corporation
IPC Code(s): G06F11/00, B60W50/02
CPC Code(s): G06F11/008
Abstract: in various examples, confirming or evaluating availability requirements as part of a safety analysis for autonomous and semi-autonomous systems and applications is described herein. for instance, systems and methods are disclosed that may add availability requirements to one or more safety analysis techniques, such as failure mode and effects analysis (fmea), critical path analysis (cpa), and/or any other safety analysis technique. in some examples, an availability requirement may indicate whether a failure mode associated with a detected failure will impact an availability of an element and/or one or more measures that may be taken to avoid impacting the availability of the element. systems and methods may then analyze a machine using these updated safety analysis techniques to detect failure modes in a system, causes of the failure modes, and effects of the failure modes, as well as determine whether these failure modes will impact the availability of the system.
20250086090. VALUE PROFILING ON ACCELERATORS_simplified_abstract_(nvidia corporation)
Inventor(s): Durgadoss R of Bangalore (IN) for nvidia corporation, Hariharan Sandanagobalane of Remond WA (US) for nvidia corporation, Pradeep Kumar of Coimbatore (IN) for nvidia corporation, Khaled Abdul Karim Mohammed of Sacramento CA (US) for nvidia corporation, Vatsa Santhanam of Cupertino CA (US) for nvidia corporation
IPC Code(s): G06F11/34, G06F8/41
CPC Code(s): G06F11/3466
Abstract: apparatuses, systems, and techniques to perform variable value profiling. in at least one embodiment, variable value profiling is to be performed by one or more accelerators.
Inventor(s): Yunzhou Liu of Santa Clara CA (US) for nvidia corporation, Kyle Kranen of Santa Clara CA (US) for nvidia corporation, Mateusz Sieniawski of Warsaw (PL) for nvidia corporation, Mateusz Szczesny of Warsaw (PL) for nvidia corporation, Piotr Bigaj of Warsaw (PL) for nvidia corporation, Pawel Morkisz of Santa Clara CA (US) for nvidia corporation, Keval Morabia of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06N3/045
CPC Code(s): G06N3/045
Abstract: apparatuses, systems, and techniques to compare image generation quality of two or more image models. in at least one embodiment, a similarity metric that compares two or more images generated by the two or more image models from the same text description may be computed.
Inventor(s): Or LITANY of Sunnyvale CA (US) for nvidia corporation, Sanja FIDLER of Toronto (CA) for nvidia corporation, Cho-Ying WU of Los Angeles CA (US) for nvidia corporation, Huan LING of Toronto (CA) for nvidia corporation, Zan GOJCIC of Zurich (CH) for nvidia corporation, Riccardo DE LUTIO of Zurich (CH) for nvidia corporation, Sameh KHAMIS of Alameda CA (US) for nvidia corporation
IPC Code(s): G06T19/00, G06T7/194, G06V10/25, G06V10/44, G06V10/764, G06V10/82
CPC Code(s): G06T19/00
Abstract: in various examples, systems and methods are disclosed relating to neural networks for three-dimensional (3d) scene representations and modifying the 3d scene representations. in some implementations, a diffusion model can be configured to modify selected portions of 3d scenes represented using neural radiance fields, without painting back in content of the selected portions that was originally present. a first view of the neural radiance fields can be inpainted to remove a target feature from the first view, and used as guidance for updating the neural radiance field so that the target feature can be realistically removed from various second views of the neural radiance fields while context is retained outside of the selected portions.
Inventor(s): David Jesus Acuna Marrero of Toronto (CA) for nvidia corporation, Rafid Mahmood of Ottawa (CA) for nvidia corporation, James Robert Lucas of Royston (GB) for nvidia corporation, Yuan-Hong Liao of Toronto (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06V10/25, G06V10/82, G06V20/70
CPC Code(s): G06V10/25
Abstract: apparatuses, system, and techniques use one or more neural networks to generate a modified bounding box based, at least in part, on one or more second bounding boxes.
- NVIDIA Corporation
- B25J9/16
- CPC B25J9/163
- Nvidia corporation
- B60W60/00
- B60W30/095
- G06F9/50
- CPC B60W60/0015
- G06F9/38
- G06T1/20
- CPC G06F9/3838
- G06F11/00
- B60W50/02
- CPC G06F11/008
- G06F11/34
- G06F8/41
- CPC G06F11/3466
- G06N3/045
- CPC G06N3/045
- G06T19/00
- G06T7/194
- G06V10/25
- G06V10/44
- G06V10/764
- G06V10/82
- CPC G06T19/00
- G06V20/70
- CPC G06V10/25
