NVIDIA Corporation patent applications on December 5th, 2024
Patent Applications by NVIDIA Corporation on December 5th, 2024
NVIDIA Corporation: 21 patent applications
NVIDIA Corporation has applied for patents in the areas of B60W60/00 (5), H04L9/40 (3), G06V20/56 (2), G06T7/50 (1), G06V10/764 (1) B60W60/0011 (2), G06T15/08 (1), H04L63/1416 (1), H04L63/0884 (1), H04L63/0457 (1)
With keywords such as: data, memory, storage, based, various, maneuver, used, request, guest, and processing in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): David Nister of Bellevue WA (US) for nvidia corporation
IPC Code(s): B60W60/00, B60W50/00
CPC Code(s): B60W60/0011
Abstract: costs associated with configurations corresponding to a maneuver type(s) may be stored in a transition state(s) volume. the same memory volume may be used for storing cost values that correspond different maneuver types and different vertices in a graph of a configuration space. in at least one embodiment, to share a memory volume between maneuver types, the system may determine a cost for a machine to reach a configuration of a configuration space using various different maneuver types. the system may then evaluate one or more of the costs to determine which of the costs to store at one or more memory location(s) corresponding to the configuration (e.g., a point in a memory volume). cost values for the memory volume may be efficiently determined using kernel-style processing.
Inventor(s): David Nister of Bellevue WA (US) for nvidia corporation
IPC Code(s): B60W60/00
CPC Code(s): B60W60/0011
Abstract: path planning may be performed under non-holonomic constraints based at least on discretizing and selectively analyzing a solution space using a graph that includes vertices corresponding to machine configurations in a configuration space, along with associated maneuver types used by the machine to traverse these configurations. the graph may include transition edges associating costs with machine transitions between maneuver types and maneuvers. one or more of the vertices may correspond to a transition state between maneuver types. in some examples, a maneuver type may be used as a transition state between maneuver types to reduce the vertices and edges of the graph. the graph may incorporate vertices and edges representing optimal maneuver types for traversing the configuration space, including longitudinally extremal and/or laterally extremal maneuvers based on machine models.
Inventor(s): Sever Ioan TOPAN of San Francisco CA (US) for nvidia corporation, Yuxiao CHEN of Newark CA (US) for nvidia corporation, Edward FU SCHMERLING of Seattle WA (US) for nvidia corporation, Karen Yan Ming LEUNG of Seattle WA (US) for nvidia corporation, Hans Jonas NILSSON of Los Gatos CA (US) for nvidia corporation, Michael COX of Menlo Park CA (US) for nvidia corporation, Marco PAVONE of Stanford CA (US) for nvidia corporation
IPC Code(s): B60W60/00
CPC Code(s): B60W60/0015
Abstract: in various examples, systems and methods are disclosed relating to refinement of safety zones and improving evaluation metrics for the perception modules of autonomous and semi-autonomous systems. example implementations can exclude areas in the state space that are not safety critical, while retaining the areas that are safety-critical. this can be accomplished by leveraging ego maneuver information and conditioning safety zone computations on ego maneuvers. a maneuver-based decomposition of perception safety zones may leverage a temporal convolution operation with the capability to account for collision at any intermediate time along the way to maneuver completion. this provides a significant reduction in zone volume while maintaining completeness, thus optimizing or otherwise enhancing obstacle perception performance requirements by filtering out regions of state space not relevant to a system's route of travel. computation of safety-zones conditioned on the ego maneuver greatly reduces excessive conservatism.
Inventor(s): Alexander Korovko of Redmond WA (US) for nvidia corporation, Aigul Dzhumamuralova of Yerevan (AM) for nvidia corporation
IPC Code(s): G01C21/00, B60W60/00, G06V20/56
CPC Code(s): G01C21/3896
Abstract: in various examples, sensor fusion for visual-inertial odometry in autonomous and semi-autonomous systems and applications is described herein. systems and methods are disclosed that split processing into at least two components. for example, the first component may be configured to process incoming frames, execute one or more perspective-n-point techniques to determine states of a machine, update states associated with one or more inertial measurement unit sensors of the machine, and add new frames to a map. the second component may be configured to adjust states (e.g., poses) associated with the machine using one or more sparse bundle adjustment techniques, adjust points within an environment, and adjust imu-related parameters using a history of camera states. in some examples, the pnp technique and/or the sba technique may be selected based on states associated with the imu sensor(s).
20240402250. FAULT DETECTION IN PARALLEL HARDWARE_simplified_abstract_(nvidia corporation)
Inventor(s): Saurabh Hukerikar of Santa Clara CA (US) for nvidia corporation, Nirmal Saxena of Los Altos Hills CA (US) for nvidia corporation, Atieh Lotfi of San Jose CA (US) for nvidia corporation, Samuel H. Duncan of Arlington MA (US) for nvidia corporation, Yanxiang Huang of San Jose CA (US) for nvidia corporation, Jason Campbell of Lake Elmo MN (US) for nvidia corporation, Paul Racunas of Landaff NH (US) for nvidia corporation
IPC Code(s): G01R31/3187, G01R31/319
CPC Code(s): G01R31/3187
Abstract: in various examples, faults are detected based at least in part on result value(s) generated by hardware component(s) by performing one or more diagnostic tests in accordance with a diagnostic test pattern. the diagnostic test pattern may be used to perform an assessment of functionality of the hardware component(s) by causing the hardware component(s) to generate the result value(s), which may be used to identify one or more hardware faults (e.g., by comparing the result value(s) to expected value(s)).
20240402740. VOLTAGE REGULATOR DROOP REDUCTION MECHANISM_simplified_abstract_(nvidia corporation)
Inventor(s): Zhonghua Li of San Jose CA (US) for nvidia corporation, Wen-Hung Lo of Saratoga CA (US) for nvidia corporation, Michael Ivan Halfen of San Francisco CA (US) for nvidia corporation, Abhishek Dhir of Oakville (CA) for nvidia corporation, Jaewon Lee of San Jose CA (US) for nvidia corporation, Jiwang Lee of San Jose CA (US) for nvidia corporation, CHUNJEN SU of Zhubei City (TW) for nvidia corporation
IPC Code(s): G05F1/563, G05F1/565, G05F3/26
CPC Code(s): G05F1/563
Abstract: power supply circuits in which a supplemental current driver is utilized to boost the current provided by a voltage regulator. the supplementing driver detects operating conditions for providing the supplementary current, and may be trained to provide particular amounts of current in response to particular operation conditions of a circuit load.
Inventor(s): Kaushal AGARWAL of Bengaluru (IN) for nvidia corporation, Jonathon Stuart Ramsay EVANS of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06F9/30, G06F9/52
CPC Code(s): G06F9/30047
Abstract: various embodiments include techniques for launching processing work in a computing system. the disclosed techniques include load and store operations that specify a category. the disclosed techniques further include barrier instructions that specify a category. a processing unit of the computing system executes a set of load and store operations that specify various categories. when the processor subsequently executes a barrier instruction that specifies a category, the barrier instruction waits for data for only load and store operations that specify the same category. after the barrier instruction completes execution, the processing unit can launch processes that are dependent on data from load and store operations of the specified category, even if data from load and store operations of other categories is still pending. as a result, the processing unit can launch processes as soon as the relevant data is available without waiting for nonrelevant data.
20240403063. AUTOMATIC POPULATION OF BOOT VOLUMES_simplified_abstract_(nvidia corporation)
Inventor(s): David Dejong of Fremont CA (US) for nvidia corporation, Siamak Nazari of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/4408
Abstract: a storage system () includes a storage processor (-) such as a storage card resident in a host server (-) and coupled to the storage device (-). the storage processor (-) may be configured to create a virtual volume (-), store content derived from an image () downloaded from a url storage corresponding to the virtual volume (-), and present the virtual volume (-) to the host server as a boot lun. a management infrastructure () can be used to create a library () of images () corresponding to different storage system characteristics and used to selected which url is provided to the storage processor (-).
Inventor(s): Manikandan SUBRAMANIAN of Bangalore (IN) for nvidia corporation
IPC Code(s): G06F13/16
CPC Code(s): G06F13/1673
Abstract: various embodiments include techniques for managing pre-fetch data in a computing system. a memory controller receives pre-fetch operations from a pre-fetch generator associated with a processing unit. the pre-fetch operations identify data that is likely to be accessed by the processing unit in the near future. in response, the memory controller retrieves read data associated with the read operations from system memory and stores the read data in a pre-fetch buffer included in the memory controller. the memory controller further receives status data via a low-latency signal path. the status data indicates information about each read operation, such as if the read operation can be serviced by a cache memory and whether the read operation is delayed but is to be transmitted to the memory controller. in response, the memory controller purges data from or holds data in the pre-fetch buffer based on the status data.
Inventor(s): Aamer Jaleel of Northborough MA (US) for nvidia corporation, Gururaj Saileshwar of Seattle WA (US) for nvidia corporation
IPC Code(s): G06F21/55, G06F12/14
CPC Code(s): G06F21/554
Abstract: rowhammer attacks, which are malicious processes that rapidly issue access requests to memory, can impose serious security threats including being used to tamper data, take control of entire systems, and even breach confidentiality. current solutions to defend against these attacks are limited, as they typically employ a deterministic tracker to track the portions of memory accessed and to mitigate potential attacks accordingly. however, the deterministic nature of these trackers results in their own vulnerability. the present disclosure provides probabilistic tracker management for mitigation of rowhammer attacks and/or other memory attacks in which a row (or other defined portion of memory) is maliciously targeted to disturb contents of neighboring rows, which can prevent these types of attacks that otherwise take advantage of the determinism in prior used tracker designs.
Inventor(s): Christopher John NEWBURN of South Beloit IL (US) for nvidia corporation
IPC Code(s): G06F21/62, G06F21/54
CPC Code(s): G06F21/6218
Abstract: in various embodiments, a proxy application processes requests to access a storage system. the proxy application receives a client request from a proxy driver executing on a client node. the client request is associated with a client buffer and a location within the storage system. the proxy application converts the client request to a proxy request that is associated with a proxy buffer and the same location within the storage system. the proxy application transmits the proxy request to a storage driver that is associated with the storage system. the storage driver causes a file server to perform at least one operation at the location in accordance with the proxy request.
Inventor(s): Yilin Yang of Santa Clara CA (US) for nvidia corporation, Bala Siva Sashank Jujjavarapu of Sunnyvale CA (US) for nvidia corporation, Pekka Janis of Uusimaa (FI) for nvidia corporation, Zhaoting Ye of Santa Clara CA (US) for nvidia corporation, Sangmin Oh of San Jose CA (US) for nvidia corporation, Minwoo Park of Saratoga CA (US) for nvidia corporation, Daniel Herrera Castro of Uusimaa (FI) for nvidia corporation, Tommi Koivisto of Uusimaa (FI) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation
IPC Code(s): G06N3/08, B60W30/14, B60W60/00, G06F18/214, G06V10/762, G06V20/56
CPC Code(s): G06N3/08
Abstract: in various examples, a deep neural network (dnn) is trained to accurately predict, in deployment, distances to objects and obstacles using image data alone. the dnn may be trained with ground truth data that is generated and encoded using sensor data from any number of depth predicting sensors, such as, without limitation, radar sensors, lidar sensors, and/or sonar sensors. camera adaptation algorithms may be used in various embodiments to adapt the dnn for use with image data generated by cameras with varying parametersâsuch as varying fields of view. in some examples, a post-processing safety bounds operation may be executed on the predictions of the dnn to ensure that the predictions fall within a safety-permissible range.
20240404174. NEURAL HEAD AVATAR CONSTRUCTION FROM AN IMAGE_simplified_abstract_(nvidia corporation)
Inventor(s): Xueting Li of Sunnyvale CA (US) for nvidia corporation, Shalini De Mello of San Francisco CA (US) for nvidia corporation, Sifei Liu of Santa Clara CA (US) for nvidia corporation, Koki Nagano of Playa Vista CA (US) for nvidia corporation, Umar Iqbal of San Jose CA (US) for nvidia corporation, Jan Kautz of Lexington MA (US) for nvidia corporation
IPC Code(s): G06T15/08, G06T13/40, G06V10/774, G06V10/82, G06V10/94, G06V40/16
CPC Code(s): G06T15/08
Abstract: systems and methods are disclosed that animate a source portrait image with motion (i.e., pose and expression) from a target image. in contrast to conventional systems, given an unseen single-view portrait image, an implicit three-dimensional (3d) head avatar is constructed that not only captures photo-realistic details within and beyond the face region, but also is readily available for animation without requiring further optimization during inference. in an embodiment, three processing branches of a system produce three tri-planes representing coarse 3d geometry for the head avatar, detailed appearance of a source image, as well as the expression of a target image. by applying volumetric rendering to a combination of the three tri-planes, an image of the desired identity, expression and pose is generated.
Inventor(s): Andrew Russell of Weston FL (US) for nvidia corporation, Omer Shapira of Brooklyn NY (US) for nvidia corporation, Max Bickley of Oakland CA (US) for nvidia corporation, Konstantin Shkurko of Yardley PA (US) for nvidia corporation, Rev Lebaredian of Los Gatos CA (US) for nvidia corporation
IPC Code(s): G06T19/20, G06T7/70, G06T19/00
CPC Code(s): G06T19/20
Abstract: apparatuses, systems, and techniques providing a teleportation system combining virtual reality and augment reality are provided. a first set of data associated with a real-world environment is received. an object in the real-world environment, and a first location of the object, are identified based on a subset of the first set of data. a second location of a first user within the real-world environment is identified based on the first set of data. a second set of data representing a first avatar of a guest user is received. a virtual representation of the real-world environment is generated based on the first and second sets of data, comprising the object positioned at the first location and at least one of a second avatar of the first user or the first avatar of the guest user. the virtual representation is send to a computing system associated with the guest user.
Inventor(s): Shagan Sah of Santa Clara CA (US) for nvidia corporation, Niranjan Avadhanam of Saratoga CA (US) for nvidia corporation, Rajath Shetty of Sunnyvale CA (US) for nvidia corporation, Ratin Kumar of Cupertino CA (US) for nvidia corporation, Yile Chen of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06V20/58, G06T7/20, G06T7/50, G06V10/764, G06V20/59, G08B13/196
CPC Code(s): G06V20/58
Abstract: in various examples, low power proximity based threat detection using optical flow for vehicle systems and applications are provided. some embodiments may use a tiered framework that uses sensor fusion techniques to detect and track the movement of a threat candidate, and perform a threat classification and/or intent prediction as the threat candidate approaches approach. relative depth indications from optical flow, computed using data from image sensors, can be used to initially segment and track a moving object over a sequence of image frames. additional sensors and processing may be brought online when a moving object becomes close enough to be considered a higher risk threat candidate. a threat response system may generate a risk score based on a predicted intent of a threat candidate, and when the risk score exceeds a certain threshold, then the threat response system may respond accordingly based on the threat classification and/or risk score.
Inventor(s): Stefan P. Sywyk of San Jose CA (US) for nvidia corporation, Lalit Gupta of Santa Clara CA (US) for nvidia corporation, Jesse Wang of Santa Clara CA (US) for nvidia corporation
IPC Code(s): H03K19/0185, G06F30/36, G11C8/08, G11C8/10
CPC Code(s): H03K19/018521
Abstract: the disclosure introduces a level-shifter including a boost circuit that provides a âone-shotâ pulse (a self-annihilating pulse) with the transitioning edge of the output signal. the pulse can be used to produce a faster output rise time and reduce the overall footprint of a level-shifter compared to conventional level-shifters. in one example the level-shifter includes: (1) input circuitry configured to receive one or more input signals from one or more input voltage domains, (2) output circuitry configured to provide an output signal, based on at least one of the one or more input signals, for an output voltage domain, wherein an operating voltage of the output voltage domain is greater than an operating voltage of the one or more input voltage domains, and (3) a boost circuit connected to the output circuitry and configured to provide a current pulse for a transition edge of the output signal.
Inventor(s): Elad Alon of Tel Aviv (IL) for nvidia corporation, Eitan Zahavi of Zichron Yaacov (IL) for nvidia corporation, Gaby Diengott of Kadima (IL) for nvidia corporation, Shie Mannor of Haifa (IL) for nvidia corporation, Vadim Gechman of Hulda (IL) for nvidia corporation
IPC Code(s): H04L41/0659, H04L41/147, H04L43/06, H04L43/0811
CPC Code(s): H04L41/0659
Abstract: a network monitor may execute, or communicate with, one or more stored machine learning models that are trained to predict a failure probability for one or more ports and/or links within a network fabric. systems and methods may monitor a set of ports and/or links to generate predictions for failure probabilities using a first trained model and low frequency telemetry data. for a subset of ports and/or links with failure probabilities exceeding a first threshold, high speed telemetry data may be used by a second trained model to generate predictions for failure probabilities for the subset of ports. suspicious ports may then be isolated and undergo various remediation and/or monitoring actions prior to de-isolating the isolated ports.
20240406154. NATIVE LINK ENCRYPTION_simplified_abstract_(nvidia corporation)
Inventor(s): Miriam Menes of Tel Aviv (IL) for nvidia corporation, Naveen Cherukuri of San Jose CA (US) for nvidia corporation, Ahmad Atamli of Oxford (GB) for nvidia corporation, Uria Basher of Nehusha (IL) for nvidia corporation, Mike Osborn of Hollis NH (US) for nvidia corporation, Mark Hummel of Franklin MA (US) for nvidia corporation, Liron Mula of Hertzlia (IL) for nvidia corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/0457
Abstract: technologies for encrypting communication links between devices are described. a method includes generating a first initialization vector (iv), from a first subspace of ivs, for a first cryptographic ordered flow, and a second iv, from a second subspace of ivs that are mutually exclusive from the first subspace. the first and second cryptographic ordered flows share a key to secure multipath routing in a fabric between devices. the method sends, to the second device, a first packet for the first cryptographic ordered flow and a second packet for the second cryptographic ordered flow. the first packet includes a first security tag with the first iv and a first payload encrypted using the first iv and a first key. the second packet includes a second security tag with the second iv and a second payload encrypted using the second iv and a second key.
Inventor(s): Christopher John NEWBURN of South Beloit IL (US) for nvidia corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/0884
Abstract: in various embodiments, a filter application filtering requests to access a storage system. the filter application receives credential data from a scheduling server and a first request from a first compute node. the filter application determines that the first request is authorized based on a first user identifier associated with the first request, a first node identifier associated with at least one of the first compute node or the first request, and the credential data. the filter application causes a file server to perform at least one operation at a first location within the storage system in accordance with the first request.
20240406196. PROTECTING VEHICLE BUSES FROM CYBER-ATTACKS_simplified_abstract_(nvidia corporation)
Inventor(s): Mark Overby of Bothel WA (US) for nvidia corporation, Rick Dingle of Bleadon (GB) for nvidia corporation, Nicola Di Miscio of Ely (GB) for nvidia corporation, Varadharajan Kannan of Bristol (GB) for nvidia corporation, Yong Zhang of Hampshire (GB) for nvidia corporation, Francesco Saracino of Kenynsham (GB) for nvidia corporation
IPC Code(s): H04L9/40, G06F9/455, G06F13/40, G06F21/60, G06N20/00, H04L9/00, H04L9/32, H04L12/40, H04L47/24, H04L61/2585, H04L67/12
CPC Code(s): H04L63/1416
Abstract: various approaches are disclosed for protecting vehicle buses from cyber-attacks. disclosed approaches provide for an embedded system having a hypervisor that provides a virtualized environment supporting any number of guest oses. the virtualized environment may include a security engine on an internal communication channel between the guest os and an external vehicle bus of a vehicle to analyze network traffic to protect the guest os from other guest oses or other network components, and to protect those network components from the guest os. each guest os may have its own security engine customized for the guest os to account for what is typical or expected traffic for the guest os (e.g., using machine learning, anomaly detection, etc.). also disclosed are approaches for corrupting a message being transmitted on a vehicle bus to prevent devices from acting on the message
20240406405. FRAME SELECTION FOR STREAMING APPLICATIONS_simplified_abstract_(nvidia corporation)
Inventor(s): Aurobinda Maharana of Chinchwad (IN) for nvidia corporation, Vignesh Ungrapalli of Udupi (IN) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation
IPC Code(s): H04N19/137, H04N19/186, H04N19/513
CPC Code(s): H04N19/137
Abstract: systems and methods herein address reference frame selection in video streaming applications using one or more processing units to identify a frame of a sequence of frames as a blurred frame based at least in part on a first variance of motion (vom) of the frame being less than or equal to an adaptive threshold that is based in part on a moving average of variance of motion (maov) determined using one or more reference frames.
NVIDIA Corporation patent applications on December 5th, 2024
- NVIDIA Corporation
- B60W60/00
- B60W50/00
- CPC B60W60/0011
- Nvidia corporation
- CPC B60W60/0015
- G01C21/00
- G06V20/56
- CPC G01C21/3896
- G01R31/3187
- G01R31/319
- CPC G01R31/3187
- G05F1/563
- G05F1/565
- G05F3/26
- CPC G05F1/563
- G06F9/30
- G06F9/52
- CPC G06F9/30047
- G06F9/4401
- CPC G06F9/4408
- G06F13/16
- CPC G06F13/1673
- G06F21/55
- G06F12/14
- CPC G06F21/554
- G06F21/62
- G06F21/54
- CPC G06F21/6218
- G06N3/08
- B60W30/14
- G06F18/214
- G06V10/762
- CPC G06N3/08
- G06T15/08
- G06T13/40
- G06V10/774
- G06V10/82
- G06V10/94
- G06V40/16
- CPC G06T15/08
- G06T19/20
- G06T7/70
- G06T19/00
- CPC G06T19/20
- G06V20/58
- G06T7/20
- G06T7/50
- G06V10/764
- G06V20/59
- G08B13/196
- CPC G06V20/58
- H03K19/0185
- G06F30/36
- G11C8/08
- G11C8/10
- CPC H03K19/018521
- H04L41/0659
- H04L41/147
- H04L43/06
- H04L43/0811
- CPC H04L41/0659
- H04L9/40
- CPC H04L63/0457
- CPC H04L63/0884
- G06F9/455
- G06F13/40
- G06F21/60
- G06N20/00
- H04L9/00
- H04L9/32
- H04L12/40
- H04L47/24
- H04L61/2585
- H04L67/12
- CPC H04L63/1416
- H04N19/137
- H04N19/186
- H04N19/513
- CPC H04N19/137