NVIDIA Corporation patent applications on April 24th, 2025
Patent Applications by NVIDIA Corporation on April 24th, 2025
NVIDIA Corporation: 12 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T1/20 (3), G06V10/82 (3), G06V20/58 (2), G06V10/44 (2), G06V10/25 (2) G06F9/45558 (1), G06F30/23 (1), G06N3/08 (1), G06N3/084 (1), G06T1/60 (1)
With keywords such as: systems, points, clock, generate, based, processing, data, buffer, features, and neural in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Philip Nelson Elcan of Hillsborough NC US for nvidia corporation, Jason Sequeira of Fremont CA US for nvidia corporation, Daniel Jonathan Hettena of Princeton NJ US for nvidia corporation, William Joseph Armstrong of Rochester MN US for nvidia corporation, Aingara Paramakuru of Pickering CA for nvidia corporation, Thomas Fleury of Chapel Hill NC US for nvidia corporation
IPC Code(s): G06F9/455
CPC Code(s): G06F9/45558
Abstract: apparatuses, systems, and techniques for testing processing units of a computing system are disclosed herein. a request to initiate a testing process for each of a set of processing units is received. a first processing unit includes a first virtual processor executing first operations. a second processing unit includes a second virtual processor executing second operations. execution of the first operations is transferred from the first virtual processor to the second virtual processor. execution of the testing process is initiated at the first processing unit while the second virtual processor executes the first and second operations. in response to a detection that the execution of the testing process is completed, execution of the first and second operations is transferred to the first virtual processor. execution of the testing process is initiated at the second processing unit while the first virtual processor running executes the first and second operations.
20250131161. METHODS OF CONTACT FOR SIMULATION_simplified_abstract_(nvidia corporation)
Inventor(s): Miles Macklin of Auckland NZ for nvidia corporation, Matthias Mueller-Fischer of Uerikon CH for nvidia corporation, Nuttapong Chentanez of Bangkok TH for nvidia corporation, Stefan Jeschke of Vienna AT for nvidia corporation, Tae-Yong Kim of San Jose CA US for nvidia corporation
IPC Code(s): G06F30/23, G06F17/16, G06F30/27, G06F111/04, G06F113/12, G06N3/08, G06T1/20, G06T15/00, G06T15/06, G06T17/20
CPC Code(s): G06F30/23
Abstract: apparatuses, systems, and techniques apply to a force-based (e.g., primal) formulation for object simulation. in at least one embodiment, updates to the force-based formulation is determined by solving for constraints that are to be satisfied when simulating rigid bodies (e.g., contact rich scenarios).
Inventor(s): Richard Edward Harang of Alexandria VA US for nvidia corporation, Daniel Cory Rohrer of Cary NC US for nvidia corporation
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: systems and methods provide for a prompt template to include private random strings that are used by a language model to reference specific tokens on which the language model has been trained. a number of random strings may be generated and inserted into a prompt template and assigned special token identifiers (ids) in a tokenizer. the text data from the prompt template are tokenized to convert the random strings to the assigned special token ids which are sent to the language model for inferencing. based on the provided special token ids, the language model may reference special tokens learned from training and then generates an inference. the random strings remain hidden during their lifetime and may be updated on-demand to ensure security.
Inventor(s): Innfarn Yoo of Fremont CA US for nvidia corporation, Rohit Taneja of Fremont CA US for nvidia corporation
IPC Code(s): G06N3/084, G06N3/045, G06N20/00, G06T7/30, G06T7/50, G06T7/521, G06T15/00, G06V10/25, G06V10/44, G06V10/764, G06V10/80, G06V10/82, G06V20/58, G06V20/64
CPC Code(s): G06N3/084
Abstract: in various examples, a two-dimensional (2d) and three-dimensional (3d) deep neural network (dnn) is implemented to fuse 2d and 3d object detection results for classifying objects. for example, regions of interest (rois) and/or bounding shapes corresponding thereto may be determined using one or more region proposal networks (rpns)—such as an image-based rpn and/or a depth-based rpn. each roi may be extended into a frustum in 3d world-space, and a point cloud may be filtered to include only points from within the frustum. the remaining points may be voxelated to generate a volume in 3d world space, and the volume may be applied to a 3d dnn to generate one or more vectors. the one or more vectors, in addition to one or more additional vectors generated using a 2d dnn processing image data, may be applied to a classifier network to generate a classification for an object.
Inventor(s): David Kvasnica of Ontario CA for nvidia corporation, Adrian Jerod Wells of Snellville GA US for nvidia corporation, Jeremiah Gustaf Ingham of Milpitas CA US for nvidia corporation
IPC Code(s): G06T1/60, G06N3/084, G06T1/20
CPC Code(s): G06T1/60
Abstract: apparatuses, systems, and techniques for buffer identification of an application for post-processing. the apparatuses, systems, and techniques includes generating a buffer statistic data structure for a buffer of a plurality of buffers associated with a frame of an application; updating the buffer statistic data structure with metadata of the draw call responsive to detecting a draw call to the buffer, and determining, based on the buffer statistic data structure, a score reflecting a likelihood of the buffer being associated with a specified buffer type.
20250131596. DETERMINING OPTICAL CENTER IN AN IMAGE_simplified_abstract_(nvidia corporation)
Inventor(s): Hugh Phu Nguyen of Milpitas CA US for nvidia corporation, Paul Kalapathy of Ozark MO US for nvidia corporation
IPC Code(s): G06T7/80, H04N25/61
CPC Code(s): G06T7/80
Abstract: optical center is determined on a column-by-column and row-by-row basis by identifying brightest pixels in respective columns and rows. the brightest pixels in each column are identified and a line is fit to those pixels. similarly, brightest pixels in each row are identified and a second line is fit to those pixels. the intersection of the two lines is the optical center.
Inventor(s): Or Litany of Sunnyvale CA US for nvidia corporation, Sanja Fidler of Toronto CA for nvidia corporation, Huan Ling of Toronto CA for nvidia corporation, Chenfeng Xu of Emeryville CA US for nvidia corporation
IPC Code(s): G06V10/25, G06T3/18, G06T7/70, G06T11/00, G06V20/70
CPC Code(s): G06V10/25
Abstract: disclosed are systems and methods relating to extracting 3d features, such as bounding boxes. the systems can apply, to one or more features of a source image that depicts a scene using a first set of camera parameters, based on a condition view image associated with the source image, an epipolar geometric warping to determine a second set of camera parameters. the systems can generate, using a neural network, a synthetic image representing the one or more features and corresponding to the second set of camera parameters.
Inventor(s): Sanja FIDLER of Toronto CA US for nvidia corporation, Matan Atzmon of Toronto CA US for nvidia corporation, Jiahui Huang of Beijing CN for nvidia corporation, Or Litany of Haifa IL for nvidia corporation, Francis Williams of Brooklyn NY US for nvidia corporation
IPC Code(s): G06V10/44, G06V10/82
CPC Code(s): G06V10/44
Abstract: in various examples, a technique for modeling equivariance in point neural networks includes generating, via execution of one or more layers included in a neural network, a set of features associated with a first partition prediction for a plurality of points included in a scene. the technique also includes applying, to the set of features, one or more transformations included in a frame associated with the plurality of points to generate a set of equivariant features. the technique further includes generating a second partition prediction for the plurality of points based at least on the set of equivariant features, and causing an object recognition result associated with the plurality of points to be generated based at least on the second partition prediction.
Inventor(s): Sanja FIDLER of Toronto CA for nvidia corporation, Matan ATZMON of Toronto CA for nvidia corporation, Jiahui HUANG of Beijing CN for nvidia corporation, Or LITANY of Haifa IL for nvidia corporation, Francis WILLIAMS of Brooklyn NY US for nvidia corporation
IPC Code(s): G06V10/82, G06V10/26, G06V20/58
CPC Code(s): G06V10/82
Abstract: in various examples, a technique for modeling equivariance in point neural networks includes determining a first partition prediction associated with partitioning of a plurality of points included in a scene into a first set of parts. the technique also includes generating, using a neural network, a second partition prediction associated with partitioning of the plurality of points into a second set of parts based at least on one or more aggregations associated with the first set of parts. the technique further includes determining a plurality of piecewise equivariant regions included in the scene based on the second partition prediction and generating an object recognition result associated with the plurality of points based on the plurality of piecewise equivariant regions.
Inventor(s): Mahdi Azizian of San Jose CA US for nvidia corporation, Thomas Kierski of Durham NC US for nvidia corporation, Sean Huver of Mountain View CA US for nvidia corporation
IPC Code(s): G16H30/40, G06T3/06, G06T7/00, G06T11/00
CPC Code(s): G16H30/40
Abstract: apparatuses, systems, and techniques are presented to generate ultrasound images. in at least one embodiment, use one or more neural networks are used to generate one or more ultrasound images of one or more objects based, at least in part, upon one or more acoustic properties of the one or more objects.
Inventor(s): Andrea Miele of San Jose CA US for nvidia corporation
IPC Code(s): H03M13/09, G06F9/50, G06T1/20, H04L1/00
CPC Code(s): H03M13/09
Abstract: apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (gpu) to compute cyclic redundancy checks. for example, in at least one embodiment, an input data sequence is distributed among gpu threads for parallel calculation of an overall crc value for the input data sequence according to various novel techniques described herein.
20250132892. ADAPTIVE CLOCK GENERATION FOR SERIAL LINKS_simplified_abstract_(nvidia corporation)
Inventor(s): Brian Matthew Zimmer of Sunnyvale CA US for nvidia corporation
IPC Code(s): H04L7/00, H04L7/033
CPC Code(s): H04L7/0091
Abstract: adaptive clock mechanisms for serial links utilizing a delay-chain-based edge generation circuit to generate a clock that is a faster (higher-frequency) version of an incoming digital clock. the base frequency of the link clock utilized by the line transmitters is determined by the (slower) clock utilized by the digital circuitry supplying data to the line transmitters. an edge generator that may be composed of only non-synchronous circuit elements multiplies the edges of the slower clock to generate the link clock and also a clock forwarded to the receiver at a phase offset from the link clock.
- NVIDIA Corporation
- G06F9/455
- CPC G06F9/45558
- Nvidia corporation
- G06F30/23
- G06F17/16
- G06F30/27
- G06F111/04
- G06F113/12
- G06N3/08
- G06T1/20
- G06T15/00
- G06T15/06
- G06T17/20
- CPC G06F30/23
- CPC G06N3/08
- G06N3/084
- G06N3/045
- G06N20/00
- G06T7/30
- G06T7/50
- G06T7/521
- G06V10/25
- G06V10/44
- G06V10/764
- G06V10/80
- G06V10/82
- G06V20/58
- G06V20/64
- CPC G06N3/084
- G06T1/60
- CPC G06T1/60
- G06T7/80
- H04N25/61
- CPC G06T7/80
- G06T3/18
- G06T7/70
- G06T11/00
- G06V20/70
- CPC G06V10/25
- CPC G06V10/44
- G06V10/26
- CPC G06V10/82
- G16H30/40
- G06T3/06
- G06T7/00
- CPC G16H30/40
- H03M13/09
- G06F9/50
- H04L1/00
- CPC H03M13/09
- H04L7/00
- H04L7/033
- CPC H04L7/0091