NVIDIA Corporation patent applications on April 17th, 2025
Patent Applications by NVIDIA Corporation on April 17th, 2025
NVIDIA Corporation: 21 patent applications
NVIDIA Corporation has applied for patents in the areas of H04N19/174 (2), G06V10/82 (2), G06F12/0811 (2), B60W50/12 (1), H04L9/08 (1) B60W50/12 (1), G06V40/107 (1), H04N21/44245 (1), H04N21/440236 (1), H04N19/70 (1)
With keywords such as: data, frame, video, network, based, information, circuit, systems, sensor, and packets in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Niranjan Avadhanam of Saratoga CA US for nvidia corporation, Yuzhuo Ren of Sunnyvale CA US for nvidia corporation
IPC Code(s): B60W50/12, B60W40/08, B60W50/14, G06V10/82, G06V20/59, G06V40/18, G06V40/60
CPC Code(s): B60W50/12
Abstract: approaches presented herein provide for the automated determination of a level of impairment of a person, as may be relevant to the performance of a task. a light and camera-based system can be used to determine factors such as gaze nystagmus that are indicative of inebriation or impairment. a test system can simulate motion of a light using a determined pattern, and capture image data of at least the eye region of a person attempting to follow the motion. the captured image data can be analyzed using a neural network to infer at least one behavior of the user, and the behavior determination(s) can be used to determine a capacity or level of impairment of a user. an appropriate action can be taken, such as to allow a person with full capacity to operate a vehicle or perform a task, or to block access to such operation or performance if the person is determined to be impaired beyond an allowable amount.
Inventor(s): Georgios Kalogerakis of Pleasanton CA US for nvidia corporation
IPC Code(s): G01J1/44, H03F3/45
CPC Code(s): G01J1/44
Abstract: an integrated circuit is disclosed. the integrated circuit comprises an input interface and an optical receiver. the optical receiver includes a photodiode, level shifter, and differential transimpedance amplifier (tia). the photodiode has a cathode and anode terminal and is configured to receive an optical signal via the input interface. the level shifter includes a parallel rc circuit. the differential tia has first and second conversion circuits. the first conversion circuit is connected to the cathode terminal and a first output terminal of the optical receiver. the second conversion circuit is connected between the anode terminal and a second output terminal of the optical receiver. the parallel rc circuit is connected between the cathode terminal of the photodiode and the first conversion circuit. the differential tia is configured to provide a differential voltage signal at the first and second output terminals of the optical receiver based on the optical signal.
Inventor(s): Padmanabham Patki of Fremont CA US for nvidia corporation, Jue Wu of Los Gatos CA US for nvidia corporation, Andrew Elias of Ottawa CA for nvidia corporation, Smbat Tonoyan of Los Gatos CA US for nvidia corporation
IPC Code(s): G01R31/3185, G01R31/317
CPC Code(s): G01R31/318536
Abstract: a scan island for automated data retrieval from an integrated circuit (ic) includes a data extraction module configured to extract data from multiple scan chains and random-access memory (ram) modules in response to a trigger event, storing the data in an external non-volatile storage medium. the scan island further comprises a clock and reset module, which includes a free-running independent clock to enable continuous operation of the scan island upon occurrence of the trigger event, and a local reset module that re-initializes the scan island in a known state following the trigger event without external intervention. the scan island operates as an isolated partition within the ic, ensuring secure and autonomous data retrieval and recovery processes.
Inventor(s): Hans Jonas Nilsson of Los Gatos CA US for nvidia corporation, Michael Cox of Menlo Park CA US for nvidia corporation, Sangmin Oh of San Jose CA US for nvidia corporation, Joachim Pehserl of Lynnwood WA US for nvidia corporation, Aidin Ehsanibenafati of Santa Clara CA US for nvidia corporation
IPC Code(s): G05B13/02, G01S13/86, G06V10/80, G06V10/82
CPC Code(s): G05B13/027
Abstract: in various examples, systems and methods are disclosed that perform sensor fusion using rule-based and learned processing methods to take advantage of the accuracy of learned approaches and the decomposition benefits of rule-based approaches for satisfying higher levels of safety requirements. for example, in-parallel and/or in-serial combinations of early rule-based sensor fusion, late rule-based sensor fusion, early learned sensor fusion, or late learned sensor fusion may be used to solve various safety goals associated with various required safety levels at a high level of accuracy and precision. in embodiments, learned sensor fusion may be used to make more conservative decisions than the rule-based sensor fusion (as determined using, e.g., severity (s), exposure (e), and controllability (c) (sec) associated with a current safety goal), but the rule-based sensor fusion may be relied upon where the learned sensor fusion decision may be less conservative than the corresponding rule-based sensor fusion.
Inventor(s): Yoni Yosef-Hay of Lyngby DK for nvidia corporation, Xiaodong Liu of Lund SE for nvidia corporation
IPC Code(s): G05F3/24, G05F1/46
CPC Code(s): G05F3/245
Abstract: a reference generation circuit includes a proportional-to-absolute temperature (ptat) current branch having a pair of diodes and a complementary-to-absolute temperature (ctat) current branch having a pair of resistors. a first bank of diode-connected transistors is positioned in the ptat branch and a second bank of diode-connected transistors is positioned in the ctat branch. diode-connected transistors of the first and second banks of transistors are selectable to tune a gate-source voltage of each of the first and second banks of diode-connected transistors.
Inventor(s): Sana Damani of Santa Clara CA US for nvidia corporation, Peter Nelson of San Francisco CA US for nvidia corporation
IPC Code(s): G06F9/52, G06T1/20, G06T1/60
CPC Code(s): G06F9/52
Abstract: a process to ameliorate scoreboard aliasing in multi-threaded data processors whereby, in response to executing at least one long-latency instruction in a first thread, a shared hardware scoreboard is incremented. a shared software register is incremented and the shared software register is spilled to a first per-thread register, and execution is switched to a second thread. after execution switches back to the first thread, execution of the first thread is suspended until the shared hardware scoreboard reaches a value at or below a difference between a value in the shared software register and the value spilled into the first per-thread register.
Inventor(s): Harold Carter Edwards of Campbell CA US for nvidia corporation, Daniel Joseph Lustig of Woburn MA US for nvidia corporation, Gonzalo Brito Gadeschi of Munich DE for nvidia corporation, Subhasmita Chakraborty of Los Altos CA US for nvidia corporation, Gokul Ramaswamy Hirisave Chandra Shekhara of Bangalore IN for nvidia corporation
IPC Code(s): G06F12/0811, G06F12/0804
CPC Code(s): G06F12/0811
Abstract: apparatuses, systems, and techniques to prevent information from being read from a second cache location while information is being stored in a first cache location. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to prevent information from being read from a second cache location while information is being stored in a first cache location.
Inventor(s): Harold Carter Edwards of Campbell CA US for nvidia corporation, Daniel Joseph Lustig of Woburn MA US for nvidia corporation, Gonzalo Brito Gadeschi of Munich DE for nvidia corporation, Subhasmita Chakraborty of Los Altos CA US for nvidia corporation, Gokul Ramaswamy Hirisave Chandra Shekhara of Bangalore IN for nvidia corporation
IPC Code(s): G06F12/0891, G06F12/0811
CPC Code(s): G06F12/0891
Abstract: apparatuses, systems, and techniques to cause information to be invalidated in a second cache location after information is stored in a first cache location. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause information to be invalidated in a second cache location after information is stored in a first cache location.
20250123992. COMBINATIONAL LOGIC-BASED SERIALIZER_simplified_abstract_(nvidia corporation)
Inventor(s): Ramses Pierco of Gent BE for nvidia corporation, Timothy De Keulenaer of Gent BE for nvidia corporation
IPC Code(s): G06F13/42, G06F1/04
CPC Code(s): G06F13/4282
Abstract: an integrated circuit includes logic circuitry configured to output serialized data from a plurality of precoded data inputs without use of a clock signal. the integrated circuit further includes a precoder circuit responsive to the clock signal to generate the plurality of precoded data inputs based on timing of data symbols positioned within a plurality of data inputs.
20250124640. TRAINING DATA SAMPLING FOR NEURAL NETWORKS_simplified_abstract_(nvidia corporation)
Inventor(s): Jonathan Peter Lorraine of Toronto CA for nvidia corporation, Cheng (Kevin) Xie of Toronto CA for nvidia corporation, Xiaohui Zeng of Toronto CA for nvidia corporation, Jun Gao of Toronto CA for nvidia corporation, Sanja Fidler of Toronto CA for nvidia corporation, James Lucas of Toronto CA for nvidia corporation
IPC Code(s): G06T15/00, G06T7/00
CPC Code(s): G06T15/005
Abstract: apparatuses, systems, and techniques to train one or more neural networks using stratified sampled training data parameters. in at least one embodiment, one or more stochastic training data parameters may be stratified sampled from one or more sampling ranges to compute a gradient for updating the one or more neural networks.
Inventor(s): Bowen WEN of Bellevue WA US for nvidia corporation, Stanley BIRCHFIELD of Sammamish WA US for nvidia corporation, Jonathan TREMBLAY of Redmond WA US for nvidia corporation, Valts BLUKIS of Seattle WA US for nvidia corporation, Dieter FOX of Seattle WA US for nvidia corporation, Yijia WENG of Palo Alto CA US for nvidia corporation
IPC Code(s): G06T17/20, B25J9/16, G06T7/11, G06T7/20, G06T19/00
CPC Code(s): G06T17/20
Abstract: one embodiment of a method for generating an articulation model includes receiving a first set of images of an object in a first articulation and a second set of images of the object in a second articulation, performing one or more operations to generate first three-dimensional (3d) geometry based on the first set of images, performing one or more operations to generate second 3d geometry based on the second set of images, and performing one or more operations to generate an articulation model of the object based on the first 3d geometry and the second 3d geometry.
Inventor(s): Sakthivel Sivaraman of Sunnyvale CA US for nvidia corporation, Nishant Puri of San Francisco CA US for nvidia corporation, Yuzhuo Ren of Sunnyvale CA US for nvidia corporation, Atousa Torabi of San Jose CA US for nvidia corporation, Shubhadeep Das of Kolkata IN for nvidia corporation, Niranjan Avadhanam of Saratoga CA US for nvidia corporation, Sumit Kumar Bhattacharya of Pune IN for nvidia corporation, Jason Roche of Santa Clara CA US for nvidia corporation
IPC Code(s): G06V40/10, G06F3/01, G06F16/632, G06T7/73, G06T15/06
CPC Code(s): G06V40/107
Abstract: interactions with virtual systems may be difficult when users inadvertently fail to provide sufficient information to proceed with their requests. certain types of inputs, such as auditory inputs, may lack sufficient information to properly provide a response to the user. additional information, such as image data, may enable user gestures or poses to supplement the auditory inputs to enable response generation without requesting additional information from users.
Inventor(s): Rudolf H. J. BLOKS of Campbell CA US for nvidia corporation, Arun Kumar SWAIN of Morgan Hill CA US for nvidia corporation
IPC Code(s): G09G3/00, B60Q9/00, G06F9/455, G09G5/00, G09G5/14
CPC Code(s): G09G3/006
Abstract: in various examples, a technique for end-to-end telltale verification for automotive systems and applications includes receiving, from a buffer, a set of commands associated with a frame to be displayed on a screen. the technique also includes determining, based at least on the set of commands, (i) an expected checksum for a telltale to be included in the frame and (ii) at least a portion of the frame associated with the telltale. the technique further includes computing a checksum for the at least the portion of the frame, and causing an alert associated with the telltale to be generated based at least on a comparison of the computed checksum with the expected checksum.
Inventor(s): Rangharajan Venkatesan of San Jose CA US for nvidia corporation, Reena Elangovan of Milpitas CA US for nvidia corporation, Brucek Kurdo Khailany of Austin TX US for nvidia corporation, Brian Matthew Zimmer of Sunnyvale CA US for nvidia corporation
IPC Code(s): H03M13/09, H03M13/00
CPC Code(s): H03M13/091
Abstract: vector-scaled hierarchical codebook quantization reduces precision (bitwidth) vectors of parameters and may enable energy-efficient acceleration of deep neural networks. a vector (block array) comprises one or more parameters within a single dimension of a multi-dimensional tensor (or kernel). for example, block array comprises 4 sub-vectors (blocks) and each sub-vector comprises 8 parameters. the parameters may be represented in integer, floating-point, or any other suitable format. a vector cluster quantization technique is used to quantize blocks of parameters in real-time. hardware circuitry within a datapath identifies an optimal codebook of a plurality of codebooks for quantizing each block of parameters and the block is encoded using the identified codebook. during processing, the identified codebook is used to obtain the quantized parameter and perform computations at the reduced precision.
Inventor(s): Rudolf H. J. BLOKS of Campbell CA US for nvidia corporation, Arun Kumar SWAIN of Morgan Hill CA US for nvidia corporation
IPC Code(s): H04L1/00
CPC Code(s): H04L1/0083
Abstract: in various examples, a technique for end-to-end camera view verification for automotive systems and applications includes computing a checksum for at least a portion of a frame to be displayed on a screen, wherein the frame comprises one or more views captured using one or more cameras. the technique also includes receiving a sequence of checksums associated with one or more previous frames displayed on the screen. the technique further includes updating one or more counters based on one or more comparisons of the computed checksum and the sequence of checksums and causing an alert associated with display of the frame on the screen to be generated based on the one or more counters.
Inventor(s): Ofek Abadi of Nahariya IL for nvidia corporation, Ido Yatzkar of Mishmarmot IL for nvidia corporation
IPC Code(s): H04L5/14, H04L7/04
CPC Code(s): H04L5/1461
Abstract: a system includes first transceivers coupled to data lanes, which are coupled to second transceivers and a first encoder coupled to the first transceivers. the first encoder, responsive to detecting a transmission signal to begin a transmission mode, determines that first bits to be transmitted by the first transceivers over the data lanes include over fifty percent of a first binary value. the first encoder generates a first data-bus-inversion (dbi) polarity signal that alternates in polarity and generates first dbi-encoded bits of the first of bits based on the first dbi polarity signal. the first encoder causes the transmission signal to be transmitted to a second encoder coupled to the second transceivers, the transmission signal to synchronize dbi encoding between the first and second encoders.
20250125953. SYSTEM FOR ACCESS CONTROL_simplified_abstract_(nvidia corporation)
Inventor(s): Stephen David GLASER of San Francisco CA US for nvidia corporation, Eric TYSON of Santa Clara CA US for nvidia corporation, Jonathon EVANS of Santa Clara CA US for nvidia corporation
IPC Code(s): H04L9/08, H04L9/32
CPC Code(s): H04L9/0866
Abstract: systems, computer program products, and methods are described for an endpoint device configured for secure data transmission within a network. an example endpoint device may include a network interface configured to receive a communication request from a peer endpoint device, and an access control unit configured to determine whether a peer endpoint device is ide qualified based on the communication request. if the peer endpoint device is ide qualified, the access control unit authorizes the communication request, allowing secure communication between the devices. if the peer endpoint device is not ide qualified, the access control unit transmits the communication request to a root port for further authorization, verifying that only ide-qualified devices are permitted to communicate directly.
Inventor(s): Johannes Zimmermann of Berlin DE for nvidia corporation, Andrija Bosnjakovic of Redmond WA US for nvidia corporation, Viktor Vandanov of San Jose CA US for nvidia corporation
IPC Code(s): H04N19/70, H04L65/65, H04L69/16, H04N19/174
CPC Code(s): H04N19/70
Abstract: in various examples, systems and methods are disclosed relating to error concealment by replacing a lost video frame region with a chronological predecessor. network packets including data corresponding to an encoded bitstream of a frame of a video stream can be received. in response to determining that at least one packet of the video stream has been lost, a region of the video frame corresponding to the lost network packet can be replaced with the same region of a previous frame of the video stream.
Inventor(s): Johannes Zimmermann of Berlin DE for nvidia corporation, Andrija Bosnjakovic of Redmond WA US for nvidia corporation, Harsh Maniar of Sunnyvale CA US for nvidia corporation
IPC Code(s): H04N21/4402
CPC Code(s): H04N21/440236
Abstract: in various examples, systems and methods are disclosed relating to improving perceived video quality through temporal redistribution of network packet payloads that may carry error mitigation data. a subset of network packets for an encoded video stream is identified from a sequence of network packets as corresponding to a region of a video frame of the encoded video stream. a transmission order for the sequence of network packets is determined based at least on the subset of network packets and one or more error correction packets corresponding to the sequence of network packets. the sequence of network packets is transmitted to a receiver client device according to the transmission order.
Inventor(s): Johannes Zimmermann of Berlin DE for nvidia corporation, Andrija Bosnjakovic of Redmond WA US for nvidia corporation
IPC Code(s): H04N21/442, H04N19/136, H04N19/146, H04N19/172, H04N19/174, H04N19/65, H04N21/462, H04N21/6437
CPC Code(s): H04N21/44245
Abstract: in various examples, systems and methods are disclosed relating to bandwidth preservation through selective application of error mitigation techniques for video frame regions. a subset of network packets for a video stream are identified as corresponding to an encoded region of a video frame of the video stream. at least one error correction packet is transmitted for the subset that encodes the region of the video frame. the network packets and the at least one error correction packet can be transmitted to a receiver device.
Inventor(s): Nitin Mahesh Gode of Pune IN US for nvidia corporation, Ashish Anand of Gorakhpur IN US for nvidia corporation, Ambrish Dantrey of Pune IN US for nvidia corporation, Murali Krishna Kamisetty of Pune IN US for nvidia corporation
IPC Code(s): H04S7/00, G06V40/16
CPC Code(s): H04S7/303
Abstract: disclosed are apparatuses, systems, and techniques that provide virtual immersion sound experience and spatialization effects with an audio device supporting a low number of sound channels, according to at least one embodiment. the techniques include but are not limited to associating input audio channels of an audio stream with virtual speakers, identifying, using an optical sensor, positioning of a user's head relative to the virtual speakers, determining simulated sound intensities at one or more reference locations associated with the user's head, and generating, based on the simulated sound intensities, output audio signals configured for physical speakers.
- NVIDIA Corporation
- B60W50/12
- B60W40/08
- B60W50/14
- G06V10/82
- G06V20/59
- G06V40/18
- G06V40/60
- CPC B60W50/12
- Nvidia corporation
- G01J1/44
- H03F3/45
- CPC G01J1/44
- G01R31/3185
- G01R31/317
- CPC G01R31/318536
- G05B13/02
- G01S13/86
- G06V10/80
- CPC G05B13/027
- G05F3/24
- G05F1/46
- CPC G05F3/245
- G06F9/52
- G06T1/20
- G06T1/60
- CPC G06F9/52
- G06F12/0811
- G06F12/0804
- CPC G06F12/0811
- G06F12/0891
- CPC G06F12/0891
- G06F13/42
- G06F1/04
- CPC G06F13/4282
- G06T15/00
- G06T7/00
- CPC G06T15/005
- G06T17/20
- B25J9/16
- G06T7/11
- G06T7/20
- G06T19/00
- CPC G06T17/20
- G06V40/10
- G06F3/01
- G06F16/632
- G06T7/73
- G06T15/06
- CPC G06V40/107
- G09G3/00
- B60Q9/00
- G06F9/455
- G09G5/00
- G09G5/14
- CPC G09G3/006
- H03M13/09
- H03M13/00
- CPC H03M13/091
- H04L1/00
- CPC H04L1/0083
- H04L5/14
- H04L7/04
- CPC H04L5/1461
- H04L9/08
- H04L9/32
- CPC H04L9/0866
- H04N19/70
- H04L65/65
- H04L69/16
- H04N19/174
- CPC H04N19/70
- H04N21/4402
- CPC H04N21/440236
- H04N21/442
- H04N19/136
- H04N19/146
- H04N19/172
- H04N19/65
- H04N21/462
- H04N21/6437
- CPC H04N21/44245
- H04S7/00
- G06V40/16
- CPC H04S7/303