NVIDIA Corporation patent applications on April 10th, 2025
Patent Applications by NVIDIA Corporation on April 10th, 2025
NVIDIA Corporation: 19 patent applications
NVIDIA Corporation has applied for patents in the areas of G06T3/40 (2), G06V10/25 (2), G06F21/60 (2), G06V20/59 (2), G06V10/82 (2) G06T11/001 (2), G01C21/3811 (1), G06T19/20 (1), H05K7/20836 (1), H04L63/0485 (1)
With keywords such as: data, image, systems, fluid, traffic, device, rgb, input, neural, and map in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Shyh-Chyuan Huang of Arcadia CA US for nvidia corporation
IPC Code(s): G01C21/00
CPC Code(s): G01C21/3811
Abstract: in various examples, associating traffic objects with traffic poles or other supporting structures in maps for autonomous systems and applications is described herein. systems and methods are disclosed that associate traffic objects (e.g., traffic signals, traffic signs, etc.) with traffic poles within maps and/or generate structures that represent the associations within the maps. for instance, a map may indicate poses of one or more traffic objects and/or a traffic pole within an environment. as such, the poses may be used to associate the traffic object(s) with the traffic pole, such as by using one or more threshold distances. next, the poses, the association(s), and/or general information associated with traffic poles may be used to generate a structure that represents the traffic object(s) connected to the traffic pole.
Inventor(s): Thomas E. DEWEY of Menlo Park CA US for nvidia corporation, Michael IRWIN of Menlo Park CA US for nvidia corporation, Simon LAI of Mountain View CA US for nvidia corporation, Sau Yan Keith LI of San Jose CA US for nvidia corporation
IPC Code(s): G06F1/26
CPC Code(s): G06F1/3234
Abstract: a computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.
Inventor(s): Eric COLTER of Rockford MI US for nvidia corporation, Arun SHAMANNA LAKSHMI of San Jose CA US for nvidia corporation, Gordon Grigor of San Francsico CA US for nvidia corporation
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4881
Abstract: embodiments of the present disclosure relate to a system and method used to schedule and initiate execution of one or more tasks. the system may include processing units that may perform operations that may include obtaining execution information that may correspond to a first task and a second task. in some embodiments, the first task may include first operations and where the second task may include second operations. in some embodiments, the operations may further include determining a time to initialize execution of the first task and the second task based at least on the execution information. in some embodiments, execution of the first task may be executed on a first computing system and the second task may be executed on a second computing system where the execution of the first operations and the second operations is interdependent.
Inventor(s): Philip John Rogers of Austin TX US for nvidia corporation, Mark Overby of Snohomish WA US for nvidia corporation, Michael Asbury Woodmansee of Lighthouse Point FL US for nvidia corporation, Vyas Venkataraman of Sharon MA US for nvidia corporation, Naveen Cherukuri of San Jose CA US for nvidia corporation, Gobikrishna Dhanuskodi of Santa Clara CA US for nvidia corporation, Dwayne Frank Swoboda of San Jose CA US for nvidia corporation, Lucien Burton Dunning of Ramsey NJ US for nvidia corporation, Mark Hairgrove of San Jose CA US for nvidia corporation, Sudeshna Guha of Bangalore IN for nvidia corporation
IPC Code(s): G06F21/53, G06F9/455, G06F21/10, G06F21/54, G06F21/60, G06F21/79
CPC Code(s): G06F21/53
Abstract: apparatuses, systems, and techniques to generate a trusted execution environment including multiple accelerators. in at least one embodiment, a parallel processing unit (ppu), such as a graphics processing unit (gpu), operates in a secure execution mode including a protect memory region. furthermore, in an embodiment, a cryptographic key is utilized to protect data during transmission between the accelerators.
20250117584. PARALLEL PROCESSING OF HIERARCHICAL TEXT_simplified_abstract_(nvidia corporation)
Inventor(s): Elias Stehle of Pfäffikon CH for nvidia corporation, Gregory Michael Kimball of San Jose CA US for nvidia corporation
IPC Code(s): G06F16/2455, G06F16/22, G06F16/28
CPC Code(s): G06F40/284
Abstract: apparatuses, systems, and techniques to parse textual data using parallel computing devices. in at least one embodiment, text is parsed by a plurality of parallel processing units using a finite state machine and logical stack to convert the text to a tree data structure. data is extracted from the tree by the plurality of parallel processors and stored.
20250117625. CIRCUIT PREDICTION USING NEURAL NETWORKS_simplified_abstract_(nvidia corporation)
Inventor(s): Jialin Song of Pasadena CA US for nvidia corporation, Aidan Swope of Santa Clara CA US for nvidia corporation, Robert Kirby of Chicago IL US for nvidia corporation, Rajarshi Roy of San Jose CA US for nvidia corporation, Saad Godil of Milpitas CA US for nvidia corporation, Jonathan Raiman of Seattle WA US for nvidia corporation, Bryan Christopher Catanzaro of Los Altos Hills CA US for nvidia corporation
IPC Code(s): G06N3/0455, G06N3/084
CPC Code(s): G06N3/0455
Abstract: apparatuses, systems, and techniques to perform neural networks. in at least one embodiment, one or more neural networks are used to predict one or more characteristics of one or more first circuits based, at least in part, on one or more characteristics of one or more second circuits.
Inventor(s): Donald Lee BRITTAIN of Pasadena CA US for nvidia corporation, Andrew Ian RUSSELL of Weston FL US for nvidia corporation, Anjul PATNEY of Kirkland WA US for nvidia corporation, Yinghao XU of San Jose CA US for nvidia corporation, Shaveen KUMAR of Vancouver CA for nvidia corporation
IPC Code(s): G06T5/00, G06T3/40, G06T5/20, G06T7/00, G06T7/60, G06T7/70
CPC Code(s): G06T5/90
Abstract: in various examples, disclosed techniques use a banding detector neural network to identify the locations and sizes of banding artifacts in pixel regions of an input image. the neural network generates a band size map that identifies at least one banding artifact in the input image. the band size map can include a set of predicted band size values, each of which corresponds to a respective pixel of the input image and represents a distance between edges of a banding artifact. the band size map and the input image are provided as input to a stochastic bilateral blur filter, which generates a de-banded image by applying blurring effects to the input image at the band locations indicated by the band size map. an inverse tone mapping operation is then performed to convert the de-banded image to an image that does not have banding artifacts.
Inventor(s): Yuzhuo REN of Sunnyvale CA US for nvidia corporation, Niranjan AVADHANAM of Saratoga CA US for nvidia corporation
IPC Code(s): G06T11/00, G06V10/77, G06V10/774, G06V10/82, G06V20/59
CPC Code(s): G06T11/001
Abstract: in various examples, infrared image data (e.g., frames of an infrared video feed) may be colorized by applying the infrared image data and/or a corresponding edge map to a generator of a generative adversarial network (gan). the gan may be trained with or without paired ground truth rgb and infrared (and/or edge map) images. in an example of the latter scenario, a first generator g(ir)→rgb and a second generator g(rgb)→ir may be trained in a first chain, their positions may be swapped in a second chain, and the second chain may be trained. in some embodiments, edges may be emphasized by weighting edge pixels (e.g., determined from a corresponding edge map) higher than non-edge pixels when backpropagating loss. after training, g(ir)→rgb may be used to generate rgb image data from infrared image data (and/or a corresponding edge map).
Inventor(s): Yuzhuo REN of Sunnyvale CA US for nvidia corporation, Niranjan AVADHANAM of Saratoga CA US for nvidia corporation
IPC Code(s): G06T11/00, G06V10/77, G06V10/774, G06V10/82, G06V20/59
CPC Code(s): G06T11/001
Abstract: in various examples, infrared image data (e.g., frames of an infrared (ir) video feed) may be colorized by transferring color statistics from an rgb image with an overlapping field of view, by modifying one or more dimensions of an encoded representation of a generated rgb image, and/or otherwise. for example, segmentation may be applied to the ir and rgb image data, and the one or more colors or statistics may be transferred from a segmented region of the rgb image data to a corresponding segmented region of the ir image data. in some embodiments, synthesized rgb image data may be fined tuned by transferring color or color statistic(s) from corresponding real rgb image data, and/or by modifying one or more dimensions of an encoded representation of the synthesized rgb image data.
Inventor(s): Jithin Thomas of Pune IN for nvidia corporation, Shashikant Radhuji Jadhav of Pune IN for nvidia corporation
IPC Code(s): G06T11/60, G06T3/40, G06V10/25, G06V10/44
CPC Code(s): G06T11/60
Abstract: approaches presented herein provide systems and methods for identifying and removing overlay elements from one or more frames in a video sequence. a frame may be evaluated to identify one or more overlay elements and a mask may be generated, or acquired, to identify one or more regions of the frame associated with the one or more overlay elements. the initial frame and mask may be used as an input to one or more neural networks to remove the overlay elements and replace the overlay elements with generated content associated with an underlying scene in the frame. a reconstructed frame may then be generated and inserted into the video sequence, replacing the frame, for view on a display.
Inventor(s): Greg MUTHLER of Chapel Hill NC US for nvidia corporation, Tero Karras of Uusimaa FI for nvidia corporation, Samuli Laine of Uusimaa FI for nvidia corporation, William Parsons Newhall, JR. of Woodside CA US for nvidia corporation, Ronald Charles Babich, JR. of Murrysville PA US for nvidia corporation, John Burgess of Austin TX US for nvidia corporation, Ignacio Llamas of Palo Alto CA US for nvidia corporation
IPC Code(s): G06T15/06
CPC Code(s): G06T15/06
Abstract: a hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. the primitives may include opaque and alpha triangles used in generating a virtual scene. the hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. the hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. the omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
Inventor(s): Yeongho Seol of Seoul KR for nvidia corporation
IPC Code(s): G06T19/20, G06T7/70, G06T13/40, G06V10/25, G06V40/16
CPC Code(s): G06T19/20
Abstract: in various examples, landmark identification and retargeting for ai systems and applications is described herein. systems and methods are disclosed that use a first three-dimensional (3d) face (e.g., a morphable model mesh) that is already associated with locations of facial landmarks to determine locations of corresponding facial landmarks on a second 3d face (e.g., a target face mesh). to determine the locations, one or more iterations of transformation processes and/or fitting processes may be performed on the first 3d face in order to morph the landmarks of the first 3d face to align with second landmarks on the second 3d face. after performing the iteration(s) of the transformation processes and/or the fitting processes, closest locations (e.g., vertices) on the second 3d face from the landmark locations (e.g., vertices) on the first 3d face are identified and used as the locations of the corresponding facial landmarks on the second 3d face.
Inventor(s): Sina Mohseni of College Station TX US for nvidia corporation, Arash Vahdat of Mountain View CA US for nvidia corporation, Jay Yadawa of San Jose CA US for nvidia corporation
IPC Code(s): G06V20/56, G06F18/211, G06F18/2415, G06F18/2431, G06N3/045, G06N3/08
CPC Code(s): G06V20/56
Abstract: apparatuses, systems, and techniques to identify out-of-distribution input data in one or more neural networks. in at least one embodiment, a technique includes training one or more neural networks to infer a plurality of characteristics about input information based, at least in part, on the one or more neural networks being independently trained to infer each of the plurality of characteristics about the input information.
Inventor(s): Rohan Badlani of San Jose CA US for nvidia corporation, José Rafael Valle Gomves da Costa of Santa Clara CA US for nvidia corporation, Kevin Jonathan Shih of Cambridge CA US for nvidia corporation, Bryan Catanzaro of Los Altos Hills CA US for nvidia corporation
IPC Code(s): G10L13/047, G10L13/08, G10L13/10, G10L17/02, G10L25/18
CPC Code(s): G10L13/047
Abstract: in various examples, synthesizing speech in multiple languages in conversational ai systems and applications is described herein. systems and methods are disclosed that use one or more models to synthesize speech from a first language spoken by a speaker to a second, target language selected by the speaker. in some examples, to perform the translation, the model(s) may disentangle one or more attributes associated with speech from speakers, such as speakers' identities, speakers' accents, and text associated with the speech. additionally, the model(s) may allow for fine-grained control of additional attributes associated with output speech, such as one or more frequencies, one or more energies, and one or more phoneme durations. furthermore, the model(s) may be configured to use the accent associated with the target language when generating text, such as when aligning text encodings with one or more phonemes.
Inventor(s): Xingqin Lin of San Jose CA US for nvidia corporation
IPC Code(s): H04B17/391, H04B17/318, H04B17/336, H04W24/10
CPC Code(s): H04B17/3913
Abstract: apparatuses, systems, and techniques to use one or more neural networks to cause a prediction of a quality of one or more wireless signals to be transmitted, wherein the prediction is based, at least in part, on one or more reference signals. in at least one embodiment, a measurement report is to be generated by one or more neural networks.
Inventor(s): Stephen Aaron WOLFE of San Jose CA US for nvidia corporation, Mihir JOSHI of Santa Clara CA US for nvidia corporation, Tao YE of Santa Clara CA US for nvidia corporation, Mustafa Yigit BILGEN of Brookline MA US for nvidia corporation, Hyung Taek RYOO of Pleasanton CA US for nvidia corporation, Arun GONA of Bothell WA US for nvidia corporation, Santosh KATVATE of Pune IN for nvidia corporation
IPC Code(s): H04L9/32, G06F21/60
CPC Code(s): H04L9/3213
Abstract: in various examples, a technique for verifying data integrity is disclosed that includes receiving a request to access a data block of a plurality of data blocks stored in a non-secure memory. the technique further includes identifying, in a secure memory, an authentication token associated with the data block. the technique also includes generating an updated authentication token based on the data block. the technique further includes determining whether the updated authentication token corresponds to the identified authentication token stored in the secure memory. the technique still further includes in response to determining that the updated authentication token corresponds to the identified authentication token stored in the secure memory, performing one or more operations using the data block.
20250119413. SYSTEM FOR SECURE DATA TRANSMISSION_simplified_abstract_(nvidia corporation)
Inventor(s): Stephen David GLASER of San Francisco CA US for nvidia corporation, Jonathon EVANS of Santa Clara CA US for nvidia corporation, Vidhya KRISHNAN of Folsom CA US for nvidia corporation, Naveen Kumar NARRISHETTI of Bengaluru IN for nvidia corporation, Peter PANEAH of Nesher IL for nvidia corporation, Vladimir VAINER of Kiryat Shmona IL for nvidia corporation, Ariel SHAHAR of Jerusalem IL for nvidia corporation, Ofir EVEN CHEN of Kfar Saba IL for nvidia corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/0485
Abstract: systems, computer program products, and methods are described for secure data transmission. an example system includes a first end-point device, an intermediate device, and a second-end point device. the first end-point device determines the format requirements of the communication link between the first end-point device and the intermediate device, and the communication link intermediate device and the second end-point device. based on the format requirements, the first end-point device configures the data packet for transmission, such that the data packet, when received at the intermediate device, is re-configured and routed to the second end-point device. when the second end-point device receives the data packet, it verifies the data packet to confirm that the packet has maintained its integrity throughout transit.
Inventor(s): Ryan Albright of Beaverton OR US for nvidia corporation, Tahir Cader of Spokane Valley WA US for nvidia corporation, Aaron Carkin of Hillsboro OR US for nvidia corporation, Siddha Ganju of San Jose CA US for nvidia corporation, Kenneth Misin of Campbell CA US for nvidia corporation, William Mecham of Elk Grove CA US for nvidia corporation, William Ryan Weese of Portland OR US for nvidia corporation, Benjamin Goska of Portland OR US for nvidia corporation, Jordan Levy of Portland OR US for nvidia corporation, Michael Thompson of Wilsonville OR US for nvidia corporation, Elad Mentovich of Tel Aviv IL for nvidia corporation, Fred Devoir of Pilot Point TX US for nvidia corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20836
Abstract: devices, apparatuses, and systems for thermal management in networking and computing systems are provided. an example in-rack thermal management system includes a cooling distribution unit (cdu) that includes a housing that defines a fluid inlet and a fluid outlet, thermal management components supported by the housing, and direct mechanical connections coupled with the fluid inlet and the fluid outlet. the in-rack thermal management system includes a fluid distribution system that includes a primary fluid channel directly coupled with the direct mechanical connection of the fluid inlet, and a secondary fluid channel directly coupled with the direct mechanical connection of the fluid outlet. in operation, the thermal management components dissipate heat of a fluid received by the cdu via the fluid inlet. the direct mechanical connections directly interface with the fluid distribution system to provide fluid communication between the cdu and the fluid distribution system to maximize dimensions of the housing.
Inventor(s): Shai Cohen of Tel Aviv IL for nvidia corporation, Liron Gantz of Tel Aviv IL for nvidia corporation, Itamar Priel of Tel Aviv IL for nvidia corporation
IPC Code(s): H01L31/0352, G02B6/12, G02B6/122, H01L31/0232, H01L31/028
CPC Code(s): H10F77/147
Abstract: to improve an optical signal to electrical signal of a photodiode (pd) which is part of an integrated circuit, the pd can be modified to reduce noise and improve the gain bandwidth. in some aspects, the absorption region of the pd can utilize a non-rectangular geometry, for example, a clipped tapered geometry which can absorb the optical signal in more linearly than a rectangular geometry. in some aspects, the input optical signal can be split into two or more split optical signals, where each split optical signal is directed toward a different portion of the absorption region. the incident power of the optical signal transmitted to each respective portion of the absorption region can be reduced by dividing the incident power by the number of split optical signals thereby improving the gain and bandwidth saturation of each portion of the absorption region.
- NVIDIA Corporation
- G01C21/00
- CPC G01C21/3811
- Nvidia corporation
- G06F1/26
- CPC G06F1/3234
- G06F9/48
- CPC G06F9/4881
- G06F21/53
- G06F9/455
- G06F21/10
- G06F21/54
- G06F21/60
- G06F21/79
- CPC G06F21/53
- G06F16/2455
- G06F16/22
- G06F16/28
- CPC G06F40/284
- G06N3/0455
- G06N3/084
- CPC G06N3/0455
- G06T5/00
- G06T3/40
- G06T5/20
- G06T7/00
- G06T7/60
- G06T7/70
- CPC G06T5/90
- G06T11/00
- G06V10/77
- G06V10/774
- G06V10/82
- G06V20/59
- CPC G06T11/001
- G06T11/60
- G06V10/25
- G06V10/44
- CPC G06T11/60
- G06T15/06
- CPC G06T15/06
- G06T19/20
- G06T13/40
- G06V40/16
- CPC G06T19/20
- G06V20/56
- G06F18/211
- G06F18/2415
- G06F18/2431
- G06N3/045
- G06N3/08
- CPC G06V20/56
- G10L13/047
- G10L13/08
- G10L13/10
- G10L17/02
- G10L25/18
- CPC G10L13/047
- H04B17/391
- H04B17/318
- H04B17/336
- H04W24/10
- CPC H04B17/3913
- H04L9/32
- CPC H04L9/3213
- H04L9/40
- CPC H04L63/0485
- H05K7/20
- CPC H05K7/20836
- H01L31/0352
- G02B6/12
- G02B6/122
- H01L31/0232
- H01L31/028
- CPC H10F77/147
