NANYA TECHNOLOGY CORPORATION patent applications on April 17th, 2025
Patent Applications by NANYA TECHNOLOGY CORPORATION on April 17th, 2025
NANYA TECHNOLOGY CORPORATION: 17 patent applications
NANYA TECHNOLOGY CORPORATION has applied for patents in the areas of H01L21/768 (3), G11C11/4076 (3), H01L23/525 (2), H01L29/16 (2), H01L21/321 (2) H01L21/76816 (2), G11C11/4096 (2), H01L23/5256 (2), G03F7/70633 (1), G06F11/263 (1)
With keywords such as: layer, signal, semiconductor, disposed, structure, substrate, stage, device, configured, and gate in patent application abstracts.
Patent Applications by NANYA TECHNOLOGY CORPORATION
Inventor(s): CHENG-WEI WANG of TAOYUAN CITY TW for nanya technology corporation
IPC Code(s): G03F7/00, G01B11/25, G03F7/20, H01L23/544
CPC Code(s): G03F7/70633
Abstract: the present disclosure provides a semiconductor structure and a system for manufacturing the semiconductor structure. the system includes a fabrication equipment, configured to perform operations to form a layer on a wafer; an exposure equipment, configured to perform patterning operations to form a pattern of the layer; and an alignment equipment, configured to detect an alignment of two overlay marks at different elevations on the wafer. the alignment equipment includes a stage, configured to support the wafer; an optical device, configured to emit a radiation to excite a photoluminescent material of one of the two overlay marks; an optical filter, configured to receive and filter a radiation emitted from the photoluminescent material; and an optical detector, configured to convert an optical signal filtered by the optical filter to an electrical signal.
Inventor(s): Jui-Chung HSU of Taoyuan City TW for nanya technology corporation, Wei Chuan CHEN of Taipei City TW for nanya technology corporation, Wan-Chun FANG of Taoyuan City TW for nanya technology corporation
IPC Code(s): G06F11/263
CPC Code(s): G06F11/263
Abstract: a system including memory devices and a tester is provided. the tester is configured to: generate a first multi-purpose command to the memory devices and a first data signal to each of a first group in the memory devices to store a first identity; generate a second multi-purpose command to the memory devices and the first data signal to each of a second group in the memory devices to store a second identity; generate a third multi-purpose command and a fourth multi-purpose command to the memory devices to select the first and second groups in the memory devices to have first and second time shifts in write leveling pulses therein separately; transmit a write datum to the memory devices for performing a write operation to the memory devices; and receive read data and compare the write datum and the read data for a test result.
20250124967. MEMORY SYSTEM AND RECEIVER_simplified_abstract_(nanya technology corporation)
Inventor(s): Wu-Der YANG of Taoyuan City TW for nanya technology corporation
IPC Code(s): G11C11/4076, G11C11/4093, H03K19/20
CPC Code(s): G11C11/4076
Abstract: a memory system includes a controller and a memory circuit. controller outputs a first data strobe signal and a second data strobe signal. memory circuit is coupled to controller, and is configured to receive first data strobe signal and second data strobe signal. memory circuit includes a receiver. receiver includes a logic conversion circuit. logic conversion circuit is coupled to controller. when first and second data strobe signal are at the same voltage level, logic conversion circuit is configured to convert first second data strobe signals into third and fourth data strobe signals. third data strobe signal and fourth data strobe signal converted by logic conversion circuit are at different voltage levels. when first and second data strobe signals are at different voltage levels, logic conversion circuit is configured to pass first and second data strobe signal and as third and fourth data strobe signals.
Inventor(s): WU-DER YANG of TAOYUAN CITY TW for nanya technology corporation
IPC Code(s): G11C11/4096, G11C11/4076
CPC Code(s): G11C11/4096
Abstract: a control unit in a memory and a method of controlling a memory are provided. the control unit includes a first input stage, a second input stage, a first output stage, and a second output stage. the first input stage is configured to receive a first signal and a second signal. the second input stage is configured to receive the first signal and the second signal. the first output stage is connected to the first input stage and configured to generate a first processed signal. the second output stage is connected to the second input stage and configured to generate a second processed signal. if the first signal and the second signal are identical, the first processed signal and the second processed signal are different.
Inventor(s): WU-DER YANG of TAOYUAN CITY TW for nanya technology corporation
IPC Code(s): G11C11/4096, G11C11/4076
CPC Code(s): G11C11/4096
Abstract: a control unit in a memory and a method of controlling a memory are provided. the control unit includes a first input stage, a second input stage, a first output stage, and a second output stage. the first input stage is configured to receive a first signal and a second signal. the second input stage is configured to receive the first signal and the second signal. the first output stage is connected to the first input stage and configured to generate a first processed signal. the second output stage is connected to the second input stage and configured to generate a second processed signal. if the first signal and the second signal are identical, the first processed signal and the second processed signal are different.
Inventor(s): Yubon CHIANG of Kaohsiung City TW for nanya technology corporation
IPC Code(s): H01L21/02, H01L21/768
CPC Code(s): H01L21/02263
Abstract: a method of manufacturing a semiconductor device includes providing a bit line structure on a substrate, and the bit line structure is located between a pair of spacers containing air gaps. the method further includes depositing a silicon nitride film to seal the air gaps. depositing the silicon nitride film includes providing gases from a showerhead into a process chamber. the showerhead and a wafer on a carrier have a first distance therebetween. depositing the silicon nitride film further includes purging the process chamber, and lifting up the showerhead such that the first distance is increased to a second distance greater than the first distance.
Inventor(s): Chao Yuan CHENG of Taipei City TW for nanya technology corporation, Chan Hen YANG of Taipei City TW for nanya technology corporation
IPC Code(s): H01L21/027, H01L21/033, H01L21/311, H01L21/762
CPC Code(s): H01L21/0274
Abstract: a method of forming a line pattern in a semiconductor device includes forming a first photoresist layer having a first trench over a substrate, filling a first material in the first trench, forming a second photoresist layer having a second trench over the first photoresist layer, filling a second material in the second trench, and after filling the second material in the second trench, removing the first photoresist layer and the second photoresist layer.
Inventor(s): KUO-HUI SU of TAIPEI CITY TW for nanya technology corporation
IPC Code(s): H01L21/768, H01L21/3205, H01L21/321, H01L29/16
CPC Code(s): H01L21/76816
Abstract: the present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. the semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. a second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.
Inventor(s): KUO-HUI SU of TAIPEI CITY TW for nanya technology corporation
IPC Code(s): H01L21/768, H01L21/3205, H01L21/321, H01L29/16
CPC Code(s): H01L21/76816
Abstract: the present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. the semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-sparse region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. a second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.
Inventor(s): WEI-ZHONG LI of TAOYUAN CITY TW for nanya technology corporation, HSIH-YANG CHIU of TAOYUAN CITY TW for nanya technology corporation
IPC Code(s): H01L23/525, H01L23/528, H10D62/13, H10D64/23, H10D64/27, H10D84/01, H10D84/03, H10D84/83
CPC Code(s): H01L23/5256
Abstract: the present disclosure provides a method of manufacturing semiconductor structure. the method includes providing a substrate, including an active area and an isolation surrounding the active area; forming a trench fuse in the active area; forming a gate structure of a transistor over the substrate adjacent to the trench fuse; and forming a doping region surrounding the trench fuse and the gate structure; wherein a distance between the isolation and the trench fuse is less than a distance between the isolation and the gate structure.
Inventor(s): HSIH-YANG CHIU of TAOYUAN CITY TW for nanya technology corporation
IPC Code(s): H01L23/525, H01H69/02, H01H85/02
CPC Code(s): H01L23/5256
Abstract: a method for fabricating a semiconductor device is provided. the method includes providing a substrate; forming a fuse element within the substrate and extending from an upper surface of the substrate; and forming a fuse medium in contact with the fuse element, wherein the fuse medium is spaced apart from the upper surface of the substrate.
Inventor(s): WU-DER YANG of TAOYUAN CITY TW for nanya technology corporation
IPC Code(s): H01L23/00, H01L21/56
CPC Code(s): H01L24/85
Abstract: the present disclosure provides a method of manufacturing a semiconductor device. the method includes providing a substrate. the method also includes attaching an electronic component to the substrate. the method further includes attaching a fixing feature to an upper surface of the electronic component. in addition, the method includes forming a bonding wire connecting the substrate and the electronic component. the bonding wire is at least partially disposed on the fixing feature.
Inventor(s): Ying-Cheng CHUANG of Taoyuan City TW for nanya technology corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/488
Abstract: embodiments of this disclosure provide a method of manufacturing a semiconductor structure, and the method includes the following steps. a substrate with a first barrier layer in an array area and a second barrier layer in the peripheral area is provided. the substrate is etched toward to form recesses in the peripheral area to make a bottom surface of each of the recesses lower than a bottom surface of the second barrier layer. gate structures are formed in the recesses, respectively. moreover, a semiconductor structure is also disclosed this disclosure.
Inventor(s): TSE-YAO HUANG of TAIPEI CITY TW for nanya technology corporation
IPC Code(s): H10D1/68
CPC Code(s): H10D1/692
Abstract: a semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. the bottom electrode structure includes a first bottom electrode layer, and a second bottom electrode layer surrounding the first bottom electrode layer. the semiconductor device also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second first bottom electrode layer. the semiconductor device further includes a top electrode disposed over and surrounded by the bottom electrode structure. the top electrode has a ring shape from a top view. in addition, the semiconductor device includes an insulating layer separating the top electrode from the bottom electrode structure.
Inventor(s): Yu-Ping Chen of New Taipei City TW for nanya technology corporation, Chen-Lun Ting of Taipei City TW for nanya technology corporation
IPC Code(s): H01L29/78, H01L29/66
CPC Code(s): H10D30/601
Abstract: provided are a semiconductor device and a manufacturing method thereof. the semiconductor device includes a gate structure disposed on a substrate, source and drain regions, and first and second doped regions. the gate structure includes a gate disposed on the substrate, a gate dielectric layer disposed between the gate and the substrate, and a spacer disposed on sidewalls of the gate and the gate dielectric layer. the source and drain regions are disposed in the substrate and at two sides of the gate structure respectively. the first doped region is disposed in the substrate and adjacent to the source region. the second doped region is disposed in the substrate and located under the first doped region. the conductive type of the second doped region is opposite to that of the source region, the drain region and the first doped region.
Inventor(s): Ying-Cheng CHUANG of Taoyuan City TW for nanya technology corporation
IPC Code(s): H01L29/40, H01L29/423
CPC Code(s): H10D64/01
Abstract: a method of forming a semiconductor structure includes the following operations. a trench is formed in a substrate. a dielectric layer is formed to cover an inner surface of the trench. a bottom conductive layer is deposited on the dielectric layer and in the trench at a first temperature of 350� c. to 450� c. an annealing process is performed on the bottom conductive layer at a second temperature greater than or equal to 470� c. a portion of the bottom conductive layer is removed to form a recess on the bottom conductive layer and in the trench. a top conductive layer is formed in the recess.
Inventor(s): JHEN-YU TSAI of KAOHSIUNG CITY TW for nanya technology corporation
IPC Code(s): H10D64/27, H10D62/10, H10D64/01
CPC Code(s): H10D64/513
Abstract: a semiconductor device and a method of manufacturing a semiconductor device are provided. the semiconductor device includes a substrate having a trench and a gate structure in the trench. the trench includes a lower gate electrode, an upper gate electrode over the lower gate electrode and a first dielectric layer partially disposed between the lower gate electrode and the upper gate electrode.
NANYA TECHNOLOGY CORPORATION patent applications on April 17th, 2025
- NANYA TECHNOLOGY CORPORATION
- G03F7/00
- G01B11/25
- G03F7/20
- H01L23/544
- CPC G03F7/70633
- Nanya technology corporation
- G06F11/263
- CPC G06F11/263
- G11C11/4076
- G11C11/4093
- H03K19/20
- CPC G11C11/4076
- G11C11/4096
- CPC G11C11/4096
- H01L21/02
- H01L21/768
- CPC H01L21/02263
- H01L21/027
- H01L21/033
- H01L21/311
- H01L21/762
- CPC H01L21/0274
- H01L21/3205
- H01L21/321
- H01L29/16
- CPC H01L21/76816
- H01L23/525
- H01L23/528
- H10D62/13
- H10D64/23
- H10D64/27
- H10D84/01
- H10D84/03
- H10D84/83
- CPC H01L23/5256
- H01H69/02
- H01H85/02
- H01L23/00
- H01L21/56
- CPC H01L24/85
- H10B12/00
- CPC H10B12/488
- H10D1/68
- CPC H10D1/692
- H01L29/78
- H01L29/66
- CPC H10D30/601
- H01L29/40
- H01L29/423
- CPC H10D64/01
- H10D62/10
- H10D64/01
- CPC H10D64/513
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