Low Leakage FET

Organization Name

murata manufacturing co., ltd.

Inventor(s)

Abhijeet Paul of Poway CA (US)

Simon Edward Willard of Irvine CA (US)

Alain Duvallet of San Diego CA (US)

Low Leakage FET

This abstract first appeared for US patent application 20250072062 titled 'Low Leakage FET

Original Abstract Submitted

fet designs that exhibit low leakage in the presence of the edge transistor phenomenon. embodiments includes nfet designs in which the work function �of the gate structure overlying the edge transistors of the nfet is increased by forming extra p+ implant regions within at least a portion of the gate structure, thereby increasing the vt of the edge transistors to a level that may exceed the vt of the central conduction channel of the nfet. in some embodiments, the gate structure of the nfet is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the fet. other methods of changing the work function �of the gate structure overlying the edge transistors are also disclosed. the methods may be adapted to fabricating pfets by reversing or substituting material types.