Low Leakage Replacement Metal Gate FET

Organization Name

Inventor(s)

Low Leakage Replacement Metal Gate FET - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240313081 titled 'Low Leakage Replacement Metal Gate FET

Simplified Explanation: The patent application describes FET designs, specifically NMOSFET designs based on SOI fabrication technology, that have low leakage in the presence of the edge transistor phenomenon. This is achieved by increasing the threshold voltage of the edge FETs to match or exceed the threshold voltage of the central conduction channel FET using a unique dual work function configuration of a high dielectric constant (high-k) replacement metal gate (RMG) structure.

Key Features and Innovation:

FET designs with low leakage in the presence of the edge transistor phenomenon
NMOSFET designs based on SOI fabrication technology
Increased threshold voltage of edge FETs using a dual work function configuration of a high-k RMG structure

Potential Applications:

Semiconductor industry for high-performance integrated circuits
Mobile devices for improved power efficiency
IoT devices for enhanced battery life

Problems Solved:

Leakage in FET designs due to the edge transistor phenomenon
Mismatch in threshold voltages of edge FETs and central conduction channel FETs

Benefits:

Improved performance and reliability of FET designs
Enhanced power efficiency in electronic devices
Extended battery life in portable electronics

Commercial Applications: Potential commercial applications include:

Semiconductor manufacturing companies
Mobile device manufacturers
IoT device makers

Prior Art: Readers can start their search for prior art related to this technology by looking into patents and research papers on SOI fabrication technology, NMOSFET designs, and high-k RMG structures in FETs.

Frequently Updated Research: Stay updated on the latest advancements in SOI fabrication technology, NMOSFET designs, and high-k RMG structures to further enhance FET performance and efficiency.

Questions about FET Designs with Low Leakage: 1. What are the key advantages of using a high-k RMG structure in FET designs? 2. How does increasing the threshold voltage of edge FETs improve overall FET performance?

Original Abstract Submitted

fet designs, and in particular nmosfet designs based on soi fabrication technology, that exhibit low leakage in the presence of the edge transistor phenomenon. embodiments include fets in which the threshold voltage vof the edge fets is increased to a level that is at least equal to the threshold voltage vof the central conduction channel fet using a novel dual work function configuration of a high dielectric constant (high-�) replacement metal gate (rmg) structure. one embodiment encompasses a fet including an rmg structure overlying a doped silicon region, the rmg structure including: an interface insulator formed over the doped silicon region; a high-� material formed over the interface insulator; an n-type work function material overlaying and in contact with a central portion of the high-� material; and a p-type work function material overlaying and in contact with at least one edge portion of the high-� material.