DETECTING AND MITIGATING MEMORY ATTACKS

Organization Name

microsoft technology licensing, llc

Inventor(s)

Ishwar Agarwal of Redmond WA (US)

Stefan Saroiu of Redmond WA (US)

Alastair Wolman of Seattle WA (US)

Daniel Sebastian Berger of Seattle WA (US)

DETECTING AND MITIGATING MEMORY ATTACKS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240112723 titled 'DETECTING AND MITIGATING MEMORY ATTACKS

Simplified Explanation

The present disclosure describes systems and methods implemented on a memory controller for detecting and mitigating memory attacks, such as row hammer attacks. The memory controller can switch between counting mode and sampling mode to track activation counts for memory sub-banks and memory rows, respectively, in order to prevent potential attacks.

Memory controller tracks activation counts for memory sub-banks and memory rows to detect potential row hammer attacks.
Controller switches between counting mode and sampling mode based on certain conditions to mitigate attacks.
By transitioning between modes, the memory controller reduces vulnerability periods to attacks.

Potential Applications

This technology can be applied in various computing systems where memory security is crucial, such as servers, data centers, and personal computers.

Problems Solved

This technology addresses the issue of memory attacks, specifically row hammer attacks, by actively detecting and mitigating them in real-time.

Benefits

- Enhanced memory security - Real-time detection and mitigation of memory attacks - Reduced vulnerability periods to attacks

Potential Commercial Applications

The technology can be utilized in the cybersecurity industry to enhance memory security in a wide range of computing devices.

Possible Prior Art

Prior art related to memory controllers and memory attack mitigation techniques may exist, but specific examples are not provided in this disclosure.

Unanswered Questions

How does the memory controller determine the conditions for transitioning between counting mode and sampling mode?

The disclosure does not provide detailed information on the specific conditions that trigger the transition between the different operating modes.

What impact does the transition between modes have on the overall performance of the memory controller?

The disclosure does not elaborate on how the switching between counting mode and sampling mode affects the efficiency and speed of the memory controller.

Original Abstract Submitted

the present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). for example, a memory controller may engage a counting mode in which activation counts for memory sub-banks are tracked. for example, a memory controller may engage a counting mode in which activation counts for memory rows of memory sub-banks are maintained. under certain conditions, the memory controller may transition from the counting mode to a sampling mode to mitigate potential row hammer attacks. the memory controller may consider various conditions in determining whether to continue detecting and mitigating potential row hammer attacks in the sampling mode and/or transitioning back to the counting mode. by selectively transitioning between the different operating modes, the memory controller may reduce periods of time when the memory hardware is vulnerable to attacks.