Microsoft Technology Licensing, LLC patent applications on February 20th, 2025
Patent Applications by Microsoft Technology Licensing, LLC on February 20th, 2025
Microsoft Technology Licensing, LLC: 27 patent applications
Microsoft Technology Licensing, LLC has applied for patents in the areas of H05K7/20 (5), G06F40/284 (2), G06F40/30 (2), G06F21/55 (2), G06N10/70 (2) A63F11/00 (1), G06N10/70 (1), H05K7/2039 (1), H05K7/20272 (1), H05K1/0203 (1)
With keywords such as: data, device, cooling, circuit, structure, computing, based, temperature, security, and graph in patent application abstracts.
Patent Applications by Microsoft Technology Licensing, LLC
20250058211. ELECTRONIC DEVICE WRAP_simplified_abstract_(microsoft technology licensing, llc)
Inventor(s): Christopher Hays KUJAWSKI of Bellevue WA (US) for microsoft technology licensing, llc, Monique CHATTERJEE of Seattle WA (US) for microsoft technology licensing, llc, Paul Ryan SANDOVAL of Kirkland WA (US) for microsoft technology licensing, llc, Stacy N. POLLEN of Seattle WA (US) for microsoft technology licensing, llc, Corrie June GREENING of Seattle WA (US) for microsoft technology licensing, llc, Aaron David THOMPSON of Seattle WA (US) for microsoft technology licensing, llc
IPC Code(s): A63F11/00
CPC Code(s): A63F11/00
Abstract: a device may include a first rigid panel having a contact surface and a cosmetic surface. a device may include a frictious material positioned on the contact surface of the first rigid panel. a device may include a second rigid panel having a contact surface and a cosmetic surface, the second rigid panel movably connected to the first rigid panel by a hinged connector. a device may include a selective connector, including: a first connection interface coupled to the first rigid panel, and a second connection interface coupled to the second rigid panel.
Inventor(s): Michael Cameron GORDON of Sammamish WA (US) for microsoft technology licensing, llc
IPC Code(s): E05B47/00, G06F1/16
CPC Code(s): E05B47/004
Abstract: the presently disclosed magnetic locking mechanism(s) for a computing device enclosure is directed at providing a fast, but tamper resistant solution for assembly and disassembly of a computing device having top and base enclosures that come together to form an overall enclosure for the computing device. top and base enclosures that incorporate one or more of the presently disclosed magnetic locking mechanisms are capable of being quickly and easily attached and detached without damaging the computing device, so long as a correct magnetic key(s) are used. this aids both repairability and upgradability of the computing device during its life cycle, as well as recyclability at the end of its life cycle. without the correct magnetic key(s), it is difficult to separate the enclosures without damaging one or both of the enclosures.
Inventor(s): Xiang MA of Portland OR (US) for microsoft technology licensing, llc
IPC Code(s): G06F3/06
CPC Code(s): G06F3/065
Abstract: embodiments of the present disclosure include techniques for memory management. in various embodiments. a memory controller mirrors memory transactions on first data in a memory when the address for the transaction is within a first range. transactions outside the first range may not be mirrored.
Inventor(s): Amar PHANISHAYEE of Seattle WA (US) for microsoft technology licensing, llc, . Ankit of Boston MA (US) for microsoft technology licensing, llc, Deepak NARAYANAN of Bellevue WA (US) for microsoft technology licensing, llc, Mihail Gavril TARTA of Sammamish WA (US) for microsoft technology licensing, llc
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5011
Abstract: systems and methods for optimizing thread allocation in a model serving system include estimating a batch size for inference requests. an optimal configuration is then determined that defines a number of inference instances, a number of threads per inference instance, and a sub-batch size per inference instance for processing a batch of inference requests of the batch size using intra-operator parallelism that minimizes average per-batch latency. the optimal configuration is determined with reference to a plurality of predetermined model profiles that define single-inference average batch latencies for different combinations of thread counts and batch sizes, the predetermined model profiles being used as input to a dynamic programming algorithm that identifies optimal configurations that minimize the average per-batch latency.
Inventor(s): Anatoliy BURUKHIN of Redmond WA (US) for microsoft technology licensing, llc, Alexey SOLOVEYCHIK of Bellevue WA (US) for microsoft technology licensing, llc, Constantin Sorin OPREA of Bothell WA (US) for microsoft technology licensing, llc
IPC Code(s): G06F16/23, G06F40/58
CPC Code(s): G06F16/23
Abstract: a method for managing localized resources displayable during execution of a software product includes receiving a localization build request from a source control platform. the localization build request specifies a unique resource identifier and a resource value for each of multiple displayable resources associated with execution of the software product in a default geographic locale. for each displayable resource, the method further includes determining a relevant recency timestamp based on a build timestamp of the localization build request and retrieving, based on the relevant recency timestamp for the displayable resource, at least one translated resource indexed in association with the relevant recency timestamp. the method still further includes adding the at least one translated resource to a localization build for the software product and returning the localization build to the source control platform.
Inventor(s): Deepak SAINI of Bellevue WA (US) for microsoft technology licensing, llc, Jian JIAO of Bellevue WA (US) for microsoft technology licensing, llc, Aditya Lakshman KALARI of Seattle WA (US) for microsoft technology licensing, llc, Chaoyin LI of Issaquah WA (US) for microsoft technology licensing, llc
IPC Code(s): G06F16/332, G06F16/31, G06F40/284, G06F40/30
CPC Code(s): G06F16/332
Abstract: an information retrieval technique uses one or more machine-trained models to generate one or more metadata embeddings. the technique then combines a query embedding with the metadata embedding(s). in some cases, the technique performs this operation using a graph convolution operation. this yields an augmented embedding. the technique then uses the augmented embedding to retrieve at least one item. the augmented embedding lies in the same vector space as target-item embeddings associated with candidate target items. otherwise, the vector spaces associated with the query embedding and metadata embedding(s) can be different. in some implementations, the technique use dense retrieval, which enables the technique to deliver output results in real time.
Inventor(s): Karishma DIXIT of Cheltenham (GB) for microsoft technology licensing, llc
IPC Code(s): G06F21/55, G06N3/0455, G06N20/00
CPC Code(s): G06F21/552
Abstract: the output of an autoencoder model is used to provide reasons for classifying logged event data as anomalous. multivariate input feature vectors based on the event data are applied to the autoencoder model to generate corresponding predicted multivariate feature vectors with respective feature elements. each feature element of each vector corresponds to a respective type of event data (e.g., sign-in failures). a reconstruction loss is determined for each predicted feature vector and used to classify the predicted feature vector as anomalous or not anomalous. reason(s) for an anomaly classification are determined by selecting one or more feature elements based on a level of percent contribution to the vectors loss and underprediction or overprediction, determined for each feature element of the anomalous predicted feature vector. each reason is related to the type of event associated with a selected feature element. the reasons may be displayed in a security analytics ui.
Inventor(s): Tamer SALMAN of Haifa (IL) for microsoft technology licensing, llc
IPC Code(s): G06F21/55
CPC Code(s): G06F21/554
Abstract: methods, systems, and computer storage media for providing security posture management using an artificial intelligence security engine in a security management system. security posture management supports security management of a computing environment based on contextual information associated with artificial-intelligence-supported applications. the security management system provides an artificial intelligence security graph associated with the artificial-intelligence-supported applications. the artificial intelligence engine uses the artificial intelligence security graph to correlate artificial intelligence attack monitoring data with operational data of the artificial-intelligence-supported applications. in operation, artificial intelligence attack monitoring data is accessed. an artificial intelligence security graph associated with a plurality of artificial-intelligence-supported applications is accessed. based on the artificial intelligence attack monitoring data and the artificial intelligence security graph, operational data of an artificial-intelligence-supported application is accessed. the artificial intelligence attack monitoring data and the operational data are analyzed to identify an artificial intelligence security alert. the artificial intelligence security alert is communicated.
Inventor(s): Kim CAMERON of Toronto, ON (CA) for microsoft technology licensing, llc
IPC Code(s): G06F21/62
CPC Code(s): G06F21/6245
Abstract: generating and associating decentralized identifiers (dids) for a group of one or more related devices. first, a device group did is generated. the device group did is associated with a group of one or more related devices. for each of the group of one or more related devices, a device did is generated, and associated with the corresponding device. a scope of permission is granted to the device group did. in response to the granting the scope of permission to the device group did, each device did is granted a subset of the scope of permission.
Inventor(s): Garret BUBAN of Snoqualmie WA (US) for microsoft technology licensing, llc
IPC Code(s): G06F21/64, G06F21/60, H04L9/32
CPC Code(s): G06F21/64
Abstract: timestamps are used to prevent data tampering. a trusted data generator generates a concatenated data object including a data object and metadata, which includes a location indication, a timestamp, and, depending on the type of encryption, an integrity value. the trusted timestamp generator encrypts the concatenated data object, stores the encrypted concatenated data object (e.g., in untrusted storage) in accordance with a location indicated by the location indication, and protects the timestamp in trusted storage (e.g., by protecting at least the root timestamp). a trusted data validator extracts the data object and metadata from the decrypted concatenated data object and validates the data object by comparing the storage location to the extracted location indication, the protected timestamp to the extracted timestamp, and a calculated integrity value to the extracted integrity value. timestamps may be validated without calculations and with tolerances, supporting performance customization/security optimization.
Inventor(s): Joseph John MCDAID of Seattle WA (US) for microsoft technology licensing, llc, Su-Piao WU of Sammamish WA (US) for microsoft technology licensing, llc, Alexander Yuryevich NOVOKHODKO of Redmond WA (US) for microsoft technology licensing, llc, Guido VAN ROSSUM of Belmont CA (US) for microsoft technology licensing, llc
IPC Code(s): G06F40/18
CPC Code(s): G06F40/18
Abstract: technology is disclosed herein for integrating native and non-native dependencies in a spreadsheet hosted by a spreadsheet application. in an implementation, a computing apparatus identifies a formula in a first cell of a spreadsheet which includes a non-native argument. the computing apparatus identifies a dependency between the first cell and a second cell created by the non-native argument. the computing apparatus limits recalculations of the spreadsheet based at least on the dependency. in an implementation, absent any other dependencies between the first cell and other cells, the first cell is excluded from recalculations triggered by changes to the other cells and included in recalculations triggered by the second cell. in an implementation, a direct or indirect dependency is created by, respectively, an explicit or implicit reference to the second cell in the non-native argument. in some implementations, the formula is native to the spreadsheet application hosting the spreadsheet.
Inventor(s): Chenguang ZHU of Sammamish WA (US) for microsoft technology licensing, llc, Yang LIU of Nanjing, Jiangsu (CN) for microsoft technology licensing, llc, David Peace HUNG of Shoreline WA (US) for microsoft technology licensing, llc, Nanshan ZENG of Bellevue WA (US) for microsoft technology licensing, llc
IPC Code(s): G06F40/284, G06F40/30, G10L15/26
CPC Code(s): G06F40/284
Abstract: the disclosure herein describes using a deep learning model to identify topic segments of a communication transcript. a communication transcript including a set of utterances is obtained. the set of utterances is divided into a plurality of utterance windows, wherein each utterance window of the plurality of utterance windows includes a different subset of utterances of the set of utterances, and wherein each utterance of the set of utterances is included in at least one utterance window of the plurality of utterance windows. for each utterance window of the plurality of utterance windows, each utterance in the utterance window is classified as a topic boundary or a non-boundary using a deep learning model. topic segments of the communication transcript are identified based on utterances of the set of utterances that are classified as topic boundaries. a communication transcript summary is generated using the communication transcript and the identified topic segments.
Inventor(s): Daniel Lo of Bothell WA (US) for microsoft technology licensing, llc, Bita Darvish Rouhani of Bellevue WA (US) for microsoft technology licensing, llc, Eric S. Chung of Woodinville WA (US) for microsoft technology licensing, llc, Yiren Zhao of Cambridge (GB) for microsoft technology licensing, llc, Amar Phanishayee of Seattle WA (US) for microsoft technology licensing, llc, Ritchie Zhao of Ithaca NY (US) for microsoft technology licensing, llc
IPC Code(s): G06N3/063, G06F9/30, G06F18/21, G06N3/084
CPC Code(s): G06N3/063
Abstract: apparatus and methods for training a neural network accelerator using quantized precision data formats are disclosed, and, in particular, for adjusting floating-point formats used to store activation values during training. in certain examples of the disclosed technology, a computing system includes processors, memory, and a floating-point compressor in communication with the memory. the computing system is configured to produce a neural network comprising activation values expressed in a first floating-point format, select a second floating-point format for the neural network based on a performance metric, convert at least one of the activation values to the second floating-point format, and store the compressed activation values in the memory. aspects of the second floating-point format that can be adjusted include the number of bits used to express mantissas, exponent format, use of non-uniform mantissas, and/or use of outlier values to express some of the mantissas.
Inventor(s): Nicolas Guillaume DELFOSSE of Seattle WA (US) for microsoft technology licensing, llc, Adam Edward PAETZNICK of Bellevue WA (US) for microsoft technology licensing, llc
IPC Code(s): G06N10/20, G06N10/70
CPC Code(s): G06N10/20
Abstract: a method to forecast the result of a clifford circuit acting on the qubits comprises: for a fault operator f acting on the qubits, precomputing a backward cumulant of the fault operator for each row u of binary matrices mand m, the backward cumulant reflecting an effect f=eff(f) on measurement outcomes of the qubits according to the clifford circuit and fault operator; sampling the fault operator f for the qubits according to the predetermined noise distribution in the clifford circuit; computing a syndrome s=mf corresponding to the effect based on a commutator of the backward cumulant versus a row of the binary matrix m; computing a set of logical flips =mf corresponding to the effect based on a commutator of the backward cumulant versus a row of the binary matrix m; and returning the result based on the syndrome and on the set of logical flips.
Inventor(s): Adam Edward PAETZNICK of Bellevue WA (US) for microsoft technology licensing, llc, Nicolas Guillaume DELFOSSE of Seattle WA (US) for microsoft technology licensing, llc, Jeongwan HAAH of Bellevue WA (US) for microsoft technology licensing, llc, Michael Edward BEVERLAND of Seattle WA (US) for microsoft technology licensing, llc
IPC Code(s): G06N10/70
CPC Code(s): G06N10/70
Abstract: a method to correct a fault in the application of a clifford circuit to a qubit register of a quantum computer comprises: (a) receiving circuit data defining the clifford circuit; (b) receiving additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice; (c) emitting an outcome code based on the circuit data, the outcome code including a series of outcome checks each corresponding to an anticipated error syndrome for the application of the clifford circuit to the qubit register; and (d) emitting a topological outcome code based on the circuit data, the additional data, and the outcome code, the topological outcome code including a series of check operators that support quantum-error correction via a topological decoder, thereby enabling fault correction in the application of the clifford circuit to the qubit register.
Inventor(s): Xinhui GE of Sammamish WA (US) for microsoft technology licensing, llc, Veeravenkata Satya Sridhar MADDIPATI of Issaquah WA (US) for microsoft technology licensing, llc, Venkatasatya Premnath AYYALASOMAYAJULA of Sammamish WA (US) for microsoft technology licensing, llc, Nikhil VERMA of Sammamish WA (US) for microsoft technology licensing, llc, Mara SAVELIEV of Redmond WA (US) for microsoft technology licensing, llc, John Theodore NASSIF of Sugar Hill GA (US) for microsoft technology licensing, llc
IPC Code(s): G06Q30/015
CPC Code(s): G06Q30/015
Abstract: a system and method for detecting trending topics in customer inquiries includes retrieving customer inquiries from a plurality of data sources for a target time window and reference time windows and detecting trending keywords in the target time window as compared to keywords in the reference time windows. responsive to detecting the trending keywords, customer inquiries in the target time window that include one or more of the trending keywords are collected and a weight is measured for each collected customer inquiry based on weights of detected trending keywords in each collected customer inquiry. a connection graph is generated for the detected trending keywords and the collected customer inquiries. the detected trending keywords are then clustered into a plurality of trending topics based on the connection graph, and the trending topics are ranked based on the measured weights of the collected customer inquiries associated with each trending topic.
Inventor(s): Amar PHANISHAYEE of Seattle WA (US) for microsoft technology licensing, llc, Divya MAHAJAN of Seattle WA (US) for microsoft technology licensing, llc, Jakub Michal TARNAWSKI of Küsnacht (CH) for microsoft technology licensing, llc
IPC Code(s): G06T1/20, G06N3/098
CPC Code(s): G06T1/20
Abstract: a training optimization system implements algorithmic solutions to solve the conjoined problem of accelerator architecture search and model partitioning for distributed training. the system makes the multi-dimensional optimization space of architecture search and device placement tractable by reducing the number of accelerator architectures explored through area-based heuristics and employing a novel integer linear program (ilp), the size of which is dependent only on the number of operators. the ilp scheduling optimization also explores the partitioning of operators across cores, known as intra-operator parallelism. despite the vast space, the ilp described herein requires significantly less time to perform the optimizations across all explored accelerator configurations. based on the optimal backward and forward pass latencies, the system leverages a novel dynamic programming (dp) approach to determine the device placement and model partitioning scheme.
Inventor(s): Benjamin James ANDREWS of Seattle WA (US) for microsoft technology licensing, llc
IPC Code(s): G06T19/00, H04N21/2187
CPC Code(s): G06T19/006
Abstract: the disclosure herein describes enabling a user of a remote mixed reality (mr) device to observe an environment of a local mr device combined with 3d surface reconstruction (sr) mesh data and live video data. optical data of a surface of an environment is obtained and a 3d surface reconstruction mesh of the surface is generated from the obtained optical data using photogrammetry. the generated 3d surface reconstruction mesh is provided for display by a remote device. a live video feed of a window region of the environment is obtained and the live video feed of the window region is provided for display on the generated 3d surface reconstruction mesh by the remote device. further, a remote user is enabled to provide feedback to a user of the local mr device, including audio feedback such as speech and virtual artifacts that are displayed to the local user.
Inventor(s): Eric C. PETERSON of Woodinville WA (US) for microsoft technology licensing, llc, Husam Atallah ALISSA of Redmond WA (US) for microsoft technology licensing, llc, Sean Patrick ABBOTT of Redmond WA (US) for microsoft technology licensing, llc
IPC Code(s): H01L23/473, H05K7/20
CPC Code(s): H01L23/473
Abstract: a cold plate assembly for cooling a computing device includes a first cooling structure and a second cooling structure. the first cooling structure is configured to provide cooling from a flow of first coolant to a first temperature section of the computing device. the second cooling structure is connected to the first cooling structure and is configured to provide cooling from a flow of second coolant to a second temperature section of the computing device. the second temperature section has a lower temperature threshold than the first temperature section. the cold plate assembly includes a thermal barrier between the first cooling structure and the second cooling structure.
Inventor(s): Mojtaba BISHEH NIASAR of Ithaca NY (US) for microsoft technology licensing, llc, Bharat S. Pillilli of El Dorado Hills CA (US) for microsoft technology licensing, llc
IPC Code(s): H04L9/06, G06F7/72
CPC Code(s): H04L9/06
Abstract: montgomery multiplier architectures are provided. a circuit can include an initial processing element (pe) circuit configured to generate a first output including (i) a radix of a carry out and (ii) a radix of an intermediate result based on radixes of respective operands, a radix of an inverse of a modulus, and a radix of the modulus, middle pe circuits configured to generate a second output including (i) respective radixes of a montgomery multiplication result and (ii) further respective radixes of a carry out on two consecutive clock cycles based on the first output, and a final pe circuit configured to generate further radixes of the montgomery multiplication results on two consecutive, subsequent clock cycles based on the second output.
Inventor(s): Maksymilian CEGIELSKI-JOHNSON of Redmond WA (US) for microsoft technology licensing, llc, Hongwei LIANG of Bellevue WA (US) for microsoft technology licensing, llc, Sandipan GANGULY of Redmond WA (US) for microsoft technology licensing, llc, Samantha SIFLEET of Renton WA (US) for microsoft technology licensing, llc
IPC Code(s): H04L67/50, G06F16/34, G06F16/901
CPC Code(s): H04L67/535
Abstract: a system and method measuring data, from user devices, regarding user interactions with a software-as-a-service (saas) product installed in each of the user devices, using a measurement module in the processor to generate measured data. the measured data is then modeled as a graph, using a graphing application in the processor, wherein the graph includes a plurality of varying metrics, each representing different attributes of a structure of the graph. a viral effectiveness index (vei) as a single metric summarizing core graph attributes of the graph is determined from the plurality of the varying metrics of the graph using a viral effectiveness index (vei) module in an analytics application in the processor.
Inventor(s): Saswata MANDAL of Bellevue WA (US) for microsoft technology licensing, llc, Ryan Yonghee KIM of Bellevue WA (US) for microsoft technology licensing, llc, Kathleen Anne SLATTERY of Seattle WA (US) for microsoft technology licensing, llc
IPC Code(s): H04N7/01, H04N9/64, H04N19/85
CPC Code(s): H04N7/01
Abstract: the present disclosure relates to systems and methods for transmitting standard dynamic range (sdr) content. the systems and methods may use a modified electro-optical transfer function (eotf) curve to convert nonlinear color values of sdr content into optical output values of modified sdr content. the systems and methods may encode the modified sdr content using eight bits while preventing banding. the systems and methods may transmit the encoded data to a client device for presentation on a display.
Inventor(s): Anuj KALIA of San Francisco CA (US) for microsoft technology licensing, llc, Junzhi GONG of Cambridge MA (US) for microsoft technology licensing, llc
IPC Code(s): H04W36/00, H04W36/08, H04W36/22
CPC Code(s): H04W36/13
Abstract: the present disclosure relates to systems, methods, and computer-readable media for increasing resiliency in distributed units of a virtual radio access network (vran) of a telecommunications network (e.g., a 5g telecommunications network), particularly when performing a planned handover operation between the distributed units. the examples described herein specifically relate to implementing an inter-distributed unit handover between distributed units that are serviced by the same radio unit. in some examples, this handover is initiated by a middlebox entity that is positioned between the distributed units and a centralized unit. in some instances, features of the middlebox entity are implemented within the framework of a centralized unit. by allowing a quick handover as described herein, the distributed units can provide uninterrupted service to a ue while allowing the distributed units to perform various upgrades or modifications to the distributed unit without service interruptions.
Inventor(s): Matthew David TURNER of Carnation WA (US) for microsoft technology licensing, llc, Craig Steven RANTA of Olympia WA (US) for microsoft technology licensing, llc, Kevin James KRAMER of Redmond WA (US) for microsoft technology licensing, llc
IPC Code(s): H05K1/02, H05K7/20
CPC Code(s): H05K1/0203
Abstract: systems and methods for supporting a high thermal gradient between a qubit plane and a control system for the qubit plane are described. a system includes a qubit plane associated with a first rigid circuit portion of a superconducting rigid-flex circuit and a control system associated with a second rigid circuit portion of the superconducting rigid-flex circuit. the superconducting rigid-flex circuit includes a flexible circuit portion for interconnecting the first rigid circuit portion with the second rigid circuit portion. the system further includes a first cooling system operable to maintain an operating temperature for the qubit plane and the first rigid circuit portion of the superconducting rigid-flex circuit at or below 100 milli-kelvin. the system further includes a second cooling system operable to maintain an operating temperature for the control system and the second rigid circuit portion of the superconducting rigid-flex circuit at or below 10 kelvin.
Inventor(s): Eric C. PETERSON of Woodinville WA (US) for microsoft technology licensing, llc, Husam Atallah ALISSA of Redmond WA (US) for microsoft technology licensing, llc, Sean Patrick ABBOTT of Redmond WA (US) for microsoft technology licensing, llc
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20272
Abstract: a cold plate assembly for cooling a computing device includes a first cooling structure and a second cooling structure. the first cooling structure is configured to provide cooling from a flow of first coolant to a first temperature section of the computing device. the second cooling structure is connected to the first cooling structure and is configured to provide cooling from a flow of second coolant to a second temperature section of the computing device. the second temperature section has a lower temperature threshold than the first temperature section. the cold plate assembly includes a thermal barrier between the first cooling structure and the second cooling structure.
Inventor(s): Jason A. HARRIGAN of Sultan WA (US) for microsoft technology licensing, llc, David Bennett JOHNSON of Seattle WA (US) for microsoft technology licensing, llc
IPC Code(s): H05K7/20, H05K9/00
CPC Code(s): H05K7/2039
Abstract: a thermal management device includes a fin pack and a plurality of channels. the fin pack has a hot side and a cold side, and the plurality of channels in the fin pack provide fluid communication from the hot side to the cold side. the channels have a transverse dimension and a longitudinal dimension, and the longitudinal dimension is at least 2.5 times the transverse dimension.
Inventor(s): Eric C. PETERSON of Woodinville WA (US) for microsoft technology licensing, llc, Husam Atallah ALISSA of Redmond WA (US) for microsoft technology licensing, llc, Sean Patrick ABBOTT of Redmond WA (US) for microsoft technology licensing, llc
IPC Code(s): H05K7/20, H01L23/427
CPC Code(s): H05K7/20809
Abstract: a cold plate assembly for cooling a computing device includes a first cooling structure and a second cooling structure. the first cooling structure is configured to provide cooling from a flow of first coolant to a first temperature section of the computing device. the second cooling structure is connected to the first cooling structure and is configured to provide cooling from a flow of second coolant to a second temperature section of the computing device. the second temperature section has a lower temperature threshold than the first temperature section. the cold plate assembly includes a thermal barrier between the first cooling structure and the second cooling structure.
Microsoft Technology Licensing, LLC patent applications on February 20th, 2025
- Microsoft Technology Licensing, LLC
- A63F11/00
- CPC A63F11/00
- Microsoft technology licensing, llc
- E05B47/00
- G06F1/16
- CPC E05B47/004
- G06F3/06
- CPC G06F3/065
- G06F9/50
- CPC G06F9/5011
- G06F16/23
- G06F40/58
- CPC G06F16/23
- G06F16/332
- G06F16/31
- G06F40/284
- G06F40/30
- CPC G06F16/332
- G06F21/55
- G06N3/0455
- G06N20/00
- CPC G06F21/552
- CPC G06F21/554
- G06F21/62
- CPC G06F21/6245
- G06F21/64
- G06F21/60
- H04L9/32
- CPC G06F21/64
- G06F40/18
- CPC G06F40/18
- G10L15/26
- CPC G06F40/284
- G06N3/063
- G06F9/30
- G06F18/21
- G06N3/084
- CPC G06N3/063
- G06N10/20
- G06N10/70
- CPC G06N10/20
- CPC G06N10/70
- G06Q30/015
- CPC G06Q30/015
- G06T1/20
- G06N3/098
- CPC G06T1/20
- G06T19/00
- H04N21/2187
- CPC G06T19/006
- H01L23/473
- H05K7/20
- CPC H01L23/473
- H04L9/06
- G06F7/72
- CPC H04L9/06
- H04L67/50
- G06F16/34
- G06F16/901
- CPC H04L67/535
- H04N7/01
- H04N9/64
- H04N19/85
- CPC H04N7/01
- H04W36/00
- H04W36/08
- H04W36/22
- CPC H04W36/13
- H05K1/02
- CPC H05K1/0203
- CPC H05K7/20272
- H05K9/00
- CPC H05K7/2039
- H01L23/427
- CPC H05K7/20809
