Micron technology, inc. (20250148182). SPATIALLY AWARE LOW POWER TECHNIQUES FOR DESIGN FOR TESTABILITY
SPATIALLY AWARE LOW POWER TECHNIQUES FOR DESIGN FOR TESTABILITY
Organization Name
Inventor(s)
Banadappa Shivaray of Gulbarga IN
Shrikrishna Pundoor of Bangalore IN
Kantharaj Shamenahalli Eswarappa of Bangalore IN
SPATIALLY AWARE LOW POWER TECHNIQUES FOR DESIGN FOR TESTABILITY
This abstract first appeared for US patent application 20250148182 titled 'SPATIALLY AWARE LOW POWER TECHNIQUES FOR DESIGN FOR TESTABILITY
Original Abstract Submitted
the subject application relates to spatially aware design for testability (dft). for instance, a method may include dividing a layout of a circuit under test (cut) into a plurality of grids based on a preconfigured policy, creating, based on the preconfigured policy, a plurality of targeted portions from the divided layout of the cut, applying a dft test pattern to the plurality of targeted portions; and capturing data output from the plurality of targeted portions.