Micron technology, inc. (20250130937). ADDRESS TRANSLATION IN A MEMORY SUB-SYSTEM FOR MEMORY POOLING
ADDRESS TRANSLATION IN A MEMORY SUB-SYSTEM FOR MEMORY POOLING
Organization Name
Inventor(s)
Rishabh Dubey of Agrate Brianza IT
ADDRESS TRANSLATION IN A MEMORY SUB-SYSTEM FOR MEMORY POOLING
This abstract first appeared for US patent application 20250130937 titled 'ADDRESS TRANSLATION IN A MEMORY SUB-SYSTEM FOR MEMORY POOLING
Original Abstract Submitted
a system including a memory device and an operatively coupled processing device to perform operations determining a size of a minimum allocation unit (mau) for a plurality of logical devices, dividing the memory device into logical units with a size equal to the mau, identifying, using a logical device identifier (ldi) data structure, a first ldi that is available, wherein the first ldi identifies a first logical device, identifying, using a logical unit identifier (lui) data structure, a first set of lui that are available, wherein the first set of lui identify a first set of logical units, allocating the first set of logical units to the first logical device, and updating an ldi-to-lui mapping data structure to reflect that the first set of logical units are allocated to the first logical device.