Micron technology, inc. (20250087254). MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
Organization Name
Inventor(s)
John D. Porter of Boise ID (US)
MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
This abstract first appeared for US patent application 20250087254 titled 'MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
Original Abstract Submitted
systems and method for sensing an accessed voltage value associated with a memory cell is described. in different embodiments, a memory array may include a different number of sense components. moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. for example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.