Micron technology, inc. (20250014640). DECODER ARCHITECTURE FOR MEMORY DEVICE
DECODER ARCHITECTURE FOR MEMORY DEVICE
Organization Name
Inventor(s)
Ferdinando Bedeschi of Biassono IT
Jeffrey E. Koelling of Fairview TX US
Riccardo Muzzetto of Arcore IT
DECODER ARCHITECTURE FOR MEMORY DEVICE
This abstract first appeared for US patent application 20250014640 titled 'DECODER ARCHITECTURE FOR MEMORY DEVICE
Original Abstract Submitted
methods, systems, and devices for decoder architecture for memory device are described. an apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. the decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. the second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. the second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.