Micron technology, inc. (20240413841). APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION

APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION

Organization Name

micron technology, inc.

Inventor(s)

Jiyun Li of Boise ID (US)

Toby D. Robbs of Boise ID (US)

APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION

This abstract first appeared for US patent application 20240413841 titled 'APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION

Original Abstract Submitted

apparatuses and methods for on-device error correction implemented in a memory. a memory may have a first column plane comprising a first number of bit lines and a parity column plane that has a second number of parity bit lines in which the first number is different than the second number. in an access operation, a column select signal may activate the first number of bit lines in the first column plane and the second number of parity bit lines in the second column plane.