Patent Applications by Micron Technology Inc on 4th September 2025

Micron Technology Inc: 34 patent applications

Micron Technology Inc has applied for patents in the areas of G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}, 8), G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}, 5), G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}, 4), G06F3/064 ({Management of blocks}, 3), G06F3/0673 ({Single storage device}, 3)

Patent Applications by Micron Technology Inc

20250277682. DEVICES WITH ENVIRONMENTAL STRESS INDICATORS

Abstract: Systems, apparatuses, and methods related to a substrate with one or more environmental stress indicators configured to detect and log environmental stress are described. The environmental stress indicators are configured to change a continuity state when exposed to one or more environmental stresse...

20250278186. BAD-DECK MANAGEMENT FOR HALF-GOOD BLOCKS

Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to perform operations including setting a partial translation unit (TU) pointer to identify a first partial-TU of an ordered sequence of partial-TUs, the ordered sequence span...

20250278187. CLUSTERED PARITY FOR NAND DATA PLACEMENT SCHEMA

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and pla...

20250278193. MANAGING I/O OPERATIONS ASSOCIATED WITH A COMPUTE EXPRESS LINK (CXL) MEMORY DEVICE

Abstract: A system can include a plurality of dynamic capacity devices and a processing device to perform operations including receiving, from a host system, a request to perform an input/output (I/O) operation at a first memory region of a first dynamic capacity device. The operations include determining, ba...

20250278194. COMMANDED DEVICE STATES FOR A MEMORY SYSTEM

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resour...

20250278196. BOOT OPERATIONS AND LOGICAL BLOCK ADDRESSES

Abstract: Methods, systems, and devices for boot operations and logical block addresses are described. A memory system may identify logical block addresses (LBAs) that are more frequently accessed during the boot phase relative to other LBAs. Such LBAs may be referred to herein as boot LBAs. For example, the ...

20250278198. INTERFACE TECHNIQUES FOR MULTI-CHANNEL MEMORY DEVICES

Abstract: Methods, systems, and devices for interface techniques for multi-channel memory devices are described. A memory device may be configured with multiple channels (e.g., channel sets) that can be operated in different modes, such as a standard mode and an evaluation mode. In a standard mode, the memory...

20250278199. VARIABLE-LENGTH CONSTRAINT ENCODING TO IMPROVE ENDURANCE

Abstract: A command to write data to a memory device is received. Based on the command, the data is encoded using a variable-length constraint encoding scheme. The encoding of the data includes generating a codeword based on a bit sequence from the data. The number of logical one bits in the codeword correspo...

20250278202. EDGE BLOCK ASSIGNMENT TO SINGLE LEVEL CELL (SLC) MODE IN MEMORY DEVICES

Abstract: One or more edge blocks of a die of a memory device are identified. A block assignment data structure associated with the memory device is identified. The block assignment data structure comprises a plurality of records, each record mapping one or more specific blocks of the memory device to a corre...

20250278206. BOOT AND INITIALIZATION TECHNIQUES FOR STACKED MEMORY ARCHITECTURES

Abstract: Methods, systems, and devices for boot and initialization techniques for stacked memory architectures are described. A memory system may include a common logic block operable to output an indication to each of a set of multiple interface blocks to initiate an initialization program, an evaluation pr...

20250278209. INCOMPLETE SUPERBLOCK TECHNIQUES

Abstract: Methods, systems, and devices for incomplete superblock techniques are described. The described techniques provide for a memory system to perform bad block replacement procedures without increasing a size of a bad block table. For example, the memory system may consolidate bad physical blocks such t...

20250278212. TECHNIQUES FOR IMPROVED WRITE PERFORMANCE MODES

Abstract: Methods, systems, and devices for techniques for improved write performance modes are described. A memory system and a host system may support a high performance mode to write data to the memory system. For example, the host system may provision a dedicated logical unit of the memory system. Upon de...

20250278245. MULTIPLY-ACCUMULATE UNIT INPUT MAPPING

Abstract: The PU of a memory device can receive a matrix of data values and a vector of data values stored in the bank. The PU can perform a first plurality of multiplication operations on a first data value of the vector utilizing a first plurality of data values of a first column of the matrix. The first pl...

20250278276. APPARATUSES, SYSTEMS, AND METHODS FOR MODE REGISTER PAGE ACCESS MODES

Abstract: Embodiments disclosed herein provide techniques for entering, remaining, and exiting a mode register page access (MRPA) mode in a semiconductor device (e.g., a memory device). A command is used to cause the memory device to enter the MRPA mode when accessing the mode register, and a subsequent comma...

20250278306. ALLOCATION OF REPAIR RESOURCES IN A MEMORY DEVICE

Abstract: In some implementations, a central processing unit (CPU) associated with a controller of a memory device may determine that a portion of a memory associated with a logical address is to be repaired. The CPU and/or a resources tracker component associated with the controller a may determine an alloca...