Micron Technology, Inc. patent applications on May 8th, 2025
Patent Applications by Micron Technology, Inc. on May 8th, 2025
Micron Technology, Inc.: 50 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (11), H10B43/27 (7), H10B41/27 (5), H10B12/00 (4), H01L21/66 (4) G06F3/0659 (3), H10B43/27 (3), G06F3/064 (2), H01L25/18 (2), G06F12/1009 (2)
With keywords such as: memory, device, data, material, conductive, include, devices, region, host, and voltage in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): John D. Leidel of McKinney TX US for micron technology, inc.
IPC Code(s): G06F3/06, G06F13/16, G06F13/40, G06F13/42, G11C7/10, G11C21/00
CPC Code(s): G06F3/0607
Abstract: an interconnect system includes host devices, one or more memory devices, and a routing system to connect the host devices and the one or more memory devices. respective ones of the host devices include an interface to communicate packet requests over respective packetized links. respective ones of the one or more memory devices include an interface to receive and respond to the packet requests over the respective packetized links. the routing system includes devices interconnected in a routing topology. respective ones of the devices include a switch and interfaces. the routing system is to route the packet requests and responses between the host devices and respective memory device destinations over the respective packetized links. the host devices are to communicate cache coherency traffic to each other over at least one of the respective packetized links.
Inventor(s): Brent Carl Byron of Boise ID US for micron technology, inc., Suresh Rajgopal of San Diego CA US for micron technology, inc., Shakeel Bukhari of San Jose CA US for micron technology, inc., Jeonghun Kim of Fort Collins CO US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: various embodiments provide for incremental power throttling on a memory system, such as a memory sub-system. in particular, for some embodiments, incremental power throttling is implemented on a memory system using one or more power credit allocations and memory operation progress tracking.
20250147679. LIGHT HIBERNATION MODE FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Liang Ge of Shanghai CN for micron technology, inc.
IPC Code(s): G06F3/06, G06F1/324
CPC Code(s): G06F3/0625
Abstract: methods, systems, and devices for a light hibernation mode for memory are described. a memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). while operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.
Inventor(s): Luca Bert of Bologna (BO) IT for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a host system to query, during booting up of the host system, a superblock size in a connected memory sub-system. the host system can place write requests into separate streams and send the streams to the memory sub-system to store data of the write requests into separate sets of superblocks for the streams respectively. the host system can allocate, a plurality of log buffers for the streams respectively and record, into the log buffers, sequences of logical addresses as in the streams respectively. the host system can trim a stream, among the plurality of streams, by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a log buffer for the stream, causing the memory sub-system to free at least one superblock.
Inventor(s): Patrick R. Khayat of San Diego CA US for micron technology, inc., Steven Michael Kientz of Westminster CO US for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA US for micron technology, inc., Mustafa N. Kaynak of San Diego CA US for micron technology, inc., Vamsi Pavan Rayaprolu of San Jose CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.
20250147686. DATA RECOVERY IN MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Sampath K. Ratnam of San Jose CA US for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA US for micron technology, inc., Mustafa N. Kaynak of San Diego CA US for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA US for micron technology, inc., Kishore Kumar Muchherla of San Jose CA US for micron technology, inc., Shane Nowell of Boise ID US for micron technology, inc., Peter Feeley of Boise ID US for micron technology, inc., Qisong Lin of El Dorado Hills CA US for micron technology, inc.
IPC Code(s): G06F3/06, G06F11/10, G06F11/14, G11C29/52
CPC Code(s): G06F3/0647
Abstract: an example system includes a memory device; and a processing device, operatively coupled to the memory device, to perform operations, including: programming a plurality of pages of the memory device; adjusting a program verify voltage associated with the plurality of pages; responsive to determining that a first error rate of a first page of the plurality of pages exceeds a second error rate of a second page of the plurality of pages, performing a recovery operation on the first page to produce recovered data; and storing the recovered data on the memory device.
Inventor(s): Luca Bert of Bologna IT for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: a plurality of context data structures are maintained. each context data structure corresponds to an active region of a plurality of active regions of a memory device. a write request directed to a first active region is received. responsive to determining that a first indicator of the first context data structure associated with the first active region characterizes the first active region as closed, a second active region is identified. a buffer associated with the second active region is identified, wherein the buffer stores host data. the host data in the buffer is padded to a predetermined size, and the buffer is flushed to the second active region. the number of padding operations performed with respect to the second active region is incremented and the second context data structure is updated. the first indicator of the first context data structure is updated, characterizing the first context data structure as open.
20250147695. CACHING FOR MULTIPLE-LEVEL MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Reshmi Basu of Boise ID US for micron technology, inc., Jonathan S. Parry of Boise ID US for micron technology, inc., Nitul Gohain of Bangalore IN for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for caching for a multiple-level memory device are described. first data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. later, second data writing to the memory device may be received. based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
Inventor(s): Muthazhagan Balasubramani of Singapore SG for micron technology, inc.
IPC Code(s): G06F3/06, G06F11/08
CPC Code(s): G06F3/0659
Abstract: a host submits a command to a memory device, where a host status indicator (id) for the host and a memory device status id for the memory device are assigned with the command in at least one of a status command slot related to the command. an interrupt signal asserted during processing of the command is determined, where the interrupt signal is indicative of a change in at least one of the host status id and the memory device status id. after determining that the interrupt signal is asserted at least one of the host status id and the memory device status id are read. based on the read information, a failure in at least one of the host and device is corrected prior to initiation of a timeout process.
20250147701. SPECIFYING MEDIA TYPE IN WRITE COMMANDS_simplified_abstract_(micron technology, inc.)
Inventor(s): Daniel J. Hubbard of Boise ID US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: an example system includes: memory devices and a processing device operatively coupled to the memory devices. the processing device is configured to perform operations, including: receiving a write command specifying a data item and comprising a dedicated field specifying an identifier of a data stream, the data stream comprising a plurality of data items including the data item, such that the identifier of the data stream is enhanced by one or more data stream attributes shared by data items comprised by the data stream; determining, by parsing the identifier of the data stream, a data stream attribute of the one or more data stream attributes shared by data items comprised by the data stream; identifying, based on the data stream attribute, a memory device managed by the processing device; and transmitting, to the memory device, an instruction specifying the data item.
20250147710. DATA MIRRORING FOR A VIRTUAL ENVIRONMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): John D. Hopkins of Milpitas CA US for micron technology, inc., Mohad Baboli of Boise ID US for micron technology, inc.
IPC Code(s): G06F3/14, G06T3/40, G06T11/60
CPC Code(s): G06F3/1454
Abstract: methods, apparatus, and non-transitory machine-readable media associated with mirroring data for a virtual environment. an apparatus can include a memory device and a processor communicatively coupled to the memory device. the processor can receive data for display from a different apparatus that is coupled to the apparatus, wherein the different apparatus is a physical apparatus. the processor can modify image data for a virtual environment using the data. a display system coupled to the processor can display the modified image data of the virtual environment to mirror the data from the different apparatus to the virtual environment.
Inventor(s): Luca Bert of Bologna (BO) IT for micron technology, inc.
IPC Code(s): G06F9/54, G06F13/16
CPC Code(s): G06F9/546
Abstract: a storage product having: a network interface operable on a computer network; a bus connector adapted to be connected to a computer bus; a storage device having a storage capacity accessible through network storage services provided over the network interface; and a processing device configured to at least generate storage access messages from incoming packets received by the network interface from the computer network. the storage product is operable in a standalone mode when no local host system is connected to the bus connector to control the storage product and operable in a slave mode when a local host system is connected to the bus connector to process a portion of the storage access messages.
Inventor(s): Fanqi Wu of Sunnyvale CA US for micron technology, inc., Zhenlei Shen of Milpitas CA US for micron technology, inc., Jiangli Zhu of San Jose CA US for micron technology, inc., Tingjun Xie of Milpitas CA US for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0754
Abstract: a processing device in a memory sub-system identifies a read error associated with a block and determines a charge loss value associated with the block. the processing device determines whether the charge loss value is greater than or equal to a charge loss threshold. responsive to determining the charge loss value is greater than or equal to the charge loss threshold, the block is identified as a healthy block.
Inventor(s): Casto Salobrena Garcia of Munich DE for micron technology, inc., Kevin Gajera of Munich DE for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: methods, systems, and devices for implicit storage of metadata at a memory device are described. a memory device may perform an error correction code (ecc) decoding operation on a first set of parity bits for a set of data and a second set of parity bits for the set of data. the memory device may compare the first set of parity bits to the second set of parity bits based on the ecc decoding operation indicating that the set of data has an uncorrectable error, the first set of parity bits to the second set of parity bits. the memory device may recover metadata information, for the set of data, previously received by the memory device, based on the comparison.
Inventor(s): Shivasankar Gunasekaran of Erie CO US for micron technology, inc., Sai Krishna Mylavarapu of Folsom CA US for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1048
Abstract: methods, systems, and devices for data routing for error correction in stacked memory architectures are described. a system may support error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). for example, an interface of the second semiconductor die may receive data stored at a memory array of the first semiconductor die. the interface may include error correction engines each operable to correct one or more bit errors. the interface may also include logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets may be configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. the interface may output the data to a host system after the error control operations are performed.
Inventor(s): Marco Redaelli of Munich DE for micron technology, inc., Gaurav Sinha of Oberschleißheim DE for micron technology, inc., Zhang Lei of Singapore SG for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/108
Abstract: methods, systems, and devices for sorting retired blocks of non-volatile memory cells are described. a memory system may recover a block that has been marked as “bad” using a requalification process. for example, after operating in an error protection mode for the block, the memory system may monitor the block to determine whether a status flag indicating an access error is set. if the status flag is set, the memory system may store information that indicates the block is unrecoverable, and the block may subsequently be retired. alternatively, if a status flag is not set, the memory system may store information that indicates the block may be recoverable. if one or more additional access operations to the block are successful, the memory system may store information that indicates the block may be used for subsequent access operations.
Inventor(s): Angelo Visconti of Appiano IT for micron technology, inc., John David Porter of Boise ID US for micron technology, inc.
IPC Code(s): G06F11/30, G11C5/14
CPC Code(s): G06F11/3058
Abstract: systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. a system may include a memory device and a memory controller communicatively coupled to the memory device. the memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. the memory controller may perform a memory management operation based on the memory management interval. sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.
Inventor(s): Fa-Long Luo of San Jose CA US for micron technology, inc., Jaime Cummins of Bainbridge Island WA US for micron technology, inc., Tamara Schmitz of Scotts Valley CA US for micron technology, inc., Jeremy Chritz of Seattle WA US for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/06, G06F12/0864, G06F12/0893
CPC Code(s): G06F12/0207
Abstract: methods, apparatuses, and systems for tensor memory access are described. multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. a memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. at least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an nth dimension of the tensor or matrix. the memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.
Inventor(s): Amit Bhardwaj of Kokapet IN for micron technology, inc.
IPC Code(s): G06F12/1009
CPC Code(s): G06F12/1009
Abstract: an example system includes a memory device and a processing device, operatively coupled with the memory device. the processing device is configured to perform operations including: determining that a write request references a partially aligned translation unit; identifying a first entry in a translation map, such that the first entry identifies a first physical block of the memory device, such that the first physical block is mapped to the partially aligned translation unit; creating a second entry in the translation map, wherein the second entry identifies a second physical block of the memory device, wherein the second physical block is mapped to the partially aligned translation unit; linking, in the translation map, the first entry and the second entry; and writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block.
Inventor(s): Dmitri Yudanov of Sacramento CA US for micron technology, inc., Ameen D. Akel of Rancho Cordova CA US for micron technology, inc., Samuel E. Bradshaw of Sacramento CA US for micron technology, inc., Kenneth Marion Curewitz of Cameron Park CA US for micron technology, inc., Sean Stephen Eilert of Penryn CA US for micron technology, inc.
IPC Code(s): G06F12/1009, G06F12/1027, G06N5/043, G06N5/045, H04L67/1097, H04L67/568, H04W8/26
CPC Code(s): G06F12/1009
Abstract: systems, methods and apparatuses of fine grain data migration in using memory as a service (maas) are described. for example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). before accessing a virtual memory address in a sub-region, the memory status map is checked. if the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.
Inventor(s): Steven Jeffrey Wallach of Dallas TX US for micron technology, inc.
IPC Code(s): G06F21/62
CPC Code(s): G06F21/629
Abstract: systems, apparatuses, and methods related to securing domain crossing using domain access tables are described. for example, a computer processor can have registers configured to store locations of domain access tables respectively for predefined, non-hierarchical domains. each respective domain access table can be pre-associated with a respective domain and can have entries configured to identify entry points of the respective domain. the processor is configured to enforce domain crossing in instruction execution using the domain access tables and to prevent arbitrary and/or unauthorized domain crossing.
Inventor(s): Danilo Caraccio of Milano IT for micron technology, inc., Federica Cresci of Milan IT for micron technology, inc., Alessandro Orlando of Milano IT for micron technology, inc., Paolo Amato of Treviglio IT for micron technology, inc., Angelo Alberto Rovelli of Agrate Brianza IT for micron technology, inc., Craig A. Jones of Plano TX US for micron technology, inc., Niccolò Izzo of Vignate IT for micron technology, inc.
IPC Code(s): G06F21/79, G06F21/10, G06F21/55, G06F21/60, G11C11/22
CPC Code(s): G06F21/79
Abstract: systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. an example method can include receiving, at a memory controller and from a host, a command and firmware data. the memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (cxl) protocol. the command can be executed to update firmware stored on the non-volatile memory device. the method can further include accessing a first public key from the non-volatile memory device. the method can further include validating the first public key with a second public key within the firmware data. the method can further include validating the firmware data. the method can further include verifying a security version of the firmware data. the method can further include updating the non-volatile memory device with the firmware data.
Inventor(s): Mahesh Rawal of Hyderabad IN for micron technology, inc., Banadappa Shivaray of Gulbarga IN for micron technology, inc., Shrikrishna Pundoor of Bangalore IN for micron technology, inc., Kantharaj Shamenahalli Eswarappa of Bangalore IN for micron technology, inc.
IPC Code(s): G06F30/333, G06F30/392
CPC Code(s): G06F30/333
Abstract: the subject application relates to spatially aware design for testability (dft). for instance, a method may include dividing a layout of a circuit under test (cut) into a plurality of grids based on a preconfigured policy, creating, based on the preconfigured policy, a plurality of targeted portions from the divided layout of the cut, applying a dft test pattern to the plurality of targeted portions; and capturing data output from the plurality of targeted portions.
Inventor(s): Poorna Kale of Folsom CA US for micron technology, inc.
IPC Code(s): G06N3/063, G06F9/30, G06F9/50, G06F17/16, G06F30/27, G06N3/08
CPC Code(s): G06N3/063
Abstract: systems, devices, and methods related to a deep learning accelerator and memory are described. for example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (ram) to store parameters of an artificial neural network (ann). the device can generate random bit errors to simulate compromised or corrupted memory cells in a portion of the ram accessed during computations of a first ann output. a second ann output is generated with the random bit errors applied to the data retrieved from the portion of the ram. based on a difference between the first and second ann outputs, the device may adjust the ann computation to reduce sensitivity to compromised or corrupted memory cells in the portion of the ram. for example, the sensitivity reduction may be performed through ann training using machine learning.
20250148312. ADAPTIVE CONTENT INSPECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Paul D. Dlugosch of Eagle ID US for micron technology, inc., Harold B Noyes of Boise ID US for micron technology, inc.
IPC Code(s): G06N5/022, H04L9/40
CPC Code(s): G06N5/022
Abstract: methods and apparatus are provided involving adaptive content inspection. in one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. the host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. the results data may be processed before being provided to the content inspection processor.
Inventor(s): Junichi Sato of Yokohama JP for micron technology, inc.
IPC Code(s): G07C5/08, B60W50/02, G06F3/06, G07C5/00
CPC Code(s): G07C5/085
Abstract: a method for an autonomous vehicle includes: controlling at least one system of the vehicle by a host system; automatically collecting, by a memory device, data generated by the at least one system, where the data is collected by the memory device independently of control by the host system; and storing the data in the memory device.
Inventor(s): John D. Hopkins of Meridian ID US for micron technology, inc., Jordan D. Greenlee of Boise ID US for micron technology, inc., Peng Xu of Boise ID US for micron technology, inc.
IPC Code(s): G11C5/06, C23C8/06, C23C8/36, C23C28/00, H10B41/27, H10B41/35, H10B41/41, H10B43/27, H10B43/35, H10B43/40
CPC Code(s): G11C5/063
Abstract: some embodiments include a method of forming a conductive structure. a metal-containing conductive material is formed over a supporting substrate. a surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and to at least one oxidant. the exposure alters at least a portion of the metal-containing conductive material to thereby form at least a portion of the conductive structure. some embodiments include a conductive structure which has a metal-containing conductive material with a first region adjacent to a second region. the first region has a greater concentration of one or both of fluorine and boron relative to the second region.
Inventor(s): Ugo Russo of Boise ID US for micron technology, inc.
IPC Code(s): G11C7/10, G11C8/12, G11C11/56, G11C16/08, G11C19/32, H10B41/35, H10B43/27
CPC Code(s): G11C7/1006
Abstract: some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. channel material pillars extend through the stack. some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. memory cells are along the channel material pillars. an insulative level is over the stack. a select gate configuration is over the insulative level. the select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. the first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. the first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. some embodiments include methods of forming assemblies.
Inventor(s): Yi-Min Lin of San Jose CA US for micron technology, inc., Fangfang Zhu of San Jose CA US for micron technology, inc., Chih-Kuo Kao of Fremont CA US for micron technology, inc.
IPC Code(s): G11C11/4074, G11C11/4076, G11C11/4096, G11C29/42
CPC Code(s): G11C11/4074
Abstract: a memory system includes a memory device and a processing device coupled to the memory device. the processing device receives a plurality of codewords; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a time elapsed since a last write operation with respect to a management unit comprising the one or more codewords; and applies the first read voltage to a set of memory cells storing the one or more codewords.
Inventor(s): Yuko Watanabe of Tokyo JP for micron technology, inc., Takefumi Shirako of Saitama-shi JP for micron technology, inc.
IPC Code(s): G11C11/4091
CPC Code(s): G11C11/4091
Abstract: apparatuses and systems including sense amplifiers are disclosed. an apparatus may include a first pull-up sense amplifier, a first pull-down sense amplifier, and a first pair of lines electrically connecting the first pull-up sense amplifier to the first pull-down sense amplifier. the apparatus may further include a second pull-up sense amplifier, a second pull-down sense amplifier, and a second pair of lines including one or more wiring twists and electrically connecting the second pull-up sense amplifier to the second pull-down sense amplifier.
Inventor(s): Lawrence Celso Miranda of San Jose CA US for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA US for micron technology, inc., Sheyang Ning of San Jose CA US for micron technology, inc., Jeffrey S. McNeil of Nampa ID US for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08, G11C16/24, G11C16/26
CPC Code(s): G11C16/10
Abstract: an example memory device includes: a memory array; and a controller coupled to the memory array, the controller to perform the following operations: identifying a set of memory cells for performing a memory programming operation, such that the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, such that the first voltage is incremented every time period over a sequence of time periods; causing a second voltage to be applied to a first bitline, such that the second voltage is incremented during a first time period of the sequence of time periods; and causing a third voltage to be applied to a second bitline, such that the third voltage is incremented during a second time period of the sequence of time periods.
Inventor(s): Vinh Q. Diep of Hayward CA US for micron technology, inc., Yingda Dong of Los Altos CA US for micron technology, inc., Ching-Huang Lu of Fremont CA US for micron technology, inc.
IPC Code(s): G11C16/12, G11C16/08, G11C16/28, G11C16/30
CPC Code(s): G11C16/12
Abstract: control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.
Inventor(s): Anjana Karthik Gudipati of Munich DE for micron technology, inc.
IPC Code(s): G11C17/18, G11C17/16, G11C29/02
CPC Code(s): G11C17/18
Abstract: methods, systems, and devices for voltage regulation for memory array test procedures are described. a system may utilize multiple voltage regulators to concurrently activate sets of antifuses and to compensate for voltage drops across the antifuses. each voltage regulator may be associated with a respective region of memory cells. the memory system may apply an activation voltage to antifuse circuitry of a memory array. respective voltage regulators for each region of memory cells may maintain the activation voltage across respective sets of antifuses of the antifuse circuitry, such that the activation voltage exceeds a respective threshold for each antifuse. each antifuse of the respective sets of antifuses may be activated based on maintain the activation voltage using the multiple voltage regulators. the set of antifuses may transition from a resistive state to a conductive state based on activating the set of antifuses.
Inventor(s): Sai Krishna Mylavarapu of Folsom CA US for micron technology, inc., Shivasankar Gunasekaran of Erie CO US for micron technology, inc., Ameen D. Akel of Rancho Cordova CA US for micron technology, inc., Brent Keeth of Boise ID US for micron technology, inc., Lance P. Johnson of Saint Paul MN US for micron technology, inc., Amy Rae Griffin of Boise ID US for micron technology, inc.
IPC Code(s): G11C29/00, G11C29/52
CPC Code(s): G11C29/76
Abstract: methods, systems, and devices for sparing techniques in stacked memory architectures are described. a memory system may implement a stacked memory architecture that includes a set of array dies stacked along a direction and a logic die coupled with the set of array dies. each array die may include one or more memory arrays accessible using one or more first interface blocks of the array die. to support sparing, the memory system may remap access from one or more first memory arrays of the set of array dies to one or more second memory arrays of the set of array dies. logic circuitry of the logic die may be operable to perform the remapping in accordance with one or more levels of granularity, such as at a die level, channel level, pseudo-channel level, bank level, or a combination thereof.
Inventor(s): Nagasubramaniyan Chandrasekaran of Eagle ID US for micron technology, inc.
IPC Code(s): H01L21/67, G01N21/95, H01L21/66, H01L21/673, H01L21/677, H01L21/687
CPC Code(s): H01L21/67288
Abstract: a wafer storage device may include one or more mutually aligned rails extending from two opposing side walls, each pair of mutually aligned rails configured to support a wafer between the side walls. the wafer storage device includes one or more sensors coupled to at least some of the one or more rails. the one or more sensors may be configured to detect a physical property of the wafer. the wafer storage device may further include a processor configured to analyze data from the one or more sensors, and a memory device. the memory device may be configured to store data produced by at least the one or more sensors or the processor. the wafer storage device may also include a power storage device configured to receive power from an external source and supply power to the one or more sensors and the processor.
Inventor(s): Kunal R. Parekh of Boise ID US for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532, H10B41/27, H10B43/27
CPC Code(s): H01L21/76877
Abstract: a method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. an isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. the exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. conductive contact structures are formed within the extended openings. conductive pad structures are formed on the conductive contact structures. additional methods, microelectronic devices, memory devices, and electronic systems are also described.
Inventor(s): Haruka Momota of Sagamihara JP for micron technology, inc., Koji Yasumori of Machida JP for micron technology, inc., Keizo Kawakita of Higashihiroshima JP for micron technology, inc.
IPC Code(s): H01L21/66, H01L21/768, H01L23/525, H01L23/528, H10B12/00
CPC Code(s): H01L22/32
Abstract: an apparatus includes an active region; a scribe region surrounding the active region; a test component in the scribe region; a pad electrode in the active region; and a power supply wiring of an upper wiring layer in the active region, the power supply wiring extending between the test component and the pad electrode; and an interconnection structure coupling the test component and the pad electrode across a border between the active region and the scribe region, the interconnection structure including a wiring portion of a lower wiring layer crossing the power supply wiring.
Inventor(s): Faxing Che of Singapore SG for micron technology, inc., Amirul Afiq Bin Hud of Singapore SG for micron technology, inc., Darren Tan Hong Suang of Singapore SG for micron technology, inc., Hong Wang Ng of Singapore SG for micron technology, inc., Soon Sing Ng of Singapore SG for micron technology, inc., Chin Hui Chong of Singapore SG for micron technology, inc.
IPC Code(s): H01L23/498, H01L21/48, H01L21/66, H01L23/00, H01L23/552, H01L25/00, H01L25/065
CPC Code(s): H01L23/49811
Abstract: a semiconductor device assembly is provided. the assembly includes a substrate and a semiconductor device. the substrate includes a first conductive layer, the first conductive layer having a first trace with a first exposed pad and a second trace with a second exposed pad. a wire bond runs above the first conductive layer to connect the first exposed pad to the second exposed pad, such that the first trace and the second trace are only connected via the wire bond. the semiconductor device includes an electrical connection to the first trace.
Inventor(s): Po Chien Li of Taichung TW for micron technology, inc., Yu Kai Kuo of Taichung TW for micron technology, inc., Yi Wen Chen of Taichung TW for micron technology, inc., Ming Wei Tsai of Taichung TW for micron technology, inc., Chien Nan Fan of Taichung TW for micron technology, inc., Chun Ming Huang of Taichung TW for micron technology, inc., Angelo Oria Espina of Catarman PH for micron technology, inc., Chun Jen Chang of Taichung TW for micron technology, inc.
IPC Code(s): H01L23/544, H01L21/66, H01L23/00, H01L25/065, H10B80/00
CPC Code(s): H01L23/544
Abstract: methods, systems, and devices for top die back-side marking for memory systems are described. one or more alignment marks may be added to the back-side of a top memory die in a multi-layer memory device and used to align a position of the top memory die relative to a position of a memory die below the top memory die. the alignment marks may be formed on the top memory die during the manufacturing process of the multi-layer memory device. operations for forming the alignment marks are described using various semiconductor fabrication techniques. operations are also disclosed for using the alignment marks to modify placement of the top memory die to reduce the alignment offset in the manufacturing process of subsequent memory dies.
Inventor(s): Owen R. Fay of Meridian ID US for micron technology, inc., Chan H. Yoo of Boise ID US for micron technology, inc.
IPC Code(s): H01L25/18, H01L23/00, H01L23/48, H01L25/00, H01L25/16
CPC Code(s): H01L25/18
Abstract: an interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. memory interface circuitry may also be located under one or more locations on the interposer for memory devices. microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
Inventor(s): Tony M. Brewer of Plano TX US for micron technology, inc.
IPC Code(s): H01L25/18, G06F11/16, G06F11/20, G11C29/00, G11C29/14, G11C29/44, H01L23/48, H01L23/522, H01L25/00, H01L25/065, H10D84/90, H10D88/00
CPC Code(s): H01L25/18
Abstract: a three-dimensional stacked integrated circuit (3d sic) that can have at least a first 3d xpoint (3dxp) die and, in some examples, can have at least a second 3dxp die too. in such examples, the first 3dxp die and the second 3dxp die can be stacked. the 3d sic can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. in such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.
20250150094. DATA ENCODING AND DECODING SCHEMES_simplified_abstract_(micron technology, inc.)
Inventor(s): Xiangyu Tang of San Jose CA US for micron technology, inc., Eyal En Gad of Highland CA US for micron technology, inc., Huai-Yuan Tseng of San Ramon CA US for micron technology, inc.
IPC Code(s): H03M7/30, G06F7/74
CPC Code(s): H03M7/6011
Abstract: a method includes receiving user data having a number of first bits. the method further includes encoding the user data by generating a number of second encoded bits having a first quantity of bits greater than that of the number of first bits. the number of second encoded bits can include one or more bits having a particular binary value and a quantity of the one or more bits is less than a threshold quantity. the method further includes writing the number of second encoded bits as the user data to a memory.
Inventor(s): Jonathan D. Harms of Boise ID US for micron technology, inc.
IPC Code(s): H04L9/32, G06Q20/06, G06Q20/38, H04L9/00
CPC Code(s): H04L9/3218
Abstract: computerized apparatus using characterized devices such as memories for intensive computational applications such as blockchain processing. in one embodiment, the computerized apparatus comprises a computational appliance (e.g., stand-alone box, server blade, plug-in card, or mobile device) that includes characterized memory devices. these memory devices are associated with a range of performances over a range of operational parameters, and can be used in conjunction with a solution density function to optimize memory searching. in one embodiment, the ledger appliance can communicate with other ledger appliances to create and/or use a blockchain ledger so as to facilitate decentralized exchanges between untrusted parties. in some variants, the ledger appliance may additionally use an application programming interface (api) to dynamically generate blockchains on the fly. various other applications are also described (e.g., social media, machine learning, probabilistic applications and other error-tolerant applications).
Inventor(s): Luca Bert of Bologna (BO) IT for micron technology, inc.
IPC Code(s): H04L49/00, H04L49/103, H04L49/90, H04L67/1097
CPC Code(s): H04L49/3036
Abstract: a memory sub-system connectable to a microprocessor to provide network storage services. the memory sub-system has a random-access memory configured with: first queues for the microprocessor and a network interface; second queues for the microprocessor and a processing device; and third queues for the processing device and a storage device. the processing device is configured to: generate first control messages and first data messages from packets received by the network interface; place the first control messages into the first queues for the microprocessor; and place the first data messages into the third queues for the storage device. the microprocessor processes the first control messages to implement security and administrative functions and place second control messages in the second queues. the storage device is configured to retrieve the first data messages from the third queues and second control messages from the second queues for processing.
Inventor(s): Ping Kao of Taichung City TW for micron technology, inc., Soichi Sugiura of Boise ID US for micron technology, inc., Yoshihiro Matsumoto of Sagamihara JP for micron technology, inc., Cheng En Lue of Sagamihara JP for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/485
Abstract: a microelectronic device includes a semiconductor base structure, word lines, digit line contacts, digit lines, and storage node contacts. the semiconductor base structure includes pillar structures horizontally separated from one another by filled isolation trenches. the word lines horizontally extend through the pillar structures and the filled isolation trenches in a first direction. the digit line contacts include conductively doped semiconductor material vertically extending into digit line contact sections of the pillar structures. the digit lines are over and in contact with the digit line contacts and horizontally extend in a second direction orthogonal to the first direction. the digit lines have a different material composition than the digit line contacts. the storage node contacts include additional conductively doped semiconductor material vertically extending into storage node contact sections of the pillar structures. methods, memory devices, and electronic systems are also described.
Inventor(s): Hong Li of Boise ID US for micron technology, inc., Ramaswamy Ishwar Venkatanarayanan of Garden City ID US for micron technology, inc., Sanh D. Tang of Kuna ID US for micron technology, inc., Erica L. Poelstra of Boise ID US for micron technology, inc.
IPC Code(s): H10B12/00, G11C11/402, H01L23/49, H01L23/538, H10D30/01, H10D30/63
CPC Code(s): H10B12/488
Abstract: some embodiments include a method of forming an integrated assembly. a structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. each of the rails includes pillars of semiconductor material. the rails have sidewall surfaces along spaces between the rails. the pillars have upper segments, middle segments and lower segments. first-material liners are formed along the sidewall surfaces of the rails. a second material is formed over the liners. first sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. second sections of the liners remain under the gaps. conductive material is formed within the gaps. the conductive material is configured as conductive lines which are along the middle segments of the pillars.
Inventor(s): Hongbin Zhu of Boise ID US for micron technology, inc., Gurtej S. Sandhu of Boise ID US for micron technology, inc., Kunal R. Parekh of Boise ID US for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/30, H10B43/30, H10B43/35, H10B43/40, H10B99/00
CPC Code(s): H10B43/27
Abstract: a method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. a first material is formed within the first and second lower openings. an upper material is formed above the lower material and above the first material in the first and second lower openings. a first upper opening is formed through the upper material to the first material in the first lower opening. at least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. after forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. conductive material of the conductive via is formed within the second upper opening. structure embodiments independent of method of formation are disclosed.
Inventor(s): Haitao Liu of Boise ID US for micron technology, inc., Kamal M. Karda of Boise ID US for micron technology, inc., Albert Fayrushin of Boise ID US for micron technology, inc., Yingda Dong of Los Altos CA US for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10D30/68, H10D30/69, H10D64/01
CPC Code(s): H10B43/27
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.
Inventor(s): Pei Qiong Cheung of Singapore SG for micron technology, inc., Zhixin Xu of Singapore SG for micron technology, inc., Yuan Fang of Singapore SG for micron technology, inc.
IPC Code(s): H10B43/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: some embodiments include a method of forming an assembly. a first stack of alternating first and second tiers is formed over a conductive structure. a first opening is formed to extend through the first stack. a sidewall of the first opening is lined with a first liner material. the first liner material is converted to a first charge-blocking material. sacrificial material is formed within the first opening. a second stack of alternating third and fourth tiers is formed over the first stack. a second opening is formed to extend through the second stack to the sacrificial material. a second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. the sacrificial material is removed. charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. some embodiments include integrated assemblies.
[[20250151284. Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor_simplified_abstract_(micron technology, inc.)]]
Inventor(s): Durai Vishak Nirmal Ramaswamy of Boise ID US for micron technology, inc.
IPC Code(s): H10B53/20, H01L21/02, H01L21/311, H01L21/768, H01L23/528, H10B12/00, H10B41/27, H10B41/35, H10B41/41, H10B43/27, H10B43/35, H10B51/10, H10B51/20, H10B51/30, H10B53/10, H10B53/30, H10D1/68, H10D62/13, H10D62/17, H10D88/00
CPC Code(s): H10B53/20
Abstract: a memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. at least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. a capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. the first electrode is electrically coupled to the first source/drain region. a horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. a capacitor-electrode structure extends elevationally through the vertically-alternating tiers. individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. an access-line pillar extends elevationally through the vertically-alternating tiers. the gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. other embodiments, including method, are disclosed.
Micron Technology, Inc. patent applications on May 8th, 2025
- Micron Technology, Inc.
- G06F3/06
- G06F13/16
- G06F13/40
- G06F13/42
- G11C7/10
- G11C21/00
- CPC G06F3/0607
- Micron technology, inc.
- CPC G06F3/0613
- G06F1/324
- CPC G06F3/0625
- CPC G06F3/064
- G06F11/10
- G06F11/14
- G11C29/52
- CPC G06F3/0647
- CPC G06F3/0656
- G06F12/02
- CPC G06F3/0659
- G06F11/08
- G06F3/14
- G06T3/40
- G06T11/60
- CPC G06F3/1454
- G06F9/54
- CPC G06F9/546
- G06F11/07
- CPC G06F11/0754
- CPC G06F11/1004
- CPC G06F11/1048
- CPC G06F11/108
- G06F11/30
- G11C5/14
- CPC G06F11/3058
- G06F12/06
- G06F12/0864
- G06F12/0893
- CPC G06F12/0207
- G06F12/1009
- CPC G06F12/1009
- G06F12/1027
- G06N5/043
- G06N5/045
- H04L67/1097
- H04L67/568
- H04W8/26
- G06F21/62
- CPC G06F21/629
- G06F21/79
- G06F21/10
- G06F21/55
- G06F21/60
- G11C11/22
- CPC G06F21/79
- G06F30/333
- G06F30/392
- CPC G06F30/333
- G06N3/063
- G06F9/30
- G06F9/50
- G06F17/16
- G06F30/27
- G06N3/08
- CPC G06N3/063
- G06N5/022
- H04L9/40
- CPC G06N5/022
- G07C5/08
- B60W50/02
- G07C5/00
- CPC G07C5/085
- G11C5/06
- C23C8/06
- C23C8/36
- C23C28/00
- H10B41/27
- H10B41/35
- H10B41/41
- H10B43/27
- H10B43/35
- H10B43/40
- CPC G11C5/063
- G11C8/12
- G11C11/56
- G11C16/08
- G11C19/32
- CPC G11C7/1006
- G11C11/4074
- G11C11/4076
- G11C11/4096
- G11C29/42
- CPC G11C11/4074
- G11C11/4091
- CPC G11C11/4091
- G11C16/10
- G11C16/04
- G11C16/24
- G11C16/26
- CPC G11C16/10
- G11C16/12
- G11C16/28
- G11C16/30
- CPC G11C16/12
- G11C17/18
- G11C17/16
- G11C29/02
- CPC G11C17/18
- G11C29/00
- CPC G11C29/76
- H01L21/67
- G01N21/95
- H01L21/66
- H01L21/673
- H01L21/677
- H01L21/687
- CPC H01L21/67288
- H01L21/768
- H01L23/522
- H01L23/532
- CPC H01L21/76877
- H01L23/525
- H01L23/528
- H10B12/00
- CPC H01L22/32
- H01L23/498
- H01L21/48
- H01L23/00
- H01L23/552
- H01L25/00
- H01L25/065
- CPC H01L23/49811
- H01L23/544
- H10B80/00
- CPC H01L23/544
- H01L25/18
- H01L23/48
- H01L25/16
- CPC H01L25/18
- G06F11/16
- G06F11/20
- G11C29/14
- G11C29/44
- H10D84/90
- H10D88/00
- H03M7/30
- G06F7/74
- CPC H03M7/6011
- H04L9/32
- G06Q20/06
- G06Q20/38
- H04L9/00
- CPC H04L9/3218
- H04L49/00
- H04L49/103
- H04L49/90
- CPC H04L49/3036
- CPC H10B12/485
- G11C11/402
- H01L23/49
- H01L23/538
- H10D30/01
- H10D30/63
- CPC H10B12/488
- H10B41/30
- H10B43/30
- H10B99/00
- CPC H10B43/27
- H10D30/68
- H10D30/69
- H10D64/01
- H10B43/10
- H10B53/20
- H01L21/02
- H01L21/311
- H10B51/10
- H10B51/20
- H10B51/30
- H10B53/10
- H10B53/30
- H10D1/68
- H10D62/13
- H10D62/17
- CPC H10B53/20
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