Micron Technology, Inc. patent applications on March 27th, 2025
Patent Applications by Micron Technology, Inc. on March 27th, 2025
Micron Technology, Inc.: 34 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (12), G11C16/04 (4), G11C16/26 (4), G11C16/34 (4), G11C16/10 (4) G06F3/0616 (3), G06F3/0659 (2), G06F1/06 (1), G11C16/102 (1), H10D64/252 (1)
With keywords such as: memory, device, data, voltage, material, value, read, block, cells, and command in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20250103088. VOLTAGE AND CLOCK FREQUENCY MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA US for micron technology, inc., Leonid Minz of Beer Sheva IL for micron technology, inc.
IPC Code(s): G06F1/06
CPC Code(s): G06F1/06
Abstract: voltage sensing circuitry and management circuitry provide voltage and clock frequency management. the voltage sensing circuitry may be configured to detect a voltage associated with a system-on-chip (soc) and determine when the voltage transitions from a first voltage to a second voltage. the management circuitry may be configured to generate clocking signals for the soc and alter a frequency of the generated clocking signals in response to the detected voltage transition.
20250103206. BIT ERROR MANAGEMENT IN MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Jeremy BINFET of Boise ID US for micron technology, inc., Tommaso VALI of Sezze IT for micron technology, inc., Walter DI FRANCESCO of Avezzano IT for micron technology, inc., Luigi PILOLLI of L'Aquila IT for micron technology, inc., Angelo COVELLO of Avezzano IT for micron technology, inc., Andrea D'ALESSANDRO of Avezzano IT for micron technology, inc., Agostino MACEROLA of San Benedetto dei Marsi IT for micron technology, inc., Cristina LATTARO of Rieti IT for micron technology, inc., Claudia CIASCHI of Latina IT for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/061
Abstract: in some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. the memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. the memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. the memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
Inventor(s): Phong S. Nguyen of Livermore CA US for micron technology, inc., Dung Viet Nguyen of San Jose CA US for micron technology, inc., James Fitzpatrick of Laguna Niguel CA US for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0616
Abstract: described are systems and methods for adaptable data modulation. an example memory sub-system comprises a controller managing one or more memory devices. the controller is configured to perform operations, comprising: receiving a unit of data to be written to the memory device; splitting the unit of data into a plurality of segments; modulating each segment of the unit of data by a modulation operation using a modulation mask derived from a corresponding seed value; and generating a modulated unit of data comprising a plurality of modulated segments and a plurality of corresponding seed identifiers, wherein each seed identifier identifies a seed value that has been used for modulating a respective segment of the unit of data.
Inventor(s): Phong S. Nguyen of Livermore CA US for micron technology, inc., Dung Viet Nguyen of San Jose CA US for micron technology, inc., James Fitzpatrick of Laguna Niguel CA US for micron technology, inc., Steven Raymond Brown of Boise ID US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0616
Abstract: described are systems and methods for dynamically configurable data modulation in memory systems. an example memory sub-system comprises a controller managing one or more memory devices. the controller is configured to perform operations, comprising: receiving a unit of data to be stored on the memory device; identifying a set of parameter values characterizing a target location of the unit of data on the memory device; determining a modulation code corresponding to the set of parameter values; modulating the unit of data by a modulation operation identified by the modulation code; and storing, on the memory device, the modulated unit of data.
Inventor(s): Yu-Chung Lien of San Jose CA US for micron technology, inc., Ching-Huang Lu of Fremont CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc.
IPC Code(s): G06F3/06, G11C11/56, G11C16/04, G11C16/24, G11C16/26, G11C16/32, G11C16/34
CPC Code(s): G06F3/0616
Abstract: methods, systems, and apparatuses include receiving a command directed to a portion of memory. a cycle number for the portion of memory is determined. a group to which the portion of memory belongs is determined. a bitline voltage is determined using the cycle number and the group. the command is executed using the bitline voltage.
Inventor(s): Mustafa N. Kaynak of San Diego CA US for micron technology, inc., Patrick R. Khayat of San Diego CA US for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA US for micron technology, inc.
IPC Code(s): G06F3/06, G11C16/04, G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G06F3/0619
Abstract: a system comprising a memory device comprising a plurality of memory cells and a processing device, operatively coupled with the memory device, to perform operations. the processing device determines, for each memory cell of the plurality of memory cells, a respective value of a metric that reflects a sensitivity of a threshold voltage of the memory cell to a change in an adjacent memory cell. the processing device determines, for each wordline of a plurality of wordlines of the memory device, based on the determined values of the metric, a respective aggregate measure of adjacent cell dependence. the processing device categorizes the wordlines into one or more wordline groups based on comparing, for each wordline, the determined aggregate measure of adjacent cell dependence to at least one threshold dependence value.
Inventor(s): Yoshio Mizukane of Sagamihara JP for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: memory devices receive refresh management (rfm) commands and perform a targeted refresh operation responsive to the rfm command. certain conflicts may occur if the rfm command is received while the memory is performing certain operations. an rfm entry circuit receives the rfm command at a first time and then provides an internal rfm signal at a second time. the second time may be the next time a row activation or refresh is performed after receiving the rfm command. the targeted refresh operation is performed responsive to the internal rfm signal.
Inventor(s): Dung Viet Nguyen of San Jose CA US for micron technology, inc., Phong S. Nguyen of Livermore CA US for micron technology, inc., James Fitzpatrick of Laguna Niguel CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0644
Abstract: host data to be programmed to a plurality of memory cells associated with a wordline of a memory device is received from a host system. the host data into a plurality of partitions is divided. each of the plurality of partitions is divided into a respective plurality of sub-partitions. one or more modulation mappings to be applied to the plurality of sub-partitions are determined based on the host data of the plurality of partitions. host data of each sub-partition of the plurality of sub-partitions is modified based on the one or more modulation mappings. the modified host data of each sub-partition is written to the plurality of memory cells associated with the wordline.
Inventor(s): Phong S. Nguyen of Livermore CA US for micron technology, inc., Dung Viet Nguyen of San Jose CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: described are systems and methods for selecting a modulation code permutation for data modulation in a memory system. an example memory sub-system comprises a controller managing one or more memory devices. the controller is configured to perform operations including: receiving data to be written to the memory device; selecting, from a set of modulation code permutations for modifying data to be written to the memory device, a modulation code permutation; determining that a cost metric value corresponding to storing data modified by the modulation code permutation on the memory device satisfies a target condition; generating, using the modulation code permutation, modulated data from the data to be written; and storing, on the memory device, the modulated data.
20250103245. ADDRESS VERIFICATION AT A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Stephen Hanna of Fort Collins CO US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for address verification at a memory system are described. a memory system may determine an address identifier based on a received read command and maintain the determined address identifier in a protected state to validate a subsequent read operation. for example, the memory system may store the determined address identifier in a first memory array, separate from a second memory array that is read from in response to the read command. the memory system may also extract an address identifier from memory cells being read in response to the read command, which may include decoding or other interpreting operations performed on information read from the memory cells. the address identifier extracted from the memory cells may be compared with the address identifier determined from the read command and maintained in the protected state, which may support a determination of how to respond to the read command.
20250103246. MEMORY SUB-SYSTEM MEDIA MANAGEMENT GROUPS_simplified_abstract_(micron technology, inc.)
Inventor(s): Karl D. Schuh of Santa Cruz CA US for micron technology, inc., Jiangang Wu of Milpitas CA US for micron technology, inc., Kishore K. Muchherla of Fremont CA US for micron technology, inc., Ashutosh Malshe of Fremont CA US for micron technology, inc., Vamsi Pavan Rayaprolu of San Jose CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a system includes a memory device and a processing device coupled to the memory device. the processing device can assign each of a plurality of superblocks to one of a plurality of groups. the processing device can monitor an order that each of the groups have been written to. the processing device can write data to a first block of a first superblock of a first of the plurality of groups.
Inventor(s): Yu-Chung LIEN of San Jose CA US for micron technology, inc., Ching-Huang LU of Fremont CA US for micron technology, inc., Zhenming ZHOU of San Jose CA US for micron technology, inc., Jun WAN of San Jose CA US for micron technology, inc.
IPC Code(s): G06F11/00
CPC Code(s): G06F11/008
Abstract: in some implementations, a memory device may receive a program command instructing the memory device to program host data to a word line associated with a memory. the memory device may determine a program erase cycle (pec) count associated with the word line. the memory device may determine, based on the pec count, a selected program scheme to be used to program the host data to the word line, wherein the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme. the memory device may execute the program command by performing the selected program scheme.
Inventor(s): Debra M. Bell of Boise ID US for micron technology, inc., Kristen M. Hopper of Boise ID US for micron technology, inc., Erika Prosser of Boise ID US for micron technology, inc., Aaron P. Boehm of Boise ID US for micron technology, inc.
IPC Code(s): G06F11/07, G06F1/20, G06F1/30, G06F3/06, G06F11/30
CPC Code(s): G06F11/0766
Abstract: methods, systems, and devices for persistent health monitoring for volatile memory devices are described. a memory device may determine that an operating condition associated with an array of memory cells on the device, such as a temperature, current, voltage, or other metric of health status is outside of a range associated with a risk of device degradation. the memory device may monitor a duration over which the operating condition is outside of the range, and may determine whether the duration satisfies a threshold. in some cases, the memory device may store an indication of when (e.g., each time) the duration satisfied the threshold. the memory device may store the one or more indications in one or more non-volatile storage elements, such as fuses, which may enable the memory device to maintain a persistent indication of a cumulative duration over which the memory device is operated with operating conditions outside of the range.
Inventor(s): Andreas Schneider of Gernlinden DE for micron technology, inc., Andrea Sorrentino of München DE for micron technology, inc., Peter Mayer of Neubiberg DE for micron technology, inc., Rethin Raj of Augsburg DE for micron technology, inc., Ankur Gupta of München DE for micron technology, inc., Marcos Alvarez Gonzalez of München DE for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: methods, systems, and devices for cyclic redundancy check (crc) comparison for error detection are described. a host system may determine an error cause associated with writing data to or reading data from a memory system. for writing data, the host system may transmit data and a crc value to the memory system. the memory system may calculate another crc value and indicate an error and the calculated crc value based on the received and calculated crc values being different. the host system may compare the calculated crc value and the originally transmitted crc value to determine an error cause. for reading data, the host system may receive data and an associated crc value from the memory system, calculate a crc value using the received data, and determine an error cause based on a comparison of the received crc value, the calculated crc, and an expected crc value.
20250103434. TECHNIQUES FOR MEMORY ERROR CORRECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Kai Wang of Shanghai CN for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1096
Abstract: methods, systems, and devices for techniques for memory error correction are described. a memory device may operate cycles associated with refresh operations and cycles associated with refresh with error correction (ecc) operations independently. for example, the memory device may include an ecc patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. additionally, the memory device may include a refresh counter which indicates a row on which to perform a refresh operation. in response to receiving a command of a first, the memory device may modify the error correction counter and maintain the refresh counter. alternatively, in response to receiving a command of a second, the memory device may modify the refresh counter and maintain the error correction counter.
Inventor(s): Minjian Wu of Shanghai CN for micron technology, inc.
IPC Code(s): G06F12/06, G06F9/4401
CPC Code(s): G06F12/0638
Abstract: the present disclosure includes apparatuses, methods, and systems for receiving executable instructions from volatile memory. in an example, a method can include storing executable instructions comprising a bootloader at a pre-defined memory address range in a non-volatile memory device of a solid state drive (ssd), copying the executable instructions from the pre-defined memory address range to a volatile memory device of the ssd in response to powering on the ssd, and transmitting the executable instructions from the volatile memory device to a host.
Inventor(s): Sourin SARKAR of Bangalore IN for micron technology, inc., Kiran K. GUNNAM of Cedar Park TX US for micron technology, inc., Chittoor Ranganathan PARTHASARATHY of Hyderabad IN for micron technology, inc.
IPC Code(s): G06F21/55, G06F21/60, G06F21/78
CPC Code(s): G06F21/554
Abstract: in some implementations, a memory device may include one or more components. the one or more components may be configured to identify an operation to access content stored in a memory of the memory device, wherein the operation is associated with a user profile. the one or more components may be configured to flag a user, associated with the user profile, as being potentially malicious based on the operation conflicting with a past content access pattern associated with the user profile. the one or more components may be configured to lock the memory based on the user being flagged.
20250103788. TOPOLOGICAL SIMULATION OF LAYOUT DESIGN_simplified_abstract_(micron technology, inc.)
Inventor(s): Yorio Takada of Tokyo JP for micron technology, inc.
IPC Code(s): G06F30/398, G06F30/392
CPC Code(s): G06F30/398
Abstract: apparatuses, computer implemented methods and non-transitory computer-readable media storing instructions to implement simulating topological features of layout designs are disclosed. an example method includes: receiving information about the layout design including topological parameters in a verification area; defining a width and a length in first and second direction directions of one or more windows; defining first and second step sizes independently from the width and the length in the first and second directions for the one or more windows, the first step size being a distance between adjacent central points of the one or more windows in the first direction and the second step size being a distance between adjacent central points of the one or more windows in the second direction; extracting information about the layout design in the one or more windows at each of a plurality of window locations; and storing the information in a database.
Inventor(s): Sean S. Eilert of Penryn CA US for micron technology, inc., Glen E. Hush of Boise ID US for micron technology, inc., Aliasger T. Zaidy of Seattle WA US for micron technology, inc., Kunal R. Parekh of Boise ID US for micron technology, inc.
IPC Code(s): G11C11/4093, G06F3/06, G06F13/16, G06F13/28, G11C7/08, G11C7/10, G11C11/408, G11C11/4091, G11C11/4096, G16B30/00, G16B50/10, H01L21/66, H01L21/78, H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): G11C11/4093
Abstract: a memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. a controller of the memory device that is coupled to the memory die can activate a row of the memory die. responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. a transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.
Inventor(s): Alyssa N. Scarbrough of Boise ID US for micron technology, inc., John D. Hopkins of Meridian ID US for micron technology, inc., Jordan D. Greenlee of Boise ID US for micron technology, inc.
IPC Code(s): G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): G11C16/0483
Abstract: a memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. the channel-material strings directly electrically couple to conductor material of the conductor tier. the insulative tier immediately-above a lowest of the conductive tiers comprises a lower first insulating material and an upper second insulating material above the upper first insulating material. the upper second insulating material is of different composition from that of the lower first insulating material. intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. other embodiments, including method, are disclosed.
20250104772. MEMORY CELL VOLTAGE LEVEL SELECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Tingjun Xie of Milpitas CA US for micron technology, inc., Murong Lang of San Jose CA US for micron technology, inc., Fangfang Zhu of Boise ID US for micron technology, inc., Jiangli Zhu of San Jose CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/26, G11C16/32
CPC Code(s): G11C16/102
Abstract: a method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (qlc) memory block, determining the time period exceeds a threshold time, designating the qlc memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the qlc memory block, and setting a read threshold level of at least a portion of the qlc memory block at the voltage threshold level of the last successful read operation.
Inventor(s): Yu-Chung Lien of San Jose CA US for micron technology, inc., Ting Luo of Santa Clara CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/04, G11C16/08, G11C16/10, G11C16/34
CPC Code(s): G11C16/26
Abstract: methods, systems, and devices for a ganged read operation for multiple sub-blocks are described. the method may include writing a respective first logic state to each memory cell of a set of memory portions and biasing a first word line and a second word line to a first voltage. in some examples, the first word line may correspond to a first memory portion and the second word line may correspond to a second memory portion. further, the method may include applying a first read pulse to the first word line and a second read pulse to the second word line and reading a second logic state from one or more memory cells of the first memory portion and the second memory portion. further, the method may include validating the write operation based on reading the second logic state from the memory cells of the first memory portion and the second memory portion.
Inventor(s): Violante Moschiano of Avezzano IT for micron technology, inc., Shyam Sunder Raghunathan of Singapore SG for micron technology, inc., Walter Di Francesco of Avezzano IT for micron technology, inc.
IPC Code(s): G11C16/32, G11C16/08, G11C16/10
CPC Code(s): G11C16/32
Abstract: a memory device includes an array of memory cells associated with multiple wordlines and control logic operatively coupled with the array. the control logic, in performing a read operation, can determine a length of time that a selected wordline, of the multiple wordlines, takes to reach a pass voltage for reading data from a memory cell associated with the selected wordline. the control logic can select a delay time based on whether the length of time is associated with a transient state or a non-transient state. the control logic can read the data from the memory cell associated with the selected wordline after the selected delay time.
Inventor(s): Zhongguang Xu of San Jose CA US for micron technology, inc., Hanping Chen of San Jose CA US for micron technology, inc., Peng Zhang of Los Altos CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc.
IPC Code(s): G11C29/12
CPC Code(s): G11C29/12005
Abstract: a processing device in a memory sub-system performs a first data integrity scan on a block of a memory device to determine a first combined reliability statistic of memory cells in the block associated with a first program level and a second program level, and performs, using a predetermined read level offset corresponding to one of the first program level or the second program level, a second data integrity scan on the block of the memory device to determine a second combined reliability statistic of the memory cells in the block associated with the first program level and the second program level. the processing device determines a difference between the first combined reliability statistic and the second combined reliability statistic and, responsive to the difference between the first combined reliability statistic and the second combined reliability statistic satisfying a threshold criterion, performs a corrective action on the block of the memory device.
20250104792. APPARATUS INCLUDING BTI CONTROLLER_simplified_abstract_(micron technology, inc.)
Inventor(s): YASUSHI MATSUBARA of Isehara JP for micron technology, inc., YOSHINORI FUJIWARA of Boise ID US for micron technology, inc., TAKUYA TAMANO of Boise ID US for micron technology, inc.
IPC Code(s): G11C29/18, G11C29/12
CPC Code(s): G11C29/18
Abstract: according to one or more embodiments of the disclosure, an apparatus comprises a memory device and a bias temperature instability (bti) controller. the bti controller generates and outputs a command and address signal for memory testing. the command and address signal causes the memory device in the idle state to operate for the testing.
20250104794. SCAN-BASED VOLTAGE FREQUENCY SCALING_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA US for micron technology, inc., Leonid Minz of Beer Sheva IL for micron technology, inc., Yoav Weinberg of North York CA for micron technology, inc.
IPC Code(s): G11C29/50, G11C29/02
CPC Code(s): G11C29/50004
Abstract: an example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (soc) at a plurality of respective voltage values. the example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. the entered data is associated with the respective plurality of voltage value. the example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the soc reaches a threshold. the example method can include indicating the determined particular voltage in the database. the indicated determined particular voltage in the database can be used for performing one or more operations using the soc.
Inventor(s): Jun Wan of San Jose CA US for micron technology, inc., Yu-Chung Lien of San Jose CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc.
IPC Code(s): G11C29/52, G11C16/34
CPC Code(s): G11C29/52
Abstract: devices, methods, and systems for performing corrective sense operations in memory are described herein. an example apparatus includes a memory component including a plurality of groups of memory cells, and a processing device coupled to the memory component and configured to perform a sense operation on the plurality of groups of memory cells, perform a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value, and perform the corrective sense operation on a second one of the plurality of groups of memory cells using the corrective value.
20250104799. MIXED-MODE VIRTUAL BLOCK GENERATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Guang Hu of Mountain View CA US for micron technology, inc., Xiangang Luo of Fremont CA US for micron technology, inc., Jianmin Huang of San Carlos CA US for micron technology, inc.
IPC Code(s): G11C29/00
CPC Code(s): G11C29/886
Abstract: aspects of the present disclosure configure a memory sub-system controller to generate virtual blocks using partial good blocks or portions of full blocks. the controller identifies a region of a set of memory components comprising a plurality of planes across a plurality of decks. the controller determines that a first memory block within a first deck associated with a first plane of the plurality of planes is a first partial good block (pgb), the first pgb including a portions categorized as being defective and portions categorized as being non-defective. the controller determines that a second memory block associated with a second plane is a full block (fb), the fb being categorized as non-defective. the controller generates a virtual block using the first pgb of the first memory block associated with the first plane and a portion of the fb of the second memory block associated with the second plane.
20250105829. CURRENT AND CLOCK FREQUENCY MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA US for micron technology, inc., Leonid Minz of Beer Sheva IL for micron technology, inc., Ekram H. Bhuiyan of Sunnyvale CA US for micron technology, inc.
IPC Code(s): H03K5/00, G01R15/18, G01R19/00, G05F1/56
CPC Code(s): H03K5/00006
Abstract: current sensing circuitry and clock management circuitry provide current and clock frequency management. in one example, an apparatus can include a voltage regulator, current sensing circuitry configured to: detect a current associated with the voltage regulator of a system-on-chip (soc), and determine when the current transitions from a first current to a second current; and clock management circuitry configured to: generate clocking signals for the soc, select a gradient frequency alteration based on the detected current, and alter a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition.
Inventor(s): Sourin SARKAR of Bangalore IN for micron technology, inc., Vamshikrishna KOMURAVELLI of Rangareddy IN for micron technology, inc.
IPC Code(s): H04L9/08, H04L9/32
CPC Code(s): H04L9/0866
Abstract: in some implementations, a memory device may generate a physical unclonable function (puf) value. the memory device may access a puf protection key stored in a non-host-addressable memory region. the memory device may encrypt the puf value, using the puf protection key, to generate an encrypted puf value. the memory device may store the encrypted puf value in scattered memory locations in the non-host-addressable memory region.
Inventor(s): Yiping Wang of Boise ID US for micron technology, inc., Andrew Li of Boise ID US for micron technology, inc., Haoyu Li of Boise ID US for micron technology, inc., Matthew J. King of Boise ID US for micron technology, inc., Wei Yeeng Ng of Boise ID US for micron technology, inc., Yongjun Jeff Hu of Boise ID US for micron technology, inc.
IPC Code(s): H10B43/27, H01L21/283, H01L21/306, H10B41/27, H10B41/35, H10B43/35
CPC Code(s): H10B43/27
Abstract: some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. the first structure has a composition along an interface with the second structure. the composition includes additive to a concentration within a range of from about 10atoms/cmto about 10atoms/cm. the additive includes one or more of carbon, oxygen, nitrogen and sulfur. some embodiments include methods of forming integrated assemblies.
Inventor(s): Paolo Fantini of Vimercate IT for micron technology, inc., Fabio Pellizzer of Boise ID US for micron technology, inc., Lorenzo Fratin of Buccinasco (MI) IT for micron technology, inc.
IPC Code(s): H10B63/00, G11C13/00, H10B20/00, H10N70/00
CPC Code(s): H10B63/84
Abstract: methods, systems, and devices for split pillar architectures for memory devices are described. a memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. after etching material, an insulative material may be deposited in a trench. portions of the insulative material may be removed to form openings, into which cell material is deposited. conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. the conductive pillars may be divided to form first and second pillars.
Inventor(s): Lifang Xu of Boise ID US for micron technology, inc., Richard J. Hill of Boise ID US for micron technology, inc., Indra V. Chary of Boise ID US for micron technology, inc., Lars P. Heineck of Boise ID US for micron technology, inc.
IPC Code(s): H01L29/417, H01L21/768, H01L23/528, H01L29/40
CPC Code(s): H10D64/252
Abstract: microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. a first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. a second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. the first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. the trench extends a width of the first and second series of stadiums. the stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.
Inventor(s): Giulio Albini of Draper UT US for micron technology, inc.
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
CPC Code(s): H10N70/826
Abstract: methods, systems, and devices for low resistance via contacts in a memory device are described. a via may be formed so as to protrude from a surrounding material. a barrier material may be formed above an array area and also above the via. after a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. the planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. the first layer of the access line material may protect the unremoved barrier material during the planarization process. a second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.
Micron Technology, Inc. patent applications on March 27th, 2025
- Micron Technology, Inc.
- G06F1/06
- CPC G06F1/06
- Micron technology, inc.
- G06F3/06
- CPC G06F3/061
- CPC G06F3/0616
- G11C11/56
- G11C16/04
- G11C16/24
- G11C16/26
- G11C16/32
- G11C16/34
- G11C16/10
- CPC G06F3/0619
- CPC G06F3/0632
- CPC G06F3/0644
- CPC G06F3/0655
- CPC G06F3/0659
- G06F11/00
- CPC G06F11/008
- G06F11/07
- G06F1/20
- G06F1/30
- G06F11/30
- CPC G06F11/0766
- G06F11/10
- CPC G06F11/1004
- CPC G06F11/1096
- G06F12/06
- G06F9/4401
- CPC G06F12/0638
- G06F21/55
- G06F21/60
- G06F21/78
- CPC G06F21/554
- G06F30/398
- G06F30/392
- CPC G06F30/398
- G11C11/4093
- G06F13/16
- G06F13/28
- G11C7/08
- G11C7/10
- G11C11/408
- G11C11/4091
- G11C11/4096
- G16B30/00
- G16B50/10
- H01L21/66
- H01L21/78
- H01L23/00
- H01L25/00
- H01L25/065
- H01L25/18
- CPC G11C11/4093
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- CPC G11C16/0483
- G11C16/08
- CPC G11C16/102
- CPC G11C16/26
- CPC G11C16/32
- G11C29/12
- CPC G11C29/12005
- G11C29/18
- CPC G11C29/18
- G11C29/50
- G11C29/02
- CPC G11C29/50004
- G11C29/52
- CPC G11C29/52
- G11C29/00
- CPC G11C29/886
- H03K5/00
- G01R15/18
- G01R19/00
- G05F1/56
- CPC H03K5/00006
- H04L9/08
- H04L9/32
- CPC H04L9/0866
- H01L21/283
- H01L21/306
- CPC H10B43/27
- H10B63/00
- G11C13/00
- H10B20/00
- H10N70/00
- CPC H10B63/84
- H01L29/417
- H01L21/768
- H01L23/528
- H01L29/40
- CPC H10D64/252
- H10N70/20
- CPC H10N70/826
