Micron Technology, Inc. patent applications on January 2nd, 2025
Patent Applications by Micron Technology, Inc. on January 2nd, 2025
Micron Technology, Inc.: 33 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (11), G11C7/10 (4), H01L25/18 (4), H01L25/00 (4), H01L23/00 (4) G11C11/4085 (2), G06F3/0632 (2), G06F3/0655 (2), G11C16/102 (2), G06F3/0604 (1)
With keywords such as: memory, device, die, semiconductor, data, access, devices, based, coupled, and systems in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20250004640. COMPLETION FLAG FOR MEMORY OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0604
Abstract: methods, systems, and devices for using a completion flag for memory operations are described. a completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. a controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.
Inventor(s): Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Sead Zildzic of Rancho Cordova CA (US) for micron technology, inc., Violante Moschiano of Avezzano (IT) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C16/34, G11C29/52
CPC Code(s): G06F3/0611
Abstract: a memory device includes array(s) of memory cells including first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory. page buffer(s) are coupled with the array(s). logic is coupled with the page buffer(s) and to cause, in response to receipt of a copyback clear command, a page buffer to perform a dual-strobe read operation on the first memory cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage. the logic causes the page buffer to determine a number of one bit values within a threshold voltage range between the first threshold voltage and the second threshold voltage. the logic causes, responsive to the number of one bit values not satisfying a threshold criterion, a copyback be performed of data in the first memory cells to the second memory cells.
Inventor(s): Ying Yu Tai of Mountain View CA (US) for micron technology, inc., Jun Wan of San Jose CA (US) for micron technology, inc., Seungjune Jeon of Santa Clara CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0616
Abstract: a processing device analyzes one or more property and capability characteristics of a plurality of memory devices produced in a development process executed by a memory device development system and identifies respective subsets of the plurality of memory devices having property and capability characteristics that meet respective standards associated with a plurality of different use cases. the processing device further allocates the respective subsets to groups of memory devices corresponding to the different use cases.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: a set of host data items is received for storage at a memory sub-system. each of the set of host data items is associated with a common data type. a zone group size metric associated with the common data type is identified among a set of zone group size metrics each associated with a distinct data type. the set of host data items are programmed to memory cells of a zone group having a zone group size indicated by the zone group size metric.
20250004656. DUAL-LEVEL REFRESH MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Nicola Del Gatto of Cassina de’ Pecchi (IT) for micron technology, inc., Niccolò Izzo of Vignate (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: methods, systems, and devices related to determining whether a target address of a memory array associated with an access request is stored in a cam. if the target address is stored in the cam, the cam may be updated to increment an access count of a target row corresponding to the target address. if the target row exceeds a first threshold value, rows of the memory array directly adjacent to the target row may be refreshed. if the target address is not stored in the cam, the target address may be written to the cam. the cam may be updated to increment an access count of an address of a bank including the target row corresponding to the target address.
20250004659. DATA REARRANGEMENT TECHNIQUES FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: methods, systems, and devices for techniques for coupled host and memory dies are described. a controller of a memory system may facilitate data rearrangement within a block-addressable memory device based on metadata associated with prefetching data to a byte-addressable memory device or to a host system. for example, the controller may utilize the metadata and various access commands to rearrange associated data within the block-addressable memory device such that the data is written to a singular superblock of the block-addressable memory device. in some examples, one or more counters may be utilized by the controller to determine whether to rearrange the data within the block-addressable memory device.
20250004663. TEMPERATURE-BASED READ DISTURB OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Christina Papagianni of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on temperature-related memory component capabilities. the controller determines a read disturb condition criterion associated with an individual memory component of a set of memory components and determines a temperature of a memory sub-system comprising the set of memory components. the controller adjusts the read disturb condition criterion based on the temperature and program erase cycles (pec) of the memory sub-system and performs an individual media management operation on the individual memory component in response to determining that the adjusted read disturb condition criterion has been satisfied.
20250004664. READ LATENCY AND SUSPEND MODES_simplified_abstract_(micron technology, inc.)
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: methods, systems, and devices for read latency and suspend modes are described. a memory system may operate in a first mode of operation associated with a first set of access operations including executing read operations, executing write operations, and suspending write operations. the memory system may receive, from a host system, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based on limiting a suspension of write operations. for example, the host system may transmit a command including the indication to switch to the second mode of operation. in another example, the host system may write a value to a register at the memory system including the indication to switch to the second mode of operation. based on receiving the indication from the host system, the memory system may then operate according to the second mode of operation.
20250004668. INTER-TIER METADATA STORAGE_simplified_abstract_(micron technology, inc.)
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0862
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for inter-tier metadata storage are described. a controller associated with a memory system may manage metadata storage across tiers of memory within the memory system or across memory systems. the controller may transfer metadata between tiers of memory based on whether an access count associated with the metadata satisfies a threshold. for example, the controller may transfer metadata from a first tier of memory to a second tier of memory if the access count satisfies a threshold count. the controller may transfer the metadata from the second tier of memory to the first tier of memory if the access count fails to satisfy the threshold count.
Inventor(s): Keng Gee Ng of Singapore (SG) for micron technology, inc., Mohammed Musaiyab Tarapati of Singapore (SG) for micron technology, inc., Shyam Sunder Raghunathan of Singapore (SG) for micron technology, inc.
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/4418
Abstract: control logic in a memory device initiates application of a program pulse on a memory array of a memory device as part of a program operation and determines whether a first request to suspend the program operation was received during the application of the program pulse. responsive to determining that the first request to suspend the program operation was received during the application of the program pulse, the control logic sets a program suspend indicator to a suspend state. responsive to completing application of the program pulse, the control logic initiates a program verify operation on the memory array, and responsive to completing the program verify operation, determines that the program suspend indicator is set to the suspend state and suspends the program operation.
Inventor(s): Keun Soo Song of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc., Hyun Yoo Lee of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F3/06
CPC Code(s): G06F11/1044
Abstract: described apparatuses and methods provide configurable error correction code (ecc) circuitry and schemes that can utilize a shared ecc engine between multiple memory banks of a memory, including a low-power double data rate (lpddr) memory. a memory device may include one or more dies with multiple memory banks. the configurable ecc circuitry can use an ecc engine that services a memory bank by producing ecc values based on data stored in the memory bank when data-masking functionality is enabled. when data-masking functionality is disabled, the configurable ecc circuitry can use the shared ecc engine that services at least two memory banks by producing ecc values with a larger quantity of bits based on respective data stored in the at least two memory banks. by using the shared ecc engine responsive to the data-masking functionality being disabled, the ecc functionality can provide higher data reliability with lower die area utilization.
20250004939. SIGNAL MONITORING BY A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Huachen Li of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for signal monitoring by a memory system are described. a memory system may receive signaling (e.g., from a host system) and may sample the signal and generate an eye diagram. during a normal mode of operation, the memory system monitor characteristics of the eye diagram to improve signaling. the memory system may determine a voltage level of the signaling based on one or more input parameters and sampling times associated with the signaling. an indication of the voltage level of the signaling may be stored (e.g., to a register of the memory system) and may be periodically transmitted to the host system.
Inventor(s): Eric N. Lee of San Jose CA (US) for micron technology, inc., Leonid Minz of Beer Sheva (IL) for micron technology, inc., Yoav Weinberg of Toronto (CA) for micron technology, inc., Ali Feiz Zarrin Ghalam of Sunnyvale CA (US) for micron technology, inc., Luigi Pilolli of L’Aquila (IT) for micron technology, inc.
IPC Code(s): G06F13/30, G06F13/16
CPC Code(s): G06F13/30
Abstract: a memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data transfer across an interface bus to be suspended by toggling a logical level of a control pin from a first level that activates the data transfer to a second level that suspends the data transfer, and causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level.
20250006235. MODIFICATION OF A COMMAND TIMING PATTERN_simplified_abstract_(micron technology, inc.)
Inventor(s): Carl L. Minifie of Boise ID (US) for micron technology, inc., Phong T. Nguyen of Boise ID (US) for micron technology, inc., Alexander A. Tomaso of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C11/4076
CPC Code(s): G11C7/109
Abstract: methods, systems, and devices for modification of a command timing pattern are described. a host device may transmit (e.g., issue), to a memory device, a quantity of deselect commands between activation or data access commands to satisfy configured timing constraints. each deselect command may indicate a polarity (e.g., a high voltage or a low voltage) for a command and address (ca) pin at the memory device. in some examples, the quantity of deselect commands may include one or more sequences of deselect commands (e.g., low-high-high-high). the host device may truncate a sequence of deselect commands, for example to satisfy timing constraints without transmitting additional unnecessary commands. by dynamically configuring the quantity of deselect commands, the host device may improve latency and overall efficiency of system operations without violating the configured timing constraints.
20250006236. MEMORY ROW-HAMMER MITIGATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Bryan David Kerstetter of Kuna ID (US) for micron technology, inc., Alan J. Wilson of Boise ID (US) for micron technology, inc., Donald Martin Morgan of Meridian ID (US) for micron technology, inc.
IPC Code(s): G11C7/24, G11C7/10, G11C8/20
CPC Code(s): G11C7/24
Abstract: methods, systems, and devices for memory row-hammer mitigation are described. a memory device may operate based on a scheme that is continuous across power cycles. for example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “on” state). accordingly, the value of the counter may be maintained across power cycles.
Inventor(s): Vincenzo Reina of Munich (DE) for micron technology, inc., Christopher Joseph Bueb of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C5/14, G11C11/4074, G11C11/4076
CPC Code(s): G11C11/40615
Abstract: methods, systems, and devices for techniques to refresh memory systems operating in low power states are described. the memory system may operate in a first power mode that includes deactivation of a voltage rail that supplies power to the memory system. the memory system may receive the power over the voltage rail during a time period that the memory system is operating in the first power mode. in some cases, the memory system may determine that the power may be received for a duration and a command is not received during that duration. the memory system may perform a self-refresh operation based on determining that the duration indicated by the timer expires without receiving a command.
Inventor(s): Yuan He of Boise ID (US) for micron technology, inc., Takamasa Suzuki of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/408
CPC Code(s): G11C11/40622
Abstract: apparatuses, systems, and methods for access based targeted refresh operations. a memory bank has a first sub-bank and a second sub-bank. a refresh control circuit detects an aggressor in one of the sub-banks. responsive to an access in the other sub-bank, the refresh control circuit performs a targeted refresh operation based on the sub-bank based on the aggressor address.
20250006248. ROW ACTIVATION INDICATION REGISTERS_simplified_abstract_(micron technology, inc.)
Inventor(s): Graziano Mirichigni of Vimercate (IT) for micron technology, inc., Antonino Caprì of Bergamo (IT) for micron technology, inc.
IPC Code(s): G11C11/408, G11C11/4076
CPC Code(s): G11C11/4085
Abstract: methods, systems, and devices related to row activation indication registers are disclosed. a first register can be coupled to a memory device and configured to store an indication of a first number of bit locations of a row address corresponding to the memory device to use in association with optimization of a row precharge time (trp) of the memory device. a second register can be coupled to the memory device and configured to store an indication of a second number of bit locations of the row address to use in association with optimization of a row address to column address delay (trcd) of the memory device.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Mingdong Cui of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C11/408, H10B80/00
CPC Code(s): G11C11/4085
Abstract: methods, systems, and devices for word line drivers for multiple-die memory devices are described. a memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. the second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. for example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.
Inventor(s): Aliasger T. Zaidy of Seattle WA (US) for micron technology, inc., Glen E. Hush of Boise ID (US) for micron technology, inc., Sean S. Eilert of Penryn CA (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4093, G06F3/06, G06F13/16, G06F13/28, G11C7/08, G11C7/10, G11C11/408, G11C11/4091, G11C11/4096, G16B30/00, G16B50/10, H01L21/66, H01L21/78, H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): G11C11/4093
Abstract: a memory device includes a memory die bonded to a logic die. a logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. the logic die can also receive signals indicative of kernel data from local input/output (lio) lines of the memory die and through the bond. the logic die can perform a plurality of operations at a plurality of vector-vector (vv) units utilizing the signals indicative of input data and the signals indicative of kernel data. the inputs and the outputs to the vv units can be configured based on a mode of the logic die.
20250006261. MEMORY DEVICE WITH SEGMENTED SGD DRAIN_simplified_abstract_(micron technology, inc.)
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc., Collin Howder of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, G11C16/14, H10B41/27, H10B41/35, H10B43/27, H10B43/35
CPC Code(s): G11C16/0483
Abstract: a variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (gidl) current during memory erase operations. the enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells at segmented drains of the select gate transistors. the segmented drains can have conductive fins integrated with the transistor channel structure and extending vertically from a top border of the transistor channel structure, where the conductive fins are separated from each other by non-conductive regions on the top border. the segmented drain can include portions extending downward below the top border. the transistor channel structures can be integrated with the channel structures of the pillars forming the strings of memory cells. additional devices, systems, and methods are discussed.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Shyam Sunder Raghunathan of Singapore (SG) for micron technology, inc., Tingjun Xie of Milpitas CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08
CPC Code(s): G11C16/102
Abstract: a processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of a block addressable by a first wordline of a first die of the memory device, wherein the first die comprises a plurality of decks of the memory device. the processing device identifies, based on a predefined usage type associated with the first die, a deck of the plurality of decks for performing the programming operation; and performing the programming operation on a second set of cells of the block addressable by the first wordline residing on the identified deck of the first die.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Aaron Lee of Sunnyvale CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C29/52
CPC Code(s): G11C16/102
Abstract: a processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells addressable by a first wordline of a first plane of the memory device. the processing device identifies a predefined index shift value associated with the first wordline. the processing device determines, by applying the predefined index shift value to a first index value of the first wordline, a second index value of a second wordline of a second plane of the memory device. the processing device further performs a second programming operation on a second set of cells addressable by the second wordline of the second plane.
Inventor(s): Shyam Sunder Raghunathan of Woodlands (SG) for micron technology, inc., Akira Goda of Setagaya (JP) for micron technology, inc., Kishore K. Muchherla of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/04, G11C16/26
CPC Code(s): G11C16/16
Abstract: an apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. control circuitry can be configured to: receive a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block; and determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation. the adjusted sense voltage is based on: a quantity of the first group of access lines that are programmed; or a quantity of the second group of access lines that are programmed; or both.
Inventor(s): Gary F. Besinga of Boise ID (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Steven Michael Kientz of Westminster CO (US) for micron technology, inc., Renato C. Padilla of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/26
CPC Code(s): G11C16/3459
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying an open block of the memory device, determining, based on at least one charge loss metric associated with a set of programmed pages of the open block or at least one charge gain metric associated with a set of erased pages of the open block, whether the open block is valid for programming, and responsive to determining that the open block is not valid for programming, abandoning the open block.
Inventor(s): Taylor Alu of Boise ID (US) for micron technology, inc., Nicola Ciocchini of Boise ID (US) for micron technology, inc., Shyam Sunder Raghunathan of Woodlands (SG) for micron technology, inc., Guang Hu of Mountain View CA (US) for micron technology, inc., Walter Di Francesco of Avezzano (IT) for micron technology, inc., Umberto Siciliani of Rubano (IT) for micron technology, inc., Violante Moschiano of Avezzano (IT) for micron technology, inc., Karan Banerjee of Singapore (SG) for micron technology, inc.
IPC Code(s): G11C29/52, G11C16/20, G11C16/34
CPC Code(s): G11C29/52
Abstract: a method includes detecting a change in a memory control signal of a memory device including memory blocks, determining based at least on the change in the memory control signal that the memory device is in a stable state, and responsive to determining that the memory device is in the stable state, associating a voltage offset bin with at least one memory block of the memory device.
Inventor(s): Libo Wang of Boise ID (US) for micron technology, inc., Xiao Li of Boise ID (US) for micron technology, inc., Bethany M. Grentz of Meridian ID (US) for micron technology, inc., Sumana Adusumilli of Boise ID (US) for micron technology, inc., Carla L. Christensen of Boise ID (US) for micron technology, inc.
IPC Code(s): G16H10/60, G01W1/10, G16H20/70
CPC Code(s): G16H10/60
Abstract: systems for weather sensing and forecasting, and associated devices and methods, are disclosed herein. in some embodiments, a system for predicting a subject's perception of weather conditions is provided. the system can generate an individual profile for the subject, the individual profile including health information of the subject. the system can receive weather data including a first weather condition for a target location. the system can compare the individual profile to a plurality of different user profiles to identify one or more similar user profiles. each similar user profile can (1) be associated with a user having similar health information as the subject, and (2) include weather perception data indicating how the user perceived a set of second weather conditions. based on the weather data and the similar user profile(s), the system can generate a prediction of the how the subject will perceive the first weather condition.
Inventor(s): Shruthi Kumara Vadivel of Boise ID (US) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc., Lance David Williamson of Boise ID (US) for micron technology, inc., Kaveri Jain of Hyderabad (IN) for micron technology, inc., Adam Lewis Olson of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/544, H01L21/311
CPC Code(s): H01L23/544
Abstract: aligning pillars of a three-dimensional nand memory assembly can include forming a first pillar and a corresponding first pillar alignment feature in at least a portion of a first substrate stack. the alignment method can include depositing a second substrate stack on the first substrate stack, covering the first pillar alignment feature and the first pillar, and depositing a first masking layer on at least a portion of the second substrate stack. illumination light can be used to illuminate a portion of the first masking layer. a reflected portion of the illumination light can indicate a location of the first pillar alignment feature corresponding to the first pillar. particular wavelengths of the illumination light can be blocked or filtered by the first masking layer.
Inventor(s): Mitsuhisa Watanabe of Akita (JP) for micron technology, inc., Fumitomo Watanabe of Akita (JP) for micron technology, inc., Masanori Yoshida of Akita (JP) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/00, H01L23/367, H01L23/498, H01L23/538, H01L25/00, H01L25/18
CPC Code(s): H01L25/0652
Abstract: semiconductor device assemblies with support substrates and associated methods are disclosed herein. in one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. the assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/00, H01L25/00, H01L25/18, H10B80/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor device with a spaced supply voltage and ground reference is disclosed. a stack of semiconductor dies includes a first semiconductor die, one or more second semiconductor dies, and first and second contacts. a gap fill is disposed over a distal end of the one or more second semiconductor dies opposite the first semiconductor die. a first rail (e.g., supply voltage) is disposed at a distal end of the gap fill opposite the first semiconductor die, and a first via extends from the first rail to the first contact. a layer of dielectric material is disposed at least partially over the first rail. a second rail (e.g., ground reference) is disposed at the layer of dielectric material, and a second via extends from the second rail to the second contact. third and fourth exposed contacts are coupled to the first and second rails, respectively.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc., Robert Noel Bielby of Placerville CA (US) for micron technology, inc.
IPC Code(s): H04L9/40, G06F8/65, G06F21/57
CPC Code(s): H04L63/029
Abstract: methods, systems, and devices for security configurations for zonal computing architecture are described. a zonal computing system in a vehicle may be associated with multiple zones. the zonal computing system may include devices (e.g., sensors, actuators) that interact with the vehicle or an environment associated with the vehicle. a memory system included in the zonal computing system may authenticate whether a device associated with a zone is a trusted device and enable or restrict communications with the device based on the authentication. for example, the zonal computing system may include a central processor that communicates with a remote server and the multiple zones and may include a gateway processor coupled with the central processor and the device and associated with the zone. based on whether the device is trusted, the memory system may enable or restrict communications between the central processer and the device and routed through the gateway processor.
20250008727. MEMORY DEVICES AND ELECTRONIC SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Erwin E. Yu of San Jose CA (US) for micron technology, inc., Surendranath C. Eruvuru of Boise ID (US) for micron technology, inc., Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc.
IPC Code(s): H10B41/41, B81B7/02, G11C7/10, G11C16/24, H10B41/20, H10B43/20, H10B43/40
CPC Code(s): H10B41/41
Abstract: a microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. the stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. the first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. the second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. the multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. the multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. additional microelectronic devices, memory devices, and electronic systems are also described.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B80/00, H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: a semiconductor device with a through via between redistribution layers is disclosed. the semiconductor device includes a stack of semiconductor dies coupled with first contact pads on a first redistribution layer. the first redistribution layer further includes a second contact pad located outside the footprint of the die stack and circuitry coupling the second contact pad to the first contact pads. a gap fill is disposed around the stack of semiconductor dies. a second redistribution layer is disposed at the stack of semiconductor dies and the gap fill. the second redistribution layer includes third contact pads coupled with the stack of semiconductor dies, a fourth contact pad disposed beyond the footprint of the stack of semiconductor dies, fifth contact pads opposite the third and fourth contact pads, and circuitry coupling the contact pads. a through via is disposed through the gap fill coupling the second and fourth contact pads.
Micron Technology, Inc. patent applications on January 2nd, 2025
- Micron Technology, Inc.
- G06F3/06
- CPC G06F3/0604
- Micron technology, inc.
- G11C16/34
- G11C29/52
- CPC G06F3/0611
- CPC G06F3/0616
- CPC G06F3/0632
- CPC G06F3/0647
- CPC G06F3/0655
- G06F12/0862
- CPC G06F3/0659
- G06F9/4401
- CPC G06F9/4418
- G06F11/10
- CPC G06F11/1044
- G06F12/02
- CPC G06F12/0246
- G06F13/30
- G06F13/16
- CPC G06F13/30
- G11C7/10
- G11C11/4076
- CPC G11C7/109
- G11C7/24
- G11C8/20
- CPC G11C7/24
- G11C11/406
- G11C5/14
- G11C11/4074
- CPC G11C11/40615
- G11C11/408
- CPC G11C11/40622
- CPC G11C11/4085
- H10B80/00
- G11C11/4093
- G06F13/28
- G11C7/08
- G11C11/4091
- G11C11/4096
- G16B30/00
- G16B50/10
- H01L21/66
- H01L21/78
- H01L23/00
- H01L25/00
- H01L25/065
- H01L25/18
- CPC G11C11/4093
- G11C16/04
- G11C16/14
- H10B41/27
- H10B41/35
- H10B43/27
- H10B43/35
- CPC G11C16/0483
- G11C16/10
- G11C16/08
- CPC G11C16/102
- G11C16/16
- G11C16/26
- CPC G11C16/16
- CPC G11C16/3459
- G11C16/20
- CPC G11C29/52
- G16H10/60
- G01W1/10
- G16H20/70
- CPC G16H10/60
- H01L23/544
- H01L21/311
- CPC H01L23/544
- H01L23/367
- H01L23/498
- H01L23/538
- CPC H01L25/0652
- CPC H01L25/0657
- H04L9/40
- G06F8/65
- G06F21/57
- CPC H04L63/029
- H10B41/41
- B81B7/02
- G11C16/24
- H10B41/20
- H10B43/20
- H10B43/40
- CPC H10B41/41
- CPC H10B80/00