Micron Technology, Inc. patent applications on February 20th, 2025
Patent Applications by Micron Technology, Inc. on February 20th, 2025
Micron Technology, Inc.: 37 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (11), G06F11/10 (6), G06F12/02 (4), G06F11/07 (4), H10B12/00 (3) G06F3/0659 (3), G06F12/0223 (2), G06F11/1068 (2), G11C19/0808 (1), G11C7/1063 (1)
With keywords such as: memory, data, device, block, include, host, cells, devices, status, and structure in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Jean-Sebastien Materne Lehn of Boise ID (US) for micron technology, inc., Francois H. Fabreguette of Boise ID (US) for micron technology, inc., Timothy A. Quick of Boise ID (US) for micron technology, inc.
IPC Code(s): C23C16/455, H01L21/02
CPC Code(s): C23C16/45553
Abstract: methods, systems, and devices for methods for depositing germanium films by atomic layer deposition are described. for instance, a device may expose a base material (e.g., multiple stacks of materials) to a first precursor to form a germanium compound on the base material, the first precursor including a germanium amidinate. in some examples, the germanium compound may include germanium and at least one leaving group. the device may react a second precursor with the germanium compound and may form a layer of germanium on the base material based on exposing the base material to the first precursor and reacting the second precursor with the germanium compound. in some examples, the device may remove the at least one leaving group from the germanium compound based on reacting the second precursor with the germanium compound.
Inventor(s): Sriteja Yamparala of Boise ID (US) for micron technology, inc., Tawalin Opastrakoon of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: a method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block, receiving a request to write data subsequent to erasing the candidate memory blocks, and, responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks. the block characteristics of the candidate memory block can include a program erase count and/or a temperature of the candidate memory block.
Inventor(s): Zhenming Zhou of San Jose CA (US) for micron technology, inc., Ying Yu Tai of Mountain View CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F11/30
CPC Code(s): G06F3/061
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on memory component reliabilities. the controller can access configuration data to determine a reliability grade associated with individual groups of the memory components. the controller can then adaptively select between different media management operations based on the reliability grade associated with each individual group of the memory components.
Inventor(s): Samir Mittal of Palo Alto CA (US) for micron technology, inc., Gurpreet Anand of Pleasanton CA (US) for micron technology, inc., Ying Yu Tai of Mountain View CA (US) for micron technology, inc., Cheng Yuan Wu of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F9/445, G06F13/16, G06F13/42, G11C16/20
CPC Code(s): G06F3/0611
Abstract: a computing system having a memory component with an embedded media controller. the memory component is encapsulated within an integrated circuit (ic) package. the embedded controller within the ic package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the ic package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the ic package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the ic package.
20250060888. MULTI-FORMAT DATA OBJECTS IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0631
Abstract: to implement a multi-format data object in memory, a device can receive an allocation request for a data object that includes a set of data elements. this allocation request includes respective details for a set of formats for the data object, such as details for a first format in the set of formats including. the details can include memory address information and a mapping between a first data element of the data object in the first format to a second data element in a second format in the set of formats. the details can also include identification of a conversion function configured to convert the first data element to the second data element. the device can provide access to the second format of the data object from the first format of the data object in the memory based on the mapping data structure or the conversion data structure.
Inventor(s): John M. Gonzales of Boise ID (US) for micron technology, inc., Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc., Seth A. Eichmeyer of Boise ID (US) for micron technology, inc., Matthew D. Jenkinson of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: apparatuses, systems, and methods for tracking latch upset events using block status data are described. an example method includes tracking a block status of each of a plurality of blocks of a first memory device by storing a first set of block status data that indicates a status of each block of the plurality of blocks in the first memory device and storing a second set of block status data that indicates a status of each block of the plurality of blocks in a location. the example method further includes comparing the first set of block status data to the second set of block status data.
Inventor(s): Sourabh Dhir of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. a memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. the memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. the memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.
Inventor(s): Reshmi Basu of Boise (ID) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0655
Abstract: systems, apparatuses, and methods related to object management in tiered memory systems are discussed. an example method can include determining a type of characteristic set for each of a plurality of memory objects to be written to a memory system. the memory system can include a first memory device and a second memory device. the method can further include configuring each of the plurality of memory objects to be written to the memory system in the first memory device or the second memory device based on the determination of the type of characteristic set associated with each of the plurality of memory objects. the method can further include writing each of the plurality of memory objects to the first memory device or the second memory device based on the configuration of each of the plurality of memory objects.
Inventor(s): Melky Arputharaja Siluvainathan of San Jose CA (US) for micron technology, inc., Rohit Sehgal of San Jose CA (US) for micron technology, inc., Vishal D. Tanna of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F13/42
CPC Code(s): G06F3/0659
Abstract: a memory device can be coupled to a host device using a compute express link (cxl) interconnect. the memory device can include a host interface circuit and processing logic circuitry, such as a subsystem manager circuit. the host interface circuit of the memory device can be configured to operate in one of an autonomous mode and a distribution mode. in the autonomous mode, the host interface circuit is configured to maintain a connection between the host device and the memory device while the subsystem manager circuit of the memory device is unavailable, such as when the subsystem manager circuit undergoes a reset routine. in the distribution mode, the host interface circuit is configured to allow communication between the host device and the subsystem manager circuit of the memory device.
Inventor(s): Roy Leonard of San Jose CA (US) for micron technology, inc., Xiaolei Man of Shanghai (CN) for micron technology, inc., Bryan Li of Shanghai (CN) for micron technology, inc., Peijing Ye of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0811
CPC Code(s): G06F3/0659
Abstract: a system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the cache. the cache has a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a method performed by a distributed computing system includes receiving a work packet from a separate computing device via a fabric interconnect at a command manager (cm) of a memory controller of a fabric attached memory (fam) device, wherein the work packet includes a memory access to be performed by a fam computing resource local to the fam device; determining a work class of the work packet; placing the work packet in a cm work queue local to the cm for the work class when space is available in the cm work queue for the work class; and when the cm work queue for the work class is full, placing the work packet in a destination work queue according to an address included in the work packet, wherein the destination queue is implemented in a memory array of the fam device external to the memory controller.
Inventor(s): Nikesh Agarwal of Village (IN) for micron technology, inc., Chandana Manjula Linganna of Bangalore (IN) for micron technology, inc., Ravi Kiran Gummaluri of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F9/50
CPC Code(s): G06F9/505
Abstract: a system can include a host configured to provide requests to, and receive responses from, multiple compute resources. in an example, the compute resources can be distributed on respective accelerator devices that can be configured to communicate with the host using various protocols, such as using compute express link (cxl). a first accelerator device can include a telemetry manager that can receive a queue utilization signal indicative of a volume of transaction request messages or response messages handled by the first accelerator device. the first accelerator device can determine a device loading metric about the first accelerator device based on the queue utilization signal, and can provide a control signal with information about the device loading metric to the host device. the host device can select the first accelerator device or a different device based on the control signal.
20250061016. BLOCK STATUS DATA RESET_simplified_abstract_(micron technology, inc.)
Inventor(s): John M. Gonzales of Boise ID (US) for micron technology, inc., Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc., Seth A. Eichmeyer of Boise ID (US) for micron technology, inc., Matthew D. Jenkinson of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: apparatuses, systems, and methods for block status data reset are described. an example method includes sending a command, from a controller, to access at least one block of a first memory device. the example method further comprises receiving a failure message from the first memory device due to the at least one block being tagged as a bad block in block status data of the first memory device. the example method further comprises in response to receiving the failure message, resetting the block status data by reloading previously stored block status data from a second memory device.
Inventor(s): John M. Gonzales of Boise ID (US) for micron technology, inc., Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc., Seth A. Eichmeyer of Boise ID (US) for micron technology, inc., Matthew D. Jenkinson of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1016
Abstract: apparatuses, systems, and methods for correcting latch upset events in a trim register are described. an example method includes sending a command, from a controller, to access at least one block of a plurality of blocks of a non-volatile memory. the method can further include receiving a failure message associated with reading the at least one block. the method can further include, in response to receiving the failure message, resetting trim data associated with the plurality of blocks.
Inventor(s): John M. Gonzales of Boise ID (US) for micron technology, inc., Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc., Seth A. Eichmeyer of Boise ID (US) for micron technology, inc., Matthew D. Jenkinson of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: apparatuses, systems, and methods for tracking latch upset events using a trim register are described. an example method includes reading trim data from trim registers in a non-volatile memory device. the example method can further include generating parity data for the trim data. the example method can further include storing the parity data in the trim registers. the example method can further include, subsequent to the generation and storage of the parity data, re-reading the trim data from the trim registers, generating additional parity data, and comparing the parity data to the additional parity data.
20250061021. DEVICE FAULT CONDITION REPORTING_simplified_abstract_(micron technology, inc.)
Inventor(s): Crescenzo Attanasio of Acerra (IT) for micron technology, inc., Carminantonio Manganelli of San Giorgio Del Sannio (IT) for micron technology, inc., Massimo Iaculo of San Marco Evangelista (IT) for micron technology, inc., Paolo Papa of Napoli (IT) for micron technology, inc., Antonio Eliso of Boscoreale (IT) for micron technology, inc.
IPC Code(s): G06F11/10, G06F3/06, G06F11/07
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for device fault condition reporting are described. a host system may transmit, to a memory system, a command to perform an operation. the memory system may receive the command and identify a fault condition associated with performing the operation. the memory system may transmit, to the host system, a message that indicates the fault condition. after the memory system transmits the message, the memory system may enter a safe mode of operation based on identifying the fault condition.
20250061023. ECC CONFIGURATION IN MEMORIES_simplified_abstract_(micron technology, inc.)
Inventor(s): Graziano Mirichigni of Vimercate (IT) for micron technology, inc., Christophe Laurent of Agrate Brianza (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1076
Abstract: the present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an error correction code (ecc) correction capability and/or an ecc granularity according to which an ecc operation is to be performed, wherein the selection of the ecc correction capability and/or the ecc granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ecc correction capability and/or a required ecc granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ecc correction capability and/or a required ecc granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ecc switch command, wherein the ecc switch command is such as to vary a previously selected ecc correction capability and/or a previously selected ecc granularity, the method further comprising: updating a second register according to the varied ecc correction capability and/or ecc granularity, said second register comprising values indicating the selected ecc correction capability and the selected ecc granularity applied to the memory cells based on the current status thereof. related apparatuses and systems are also herein disclosed.
Inventor(s): Bhumika Chhabra of Boise ID (US) for micron technology, inc., Erica A. Ellingson of Boise ID (US) for micron technology, inc., Sumedha Gandharava of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/30, G06F11/32
CPC Code(s): G06F11/3089
Abstract: systems, methods, and apparatuses for data prioritization and selective data processing are described herein. a computing device may receive sensor data and prioritize a first portion of the sensor data over a second portion of the sensor data. the first portion of sensor data may be stored in a first memory that has a higher access rate than a second memory where the second portion of sensor data is stored. the first portion of sensor data may be processed with priority and the second portion of sensor data may be transmitted to a cloud computing device.
20250061055. STORAGE OF DATA USING RETIRED MEMORY ROWS_simplified_abstract_(micron technology, inc.)
Inventor(s): Rohit Sehgal of San Jose CA (US) for micron technology, inc., Vishal Tanna of Santa Clara CA (US) for micron technology, inc., Melky Siluvainathan of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G11C29/44
CPC Code(s): G06F12/0223
Abstract: methods, apparatuses, and systems related to storing non-mission-critical data using retired memory slots are described. an apparatus includes circuitry configured to determine that a post package repair (ppr) operation, associated with a memory row of a memory device, has been requested by a host device communicably coupled to the circuitry. the memory row is associated with a physical address. the circuitry determines a location of a defective bit in the memory row. retired row data comprising the physical address associated with the memory row and the defective bit location is maintained in non-transitory memory of the apparatus.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0223
Abstract: a memory device (e.g., a high-bandwidth (hbm) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. the memory die can include first memory banks associated with a first channel (e.g., having a first command address (ca) bus) and a first pseudo channel (e.g., having a first data (dq) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second dq bus). operations can be performed at the first memory banks or the second memory banks in response to a command received through the first ca bus. the operations can cause data to be returned to circuitry that routes the data to an interface to the first dq bus or an interface to the second dq bus based on whether the data resulted from operations at the first memory banks or the second memory banks.
20250061058. BLOCK STATUS PARITY DATA IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): John M. Gonzales of Boise ID (US) for micron technology, inc., Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc., Seth A. Eichmeyer of Boise ID (US) for micron technology, inc., Matthew D. Jenkinson of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F11/10
CPC Code(s): G06F12/0246
Abstract: apparatuses, systems, and methods for block status parity data are described. an example method includes storing block status data associated with at least one block of a non-volatile memory that indicates a status of the at least one block of memory within a controller. the example method further comprises storing parity data that corresponds to the block status data. the example method further comprises prior to writing the block status data to the non-volatile memory, comparing the stored block status data to the parity data.
20250061059. HYBRID CACHE COHERENCY_simplified_abstract_(micron technology, inc.)
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0802
Abstract: to implement a hybrid of software and hardware coherency management, a device can receive an unrestricted-access read request for memory that corresponds to a cache line from a first host and record an indication of the unrestricted-access read request with respect to the cache line. here, the indication can include an identifier for the first host. however, if the device receives a shared-access read request for the cache line from a second host, the device does not record an identifier of the second host. rather, the device can communicate an invalidation request for the cache line to the first host using the identifier for the first host to provoke the first host to write-back the data and invalidate the cache line.
Inventor(s): Melky Arputharaja Siluvainathan of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F13/12, G06F13/24
CPC Code(s): G06F13/124
Abstract: a first set of parameter values are programed to a first set of sequencer registers. a second set of parameter values are programmed to a second set of sequencer registers. in response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/16
CPC Code(s): G06F13/1684
Abstract: a memory device (e.g., a high-bandwidth (hbm) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. the memory die can include first memory banks associated with a first channel (e.g., having a first command address (ca) bus) and a first pseudo channel (e.g., having a first data (dq) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second dq bus). operations can be performed at the first memory banks or the second memory banks in response to a command received through the first ca bus. the operations can cause data to be returned to circuitry that routes the data to an interface to the first dq bus or an interface to the second dq bus based on whether the data resulted from operations at the first memory banks or the second memory banks.
Inventor(s): Sai Vidya Manohar Raju Kasturi of Hyderabad (IN) for micron technology, inc., Rahul Krishna Velitheri of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G11C5/14, H04L25/03
CPC Code(s): G11C5/147
Abstract: a system including a memory sub-system controller to transmit a data signal via a communication channel. the system includes a receiver to receive the data signal from the memory sub-system controller via an interface, the receiver comprising a decision feedback equalizer (dfe) sub-system. the dfe sub-system includes a first data detector circuit including a first tap circuit, where the first data detector circuit generates, using a first reference voltage, a first subset of detected values corresponding to the data signal. the dfe sub-system includes a second data detector circuit including a second tap circuit, where the second data detector circuit generates a second subset of detected bit values corresponding to the data signal using a second reference voltage.
Inventor(s): Murong Lang of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Jian Huang of Union City CA (US) for micron technology, inc., Zhongguang Xu of San Jose CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1063
Abstract: a read operation is performed on a set of memory cells addressable by a first wordline (wl), wherein the set of memory cells is comprised by an open translation unit (tu_ of memory cells of a memory device. respective threshold voltage offset bins for each wl of a second plurality of wls coupled to respective sets of memory cells comprised by the open tu are determined based on a threshold voltage offset bin associated with the first wl. respective default threshold voltages for each wl of the first plurality of wls are updated based on the respective threshold voltage offset bins for each wl of the second plurality of wls.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G11C7/16, G11C7/10, G11C7/12, G11C8/08
CPC Code(s): G11C7/16
Abstract: a memory sub-system configured to perform multiplication and accumulation operations using truncated outputs. for example, voltages can be applied, according to a bit slice having a slice weight in an input, to memory cells storing weights. a resolution control can be applied, according to the slice weight, to an analog to digital converter coupled to the line having a current resulting from the memory cells responsive to the voltages. the analog to digital converter can measure at least one first bit of a quantity representative of a magnitude of the current in the line to provide a truncated output, skipping measuring of at least one second bit of the quantity according to the resolution control. summing truncated outputs resulting from the bit slices from the input can provide an approximated result of the sum of elements in the input weighted by the weights.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C11/4091, G11C11/4097, H10B12/00
CPC Code(s): G11C11/4085
Abstract: a microelectronic device includes a first die and a second die vertically overlying and attached to the first die. the first die includes an array region and a peripheral region horizontally neighboring the array region. the array region includes memory cells respectively including a first transistor structure, a second transistor structure horizontally neighboring the first transistor structure, and a storage device vertically underlying and coupled to the first transistor structure and the second transistor structure. the peripheral region includes sub word line driver circuitry. the second die includes sense amplifier regions and a cmos region horizontally neighboring some of the sense amplifier regions. the sense amplifier regions are within a horizontal area of the array region of the first die and include sense amplifier circuitry. the cmos region horizontally neighbors some of the sense amplifier regions and includes cmos circuitry. related memory devices and electronic systems are also described.
Inventor(s): Lorenzo Fratin of Buccinasco (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc., Agostino Pirovano of Milano (IT) for micron technology, inc., Russell L. Meyer of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C13/00, H01L23/528
CPC Code(s): G11C13/0007
Abstract: methods, systems, and devices for self-selecting memory with horizontal access lines are described. a memory array may include first and second access lines extending in different directions. for example, a first access line may extend in a first direction, and a second access line may extend in a second direction. at each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
[[20250061956. Memory Devices Comprising Magnetic Tracks Individually Comprising a Plurality of Magnetic Domains Having Domain Walls and Methods of Forming a Memory Device Comprising Magnetic Tracks Individually Comprising a Plurality of Magnetic Domains Having Domain Walls_simplified_abstract_(micron technology, inc.)]]
Inventor(s): Livio Baldi of Agrate Brianza (IT) for micron technology, inc., Marcello Mariani of Milano (IT) for micron technology, inc.
IPC Code(s): G11C19/08, G11B5/49, G11C11/14, G11C11/16, H10N50/01, H10N50/80
CPC Code(s): G11C19/0808
Abstract: a method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. the uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. a plurality of magnetic tracks is formed over and which angle relative to the alternating regions. interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. other methods, including memory devices independent of method, are disclosed.
20250061960. MEMORY DEVICE WITH A STORAGE COMPONENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Lingming Yang of Meridian ID (US) for micron technology, inc., Raghukiran Sreeramaneni of Frisco TX (US) for micron technology, inc., Nevil N. Gajera of Meridian ID (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/00
CPC Code(s): G11C29/52
Abstract: a stacked memory device (e.g., a high-bandwidth memory (hbm) device) having a storage component is disclosed. the stacked memory device can include a first logic die, one or more memory dies, a second logic die, and one or more storage dies. the first logic die is coupled with the one or more memory dies and the second logic die through tsvs. the second logic die is coupled with the one or more storage dies through additional tsvs. the first logic die can issue commands to the one or more memory dies that cause the one or more memory dies to perform operations (e.g., read/write operations). the first logic die can also issue commands to the second logic die that cause the second logic die to issue commands to the one or more storage dies to perform operations.
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, G11C16/04, H10B41/10, H10B41/20, H10B43/10, H10B43/20
CPC Code(s): H01L23/5283
Abstract: a microelectronic device includes a first deck, a second deck, and a first conductive structure. the first deck has one or more memory cell strings and a stack of data lines operably connected to the one or more memory cell strings. each of the one or more memory cell strings includes a first conductive contact. the second deck is vertically adjacent to the first deck and includes stacked tiers of conductive material defining a first interconnect structure. the first interconnect structure is operably connected to a data line of the stack of data lines. the first conductive structure is electrically coupled to the first conductive contact of the first deck and to the first interconnect structure of the second deck. methods of forming the microelectronic device are also disclosed, as are memory devices, electronic signal processor devices, and electronic systems comprising such microelectronic devices.
Inventor(s): Kai Chieh Wang of Hsinchu City (TW) for micron technology, inc., Chia Ching Chen of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/31, H01L23/498, H01L25/00, H01L25/065, H10B80/00
CPC Code(s): H01L24/32
Abstract: a semiconductor device assembly is provided, which comprises a vertical stack of semiconductor devices, the vertical stack including a plurality of electrical interconnects, a plurality of retention structures, and a non-conductive film (ncf) between each adjacent pair of semiconductor devices of the vertical stack. the plurality of retention structures between each adjacent pair of semiconductor devices is disposed peripherally to the corresponding plurality of electrical interconnects. each of the plurality of retention structures has a height less than a space between the corresponding adjacent pair of semiconductor devices, and the plurality of retention structures between each adjacent pair of semiconductor devices has a smaller first average pitch between adjacent ones of the plurality of retention structures than a second average pitch between adjacent ones of the corresponding plurality of electrical interconnects.
20250063719. MEMORY DEVICES INCLUDING CAPACITORS_simplified_abstract_(micron technology, inc.)
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Yuan He of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C5/02, G11C5/10, G11C11/407
CPC Code(s): H10B12/30
Abstract: a microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. the microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. the capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. related microelectronic devices, electronic systems, and methods are also described.
Inventor(s): Giorgio Servalli of Fara Gera D'Adda (IT) for micron technology, inc., Marcello Mariani of Milano (IT) for micron technology, inc.
IPC Code(s): H10B12/00, G11C11/22, H10B53/10, H10B53/30
CPC Code(s): H10B12/315
Abstract: some embodiments include an assembly having first and second pillars. each of the pillars has an inner edge and an outer edge. a first gate is proximate a channel region of the first pillar. a second gate is proximate a channel region of the second pillar. a shield line is between the first and second pillars. first and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. an insulative material is over the first and second bottom electrodes. the insulative material may be ferroelectric or non-ferroelectric. a top electrode is over the insulative material. some embodiments include methods of forming assemblies.
Inventor(s): Collin Howder of Boise ID (US) for micron technology, inc., Justin D. Shepherdson of Meridian ID (US) for micron technology, inc., Chet E. Carter of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B43/50
CPC Code(s): H10B43/27
Abstract: a microelectronic device may include a source structure and a stack structure. the stack structure may include a vertically alternating sequence of insulative structures and conductive structures. filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.
Inventor(s): Beth R. Cook of Boise ID (US) for micron technology, inc., Zhuo Chen of Boise ID (US) for micron technology, inc., Yixin Yan of Boise ID (US) for micron technology, inc., Sarah P. Sredzinski of Meridian ID (US) for micron technology, inc., Gloria Y. Yang of Boise ID (US) for micron technology, inc., Kathryn H. Russo of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B53/30
CPC Code(s): H10B53/30
Abstract: an electronic device comprises a memory array comprising access lines, data lines, and memory cells. each memory cell is coupled to an associated access line and an associated data line and each memory cell comprises an access device, and a capacitor adjacent to the access device. the capacitor comprises a first electrode, a second electrode separated from the first electrode by an insulative material, and a leaker device adjacent to the first electrode. the second electrode and the leaker device extend through a lattice insulative material adjacent to the first electrode. the leaker device exhibits a substantially circular cross-sectional shape in a direction that is transverse to a direction in which the leaker device extends, with portions of the leaker device extending within a recessed region of the insulative material. methods of forming electronic devices are also disclosed.
Micron Technology, Inc. patent applications on February 20th, 2025
- Micron Technology, Inc.
- C23C16/455
- H01L21/02
- CPC C23C16/45553
- Micron technology, inc.
- G06F3/06
- CPC G06F3/0608
- G06F11/30
- CPC G06F3/061
- G06F9/445
- G06F13/16
- G06F13/42
- G11C16/20
- CPC G06F3/0611
- CPC G06F3/0631
- CPC G06F3/064
- CPC G06F3/0647
- G06F12/02
- CPC G06F3/0655
- CPC G06F3/0659
- G06F12/0811
- G06F9/50
- CPC G06F9/505
- G06F11/10
- CPC G06F11/1004
- G06F11/07
- CPC G06F11/1016
- CPC G06F11/1068
- CPC G06F11/1076
- G06F11/32
- CPC G06F11/3089
- G11C29/44
- CPC G06F12/0223
- CPC G06F12/0246
- G06F12/0802
- CPC G06F12/0802
- G06F13/12
- G06F13/24
- CPC G06F13/124
- CPC G06F13/1684
- G11C5/14
- H04L25/03
- CPC G11C5/147
- G11C7/10
- CPC G11C7/1063
- G11C7/16
- G11C7/12
- G11C8/08
- CPC G11C7/16
- G11C11/408
- G11C11/4091
- G11C11/4097
- H10B12/00
- CPC G11C11/4085
- G11C13/00
- H01L23/528
- CPC G11C13/0007
- G11C19/08
- G11B5/49
- G11C11/14
- G11C11/16
- H10N50/01
- H10N50/80
- CPC G11C19/0808
- G11C29/52
- G11C29/00
- CPC G11C29/52
- G11C16/04
- H10B41/10
- H10B41/20
- H10B43/10
- H10B43/20
- CPC H01L23/5283
- H01L23/00
- H01L23/31
- H01L23/498
- H01L25/00
- H01L25/065
- H10B80/00
- CPC H01L24/32
- G11C5/02
- G11C5/10
- G11C11/407
- CPC H10B12/30
- G11C11/22
- H10B53/10
- H10B53/30
- CPC H10B12/315
- H10B43/27
- H10B43/50
- CPC H10B43/27
- CPC H10B53/30