Micron Technology, Inc. patent applications on April 3rd, 2025
Patent Applications by Micron Technology, Inc. on April 3rd, 2025
Micron Technology, Inc.: 25 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (5), G06F11/10 (4), G11C29/52 (2), G11C29/00 (2), G06Q50/47 (2) F16L3/1058 (1), G06F21/554 (1), H03M13/1111 (1), H01L23/5283 (1), H01L23/36 (1)
With keywords such as: memory, data, read, bit, device, based, portion, metadata, value, and error in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20250109805. VARIABLE ROUTING CLAMP_simplified_abstract_(micron technology, inc.)
Inventor(s): Cristofer Anthony FARNETTI of Boise ID US for micron technology, inc., Maxwell Lewis BENNETT of Boise ID US for micron technology, inc.
IPC Code(s): F16L3/10
CPC Code(s): F16L3/1058
Abstract: implementations described herein relate to a variable routing clamp. in some implementations, a routing clamp may include a rigid body defining a channel. the routing clamp may include a flexible cushion that is configured to be inserted into the channel, where the flexible cushion includes two or more through holes extending through the flexible cushion that are configured to receive flexible lines, and where distances between the two or more through holes satisfy a threshold. the routing clamp may include a rigid cap that is configured to be fastened to the rigid body over an opening of the channel, where the rigid cap includes one or more lips that are configured to restrict movement of the flexible cushion after the flexible cushion is inserted into the channel.
Inventor(s): Mohad Baboli of Boise ID US for micron technology, inc., John Hopkins of Meridian ID US for micron technology, inc.
IPC Code(s): G01C21/34, B60W60/00, G06Q30/0251, G06Q30/0273, G06Q50/47
CPC Code(s): G01C21/3484
Abstract: a system and method for optimizing routes for an autonomous vehicle ride service based on business promotions and incentives. a vehicle routing service identifies multiple possible routes between a rider's pick-up and drop-off locations that meet time and distance requirements. for each route, an expected monetary value is calculated based on promotions from businesses located near the route. businesses provide promotions with bid values via an integrated promotion management platform. the route with the highest expected value based on associated promotion bid values is selected and provided to the autonomous vehicle. promotion content is transmitted to vehicle displays or the rider's mobile device. the rider can accept offers to re-route to a business. the system continually evaluates new promotions for additional revenue opportunities. by optimizing routes based on promotions and incentives, the system maximizes value for riders, businesses, and the ride service.
Inventor(s): Sujeet Ayyapureddi of Boise ID US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/061
Abstract: apparatuses, systems, and methods for bounded fault compliant metadata storage. a memory module may be capable of repairing information along a portion of the data terminals of a memory device. to prevent errors in the metadata from propagating across more than the correctable portion, the metadata may be provided along a portion of the data terminals, while the data associated with that metadata is provided along more data terminals. for example, in a 9�2p2 module the data may use two terminals, while the metadata only uses one. in a 5�2p4 module, the metadata may use a pair of terminals, while the data uses four.
Inventor(s): Mariano Eduardo Burich of San Diego CA US for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA US for micron technology, inc., Mustafa N. Kaynak of San Diego CA US for micron technology, inc., Eyal En Gad of Santa Clara CA US for micron technology, inc., Phong S. Nguyen of Livermore CA US for micron technology, inc., Dung Viet Nguyen of San Jose CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a soft input is obtained from a sense word corresponding to encoded host data read from the memory device and decoded using a parity-check matrix. a match array is maintained. each iteration of an error correcting code operation a number of unsatisfied check nodes of a respective bit of the sense word is calculated for each bit of the sense word. a bit flip threshold from a threshold data structure is obtained based on a current iteration of the error correcting code operation, a soft bit associated with the respective bit, and a match bit associated with the respective bit. the respective bit is flipped based on the number of unsatisfied check nodes satisfying the bit flip threshold.
Inventor(s): Sundararajan Sankaranarayanan of Fremont CA US for micron technology, inc., Sampath Ratnam of San Jose CA US for micron technology, inc., Jiangang Wu of Milpitas CA US for micron technology, inc., Chandra Mouli Guda of Fremont CA US for micron technology, inc., Steven R. Brown of Boise ID US for micron technology, inc., Ashutosh Malshe of Fremont CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: the disclosure configures a memory sub-system controller to store random data in a different layout from sequential data. the controller receives a request to store a set of data to a set of memory components. the controller determines whether the set of data corresponds to either sequential data or random data and selects a write cursor from a plurality of write cursors to associate with the set of data in response to determining whether the set of data corresponds to the sequential data or the random data. the controller programs the set of data to one or more of the set of memory components according to a data layout associated with the selected write cursor.
Inventor(s): Sujeet Ayyapureddi of Boise ID US for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1008
Abstract: apparatuses, systems, and methods for read/modify/write single-pass metadata access operations. during a write a memory receives data bits and at least one metadata bit and a column address which includes column select bits and column sub-select bits. a column decoder selects a set of bit lines in an extra column plane based on the column select bits and a set of bits is read out. a subset of that set of bits is selected based on the column sub-select bits and overwritten with the at least one metadata bit. the modified set of bits is written back to the extra column plane.
Inventor(s): Zhengang Chen of San Jose CA US for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1016
Abstract: a processing device in a memory sub-system identifies a plurality of read retry offset voltages having respective check-fail bit counts that are within a target check-fail bit count range for a programming level of a memory device, performs one or more auto-read calibration operations for each of the plurality of read retry offset voltages, and determines respective syndrome weights for sense words read from the memory device using each of the plurality of read retry offset voltages. the processing device further identifies a read retry offset voltage of the plurality of read retry offset voltages having a lowest respective syndrome weight, and performs an error recovery operation using the identified read retry offset voltage.
20250110827. CONCURRENT READ ERROR HANDLING OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Chung Lien of San Jose CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for concurrent read error handling operations are described. a system may perform a read error handling procedure in which operations may be performed concurrently or in succession. for example, a second read operation may be initiated while error control is being performed for a first read operation, or while data from the first read operation is being transferred to a controller. further, the second read operation may be terminated based on identifying one or more errors in the data from the first read operation, such that the read error handling procedure may be terminated without finishing active processes of the read error handling procedure. additionally, the system may be configured to perform the read error handling procedure such that a channel activation operation and a channel deactivation operation may be performed at the beginning and end of the read error handling procedure, respectively.
Inventor(s): Sujeet Ayyapureddi of Boise ID US for micron technology, inc.
IPC Code(s): G06F11/10, G06F13/16
CPC Code(s): G06F11/1072
Abstract: apparatuses, systems, and methods for alternate memory die metadata storage. a memory module includes a number of memory devices. a controller writes data and metadata to the module. the data is stored in the memory devices, while the metadata is stored in a selected portion of the memory devices. the selected portion of the memory devices may use separate write enable signals to protect bit lines which the metadata is not being written to.
Inventor(s): Lu Tong of Woodlands SG for micron technology, inc., Ashish Ghai of Saratoga CA US for micron technology, inc., Chai Chuan Yao of Woodlands SG for micron technology, inc., Ekamdeep Singh of San Jose CA US for micron technology, inc., Lakshmi Kalpana Vakati of San Jose CA US for micron technology, inc., Sheng Huang Lee of Meridian ID US for micron technology, inc., Matthew Ivan Warren of Meridian ID US for micron technology, inc., Dheeraj Srinivasan of San Jose CA US for micron technology, inc., Jeffrey Ming-Hung Tsai of San Jose CA US for micron technology, inc.
IPC Code(s): G06F11/20, G06F3/06
CPC Code(s): G06F11/2023
Abstract: control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. the control logic identify a subset of memory blocks of one or more memory planes that pass a program count operation associated with a last programming level of the set of programming levels. the control logic further terminates execution of the programming operation on the one or more memory planes associated with the subset of memory blocks.
Inventor(s): Salvatore Comitato of San Nicola La Strada IT for micron technology, inc., Felice Cosenza of Palma Campania IT for micron technology, inc., Graziano Leone of Orta Di Atella IT for micron technology, inc., Lucia Santojanni of Napoli IT for micron technology, inc., Nicola Colella of Capodrise IT for micron technology, inc.
IPC Code(s): G06F11/263, G06F11/22
CPC Code(s): G06F11/263
Abstract: devices and techniques for estimating lifelong data traffic of a memory device are described herein. a system includes a processing device and memory configured to store instructions to perform operations comprising: receiving a history of memory accesses to a device under test during execution of an application; identifying a partition size associated with the application; determining an address offset value based on the partition size and the application; and repeatedly applying the memory accesses over a number of iterations, the application of the memory accesses constrained to the partition size, and the memory accesses applied with each iteration beginning at an address based on a multiple of the address offset value to produce an estimation of data traffic.
Inventor(s): Alex Frolikov of San Jose CA US for micron technology, inc.
IPC Code(s): G06F12/02, G06F3/06, G06F12/0811, G06F12/0884
CPC Code(s): G06F12/0246
Abstract: a computer storage device having a host interface, a controller, non-volatile storage media, and firmware. the firmware instructs the controller to: generate mapping data defining mapping, from logical block addresses in namespaces configured on the non-volatile storage media, to logical block addresses in a capacity of the non-volatile storage media; maintain an active copy of the mapping data; generate cached copies of the mapping data from the active copy; generate a shadow copy from the active copy; implement changes in the shadow copy; after the changes are made in the shadow copy, activate the shadow copy and simultaneously deactivate the previously active copy; and update the cached copies according to the newly activated copy, as a response to the change in active copy identification.
Inventor(s): Steven Jeffrey Wallach of Dallas TX US for micron technology, inc.
IPC Code(s): G06F12/0842
CPC Code(s): G06F12/0842
Abstract: a computing system, method and apparatus to cache a portion of a data block. a processor can access data using memory addresses in an address space. a first memory can store a block of data at a block of contiguous addresses in the space of memory address. a second memory can cache a first portion of the block of data identified by an item selection vector. for example, response to a request to cache the block of data stored in the first memory, the computing system can communicate the first portion of the block of data from the first memory to the second memory according to the item selection vector without accessing a second portion of the block of data. thus, different data blocks in the first memory of a same size can be each cached in different cache blocks of different sizes in the second memory.
Inventor(s): Yunyoung Lee of Meridian ID US for micron technology, inc., Yuan He of Boise ID US for micron technology, inc.
IPC Code(s): G06F21/55
CPC Code(s): G06F21/554
Abstract: memory devices direct refresh management (drfm) attack identification. a drfm logic circuit receives drfm aggressor address and compares it to a previous drfm aggressor address. if there is not a match, then a drfm operation is performed. if there is a match, then the drfm operation may be skipped. this may prevent repeated drfm operations from being performed on a same drfm aggressor address.
Inventor(s): Mohad Baboli of Boise ID US for micron technology, inc., John Hopkins of Meridian ID US for micron technology, inc.
IPC Code(s): G06Q20/10, G06Q10/02, G06Q10/0639, G06Q30/0283, G06Q50/47, G06V20/59, G06V40/20, H04L43/0876, H04L67/50
CPC Code(s): G06Q20/10
Abstract: a system and method for determining a ride fare for a ride in a network-connected autonomous vehicle is disclosed. the system may divide an overall ride fare between the rider, and the enterprise or company at which the rider is employed, where the amounts allocated to each are dependent upon a productivity metric indicating a measure of the work performed by the rider during the ride. accordingly, the system receives a ride request over a network and calculates an overall ride fare using ride parameters. at the ride's conclusion, the system receives a productivity metric indicating rider productivity enabled by the vehicle's virtual work environment. the system uses the productivity metric to calculate a portion of the overall fare allocated to the rider's account. the virtual environment may include network connectivity, input devices, displays, and cloud-based productivity software. a productivity sensing system generates the productivity metric by monitoring network traffic, or monitoring software application interactions.
Inventor(s): Abhishek Chaurasia of Redmond WA US for micron technology, inc., Katya B. Giannios of West Lafayette IN US for micron technology, inc.
IPC Code(s): G06T7/10, G06N3/045
CPC Code(s): G06T7/10
Abstract: a system, method and apparatus of image segmentation with semi supervised training of an artificial neural network using coarse labels. for example, a first artificial neural network is trained to perform image segmentation on first images according to fine labels of image segmentation for the first images and to perform image segmentation on second images according to coarse labels of image segmentation for the second images. after the training, the first artificial neural network is used to perform image segmentation of the second images to identify improved labels of image segmentation for the second images. subsequently, a supervised machine learning technique can be used to train a second artificial neural network to perform image segmentation on the first images according to fine labels and on the second images according to the improved labels.
Inventor(s): Wonjun Choi of Boise ID US for micron technology, inc., Hyun Yoo Lee of Boise ID US for micron technology, inc.
IPC Code(s): G11C11/406
CPC Code(s): G11C11/40626
Abstract: apparatuses, systems, and methods for refresh rate register adjustment based on a targeted refresh queue. a memory includes a temperature sensor which measures a temperature of the memory. the memory also includes a targeted refresh queue which stores identified aggressor addresses. a value of a refresh rate register is set based on both the measured temperature and the number of addresses in the queue. a controller of the memory reads the value of the refresh rate register and provides a refresh signal with timing based on the refresh rate register. in some embodiments, a ratio of targeted and normal refresh operations is adjusted based on how many addresses are in the targeted refresh queue.
Inventor(s): Tomoko Ogura Iwasaki of San Jose CA US for micron technology, inc., Manik Advani of Fremont CA US for micron technology, inc., Ramin Ghodsi of San Jose CA US for micron technology, inc.
IPC Code(s): G11C29/42, G11C15/04, G11C29/12, G11C29/20
CPC Code(s): G11C29/42
Abstract: a memory device includes a content addressable memory (cam) block storing a plurality of stored search keys. the memory device further includes control logic that determines a first number of memory cells in at least one string of the cam block storing one of the plurality of stored search keys, the first number of memory cells storing a first logical value, and stores a calculated parity value representing the first number of memory cells in a page cache associated with the cam block. the control logic further reads stored parity data from one or more memory cells in the at least one string, the one or more memory cells connected to one or more additional wordlines in the cam block, and compares the calculated parity value to the stored parity data to determine whether an error is present in the one of the plurality of stored search keys in the cam block.
20250111886. READ WINDOW MANAGEMENT IN A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Li-Te Chang of San Jose CA US for micron technology, inc., Murong Lang of San Jose CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc., Ting Luo of Santa Clara CA US for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/00, G11C29/50
CPC Code(s): G11C29/52
Abstract: methods, systems, and devices for read window management in a memory system are described. a memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. the memory system may then use the first value for the read window to predict a second value for the read window. based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. the memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.
Inventor(s): Sujeet Ayyapureddi of Boise ID US for micron technology, inc.
IPC Code(s): G11C29/00, G11C7/08, G11C29/02, G11C29/52
CPC Code(s): G11C29/789
Abstract: apparatuses, systems, and methods for separate write enable signals for granular single pass metadata access operations. during an example write operation a memory may receive data bits and at least one metadata bit. a set of bit lines in a first column plane is selected and a first write enable signal is provided which enables writing data to each of that set of bit lines. a second set of bit lines in a second column plane is selected and a second write enable signal is provided which enables writing the at least one metadata bit to a selected subset of the second set of bit lines.
[[20250112086. Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-on-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry_simplified_abstract_(micron technology, inc.)]]
Inventor(s): David H. Wells of Boise ID US for micron technology, inc.
IPC Code(s): H01L21/764, H01L21/02, H01L21/20
CPC Code(s): H01L21/764
Abstract: some embodiments include methods of forming voids within semiconductor constructions. in some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
Inventor(s): Chan H. Yoo of Boise ID US for micron technology, inc., Owen R. Fay of Meridian ID US for micron technology, inc.
IPC Code(s): H01L23/36, H01L23/00, H01L23/42, H01L23/498, H01L25/00, H01L25/065, H01L25/10, H05K7/20
CPC Code(s): H01L23/36
Abstract: semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. a semiconductor assembly may comprise a supporting structure and a device with a thermal management layer disposed between the supporting structure and the device. the thermal management layer may be configured to reduce heat transfer between the supporting structure and the device.
Inventor(s): Si-Woo Lee of Saratoga CA US for micron technology, inc., Scott E. Sills of Boise ID US for micron technology, inc., Yuichi Yokoyama of Boise ID US for micron technology, inc.
IPC Code(s): H01L23/528, H01L23/532, H10B12/00
CPC Code(s): H01L23/5283
Abstract: a microelectronic device includes a stack structure with tiers individually extending through an array area and into a staircase area horizontally neighboring the array area. the array area includes at least one access device. the staircase area includes a staircase structure having steps at ends of the tiers. at least some of the tiers individually include a conductive region, insulative regions, and discrete regions of semiconductor material. the conductive region includes conductive material extending through the array area and into the staircase area. the insulative regions are in both the array area and the staircase area. the discrete regions of semiconductor material are in the array area. the staircase area is substantially free of the semiconductor material. the conductive material is thicker in the staircase area than in the array area. related electronic systems and methods of formation are also disclosed.
Inventor(s): Sujeet Ayyapureddi of Boise ID US for micron technology, inc.
IPC Code(s): H03M13/11, H03M13/00
CPC Code(s): H03M13/1111
Abstract: apparatuses, systems, and methods for scalable 1-pass error correction code operations. a memory device includes an error correction code (ecc) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. the number of parity bits may be selected based on a setting in a mode register. the data and parity are written to the memory array as part of a single access pass. the data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.
Inventor(s): Collin Howder of Boise ID US for micron technology, inc., M. Jared Barclay of Middleton ID US for micron technology, inc., Bhavesh Bhartia of Singapore SG for micron technology, inc., Chet E. Carter of Boise ID US for micron technology, inc., John D. Hopkins of Meridian ID US for micron technology, inc., Andrew Li of Boise ID US for micron technology, inc., Haoyu Li of Boise ID US for micron technology, inc., Alyssa N. Scarbrough of Boise ID US for micron technology, inc., Grady S. Waldo of Boise ID US for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. the channel-material strings directly electrically couple with conductor material of the conductor tier. the conductive tiers individually comprise a horizontally-elongated conductive line. a second vertical stack is aside the first vertical stack. the second vertical stack comprises an upper portion and a lower portion. the upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. the lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. other embodiments, including method, are disclosed.
Micron Technology, Inc. patent applications on April 3rd, 2025
- Micron Technology, Inc.
- F16L3/10
- CPC F16L3/1058
- Micron technology, inc.
- G01C21/34
- B60W60/00
- G06Q30/0251
- G06Q30/0273
- G06Q50/47
- CPC G01C21/3484
- G06F3/06
- CPC G06F3/061
- CPC G06F3/0655
- CPC G06F3/0659
- G06F11/10
- CPC G06F11/1008
- CPC G06F11/1016
- G06F11/07
- CPC G06F11/1068
- G06F13/16
- CPC G06F11/1072
- G06F11/20
- CPC G06F11/2023
- G06F11/263
- G06F11/22
- CPC G06F11/263
- G06F12/02
- G06F12/0811
- G06F12/0884
- CPC G06F12/0246
- G06F12/0842
- CPC G06F12/0842
- G06F21/55
- CPC G06F21/554
- G06Q20/10
- G06Q10/02
- G06Q10/0639
- G06Q30/0283
- G06V20/59
- G06V40/20
- H04L43/0876
- H04L67/50
- CPC G06Q20/10
- G06T7/10
- G06N3/045
- CPC G06T7/10
- G11C11/406
- CPC G11C11/40626
- G11C29/42
- G11C15/04
- G11C29/12
- G11C29/20
- CPC G11C29/42
- G11C29/52
- G11C29/00
- G11C29/50
- CPC G11C29/52
- G11C7/08
- G11C29/02
- CPC G11C29/789
- H01L21/764
- H01L21/02
- H01L21/20
- CPC H01L21/764
- H01L23/36
- H01L23/00
- H01L23/42
- H01L23/498
- H01L25/00
- H01L25/065
- H01L25/10
- H05K7/20
- CPC H01L23/36
- H01L23/528
- H01L23/532
- H10B12/00
- CPC H01L23/5283
- H03M13/11
- H03M13/00
- CPC H03M13/1111
- H10B43/27
- H10B41/27
- CPC H10B43/27
