MICRON TECHNOLOGY, INC. patent applications on April 10th, 2025
Patent Applications by MICRON TECHNOLOGY, INC. on April 10th, 2025
MICRON TECHNOLOGY, INC.: 47 patent applications
MICRON TECHNOLOGY, INC. has applied for patents in the areas of G06F3/06 (12), G11C7/10 (4), G11C16/08 (3), G11C11/4091 (3), G11C5/06 (3) G11C11/4091 (3), G06F3/0653 (2), G06F3/0655 (2), G06F3/0659 (2), G11C7/222 (2)
With keywords such as: memory, data, cells, device, some, devices, respective, cell, methods, and coupled in patent application abstracts.
Patent Applications by MICRON TECHNOLOGY, INC.
Inventor(s): Jay Sarkar of San Jose CA US for micron technology, inc., David Scott Ebsen of Minnetonka MN US for micron technology, inc., Aaron Lucas of Boulder CO US for micron technology, inc., Seyhan Karakulak of San Jose CA US for micron technology, inc., Saeed Sharifi Tehrani of San Diego CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. the processing device can perform operations including identifying a set of logical addresses associated with data stored on the memory devices in one or more blocks of a first type; determining a temporal metric class associated with the set of logical addresses, wherein the temporal metric class is associated with a corresponding range of predicted update characteristic of the data; identifying, based on the temporal metric class, a set of blocks of a second type, wherein a first block of the first type comprises a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type comprises a second plurality of memory cells having a second number of bits per cell that exceeds the first number of bits per cell; and moving the data to the identified set of blocks.
20250117143. REDUCED POWER ADDRESSING_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA US for micron technology, inc., Leonid Minz of Bear Sheva IL for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: an intermediate component can be provided between initiator components (from which access requests are originated) and target components (that are to be accessed via the access requests). the intermediate component can encode, decode, and/or bypass the encoding process of address bits to ensure that address bits of the access requests are in a format that is compatible with access of the respective target component.
Inventor(s): Steven Michael Kientz of Westminster CO US for micron technology, inc., Chia-Yu Kuo of Hukou Town TW for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0644
Abstract: an example method of threshold voltage offset calibration at memory device power up comprises: identifying a set of memory pages that have been programmed within a time window; determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages; identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion; selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and associating the set of memory pages with the selected voltage offset bin.
Inventor(s): Deping He of Boise ID US for micron technology, inc., Nadav Grosz of Broomfield CO US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: methods, systems, and devices for data transfer during maintenance operations are described. a memory system utilize an auto-suspend feature to parallelize aspects of maintenance operations. for example, the memory system may suspend a programming operation being performed on a first block of memory cells. the memory system may read data from a second block of memory cells while the programming operation is suspended, and may transfer the data from the second block of memory cells (e.g., to a controller) in parallel with resuming the programming operation on the first block of memory cells. the memory system may transfer the data read from the second block of memory cells to a third block of memory cells in parallel with resuming the programming operation on the first block of memory cells.
20250117153. OPTIMIZED COMMAND QUEUES WITH LOW LATENCY_simplified_abstract_(micron technology, inc.)
Inventor(s): Bryan Dale Hornung of Plano TX US for micron technology, inc., Tony Brewer of Plano TX US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: a system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: monitoring a host command stream from a host system to the memory device; determining whether a phase value of a host command in the host command stream is valid; responsive to determining that the phase value of the host command is valid, copying the host command; storing the copied host command in a queue in a local memory; and executing the copied host command in the queue in the local memory.
Inventor(s): David Andrew Roberts of Wellesley MA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: a host system includes a memory and a processing device coupled to the memory to perform operations including obtaining log data from a memory sub-system of a plurality of memory sub-systems, wherein the log data reflects memory usage of a memory device of the memory sub-system, wherein the memory device is shared by the plurality of host systems, including the host system, connected to the plurality of memory sub-systems; and determining, based on the log data, a schedule of a plurality of processes running on the plurality of host systems, wherein the plurality of processes share the memory device.
20250117156. SEQUENTIALIZING DATA OF A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): David Aaron Palmer of Boise ID US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: in accordance with examples as described herein, a memory system may initialize a data optimization operation by transmitting signaling to a host system. for example, the memory system may identify data associated with non-sequential logical block addresses (lbas), and may indicate the discontinuous lbas to the host system. in response, the host system may indicate which of the discontinuous lbas represent sequential data. accordingly, the memory system may sequentialize the one or more of the discontinuous lbas to defragment the associated data.
Inventor(s): Giovanni Maria Paolucci of Milan IT for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: an example memory device includes a memory array and processing logic to perform operations including: identifying, among a plurality of memory cells of the memory array, a target memory cell and a set of memory cells adjacent to the target memory cell, such that each memory cell of the set of memory cells is characterized by a respective memory cell state; determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins; and determining a set of read level offsets for reading the target memory cell, such that each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins.
Inventor(s): Liang Yu of Boise ID US for micron technology, inc., Jonathan S. Parry of Boise ID US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for techniques for staggering data burst events across channels are described. a memory system may offset data transfer events over multiple channels with a timing delay between data transfers over respective channels. for example, the memory system may initiate a first data transfer over a first channel at a first time and implement a timing delay before a second data transfer over a second channel at a second time such that the second time occurs after the first time. in some cases, the memory system may initiate one data transfer over each respective channel at a time, and in some cases, the memory system may initiate two or more data transfers over respective channels at a same time. in some cases, each channel may be associated with a respective timing delay.
20250117163. PERFORMANCE TUNING FOR A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Liang Ge of Shanghai CN for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for performance tuning for a memory device are described. in some examples, a memory system may receive a command (e.g., a read command or a write command) that includes an indicator. the indicator may instruct the memory system to suppress one or more portions of the command. for example, the command may be received by an interface of the memory system and the controller may instruct the memory system to suppress one or more operations performed by a processor of the memory system, a storage controller of the memory system, or both. upon suppressing one or more operations associated with the command, the memory system may output a response to the test system, which may allow for the test system to tune one or more performance aspects of the memory system.
20250117209. FIRMWARE VALIDATION FOR FIRMWARE UPDATES_simplified_abstract_(micron technology, inc.)
Inventor(s): Niccolò Izzo of Vignate IT for micron technology, inc., Alessandro Orlando of Milano IT for micron technology, inc., Danilo Caraccio of Milano IT for micron technology, inc.
IPC Code(s): G06F8/65, G06F21/57, H04L9/08
CPC Code(s): G06F8/65
Abstract: methods, systems, and devices related to firmware validation for firmware updates are disclosed. a controller can, in association with a firmware update of a memory module: determine whether first security information and first customer information of a manifest of a firmware package are valid using second security information and second customer information, respectively, stored by a non-volatile memory device of the memory module; determine whether a first public key of a first image of the firmware package is valid using a second public key of the manifest corresponding to the first image and associated with the first security information and the first customer information; and determine whether a third public key of a second image of the firmware package is valid using a fourth public key of the manifest corresponding to the second image and associated with the first security information and the first customer information.
20250117273. INDICATING DATA CORRUPTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Casto Salobrena Garcia of Munich DE for micron technology, inc., Marcos Alvarez Gonzalez of München DE for micron technology, inc., Michael Dieter Richter of Ottobrunn DE for micron technology, inc., Thomas Hein of München DE for micron technology, inc., Ronny Schneider of Höhenkirchen-Siegertsbrunn DE for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0751
Abstract: methods, systems, and devices for indicating data corruption are described. a memory system may be configured to identify and store corrupted data received from a host system without storing metadata. as part of transmitting a bulk transmission, the host system may transmit first data to be stored at an address of the memory system, and a first indication identifying that the first data is corrupted. the memory system may generate second data with a pattern of bits indicating that data stored at the address of the memory system is corrupted. the memory system may store the second data to the address, and later retrieve the second data in response to receiving a read command from the host system. then, the memory system may generate a second indication identifying that the second data is corrupted, and transmit the second data and the second indication to the host system.
20250117289. VALLEY CHECK MEMORY SYSTEM COMMAND_simplified_abstract_(micron technology, inc.)
Inventor(s): Charles S. Kwong of Redwood City CA US for micron technology, inc., Seungjune Jeon of Santa Clara CA US for micron technology, inc., Jun Wan of San Jose CA US for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: aspects of the present disclosure configure a system component, such as memory sub-system controller, to detect read errors in one or more memory cells using a plurality of read thresholds. the controller selects, for inspection, a target valley of a plurality of valleys associated with an individual memory component of the set of memory components. the controller reads the target valley using a first read threshold to obtain a first set of data and reads the target valley using a second read threshold to obtain a second set of data. the controller compares the first set of data to the second set of data and performs one or more memory operations on the target valley in response to comparing the first set of data to the second set of data.
Inventor(s): Deping He of Boise ID US for micron technology, inc., Wenjun Wu of Shanghai CN for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/06
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for compression-based address mapping management in a memory system are described. a memory system may reduce a quantity of times regions of an address mapping table are transferred between a non-volatile memory and a local memory of the memory system. the memory system may selectively retain regions of the address mapping table in local memory in-between checkpoint procedures. during a checkpoint procedure, the memory system may compress the regions of the address mapping table in the local memory and, if the regions are sufficiently compressible, may keep the regions in the local memory until the next checkpoint procedure.
20250117322. SEGREGATING LOGICAL TO PHYSICAL MAPPINGS_simplified_abstract_(micron technology, inc.)
Inventor(s): Ritesh Tiwari of Bangalore IN for micron technology, inc., Giuseppe Cariello of Boise ID US for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for segregating logical to physical mappings are described. a memory system may segregate l2p mappings based on one or more characteristics of the data associated with to the l2p mappings. the memory system may determine whether a logical address included in a write command is associated with a first characteristic, a second characteristic, or some other characteristic. the memory system may write an l2p mapping to a first block of memory cells, a second block of memory cells, or some other block of memory cells based on the determined characteristic of the l2p mapping. the block of memory cells that the l2p mapping is written to may include other mappings having data with a same (or similar) characteristic.
20250117331. LOADING DATA IN A TIERED MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Sudharshan Sankaran Vazhkudai of Austin TX US for micron technology, inc., Moiz Arif of Rochester NY US for micron technology, inc., Kevin Assogba of Rochester NY US for micron technology, inc., Muhammad Mustafa Rafique of Rochester NY US for micron technology, inc.
IPC Code(s): G06F12/0862
CPC Code(s): G06F12/0862
Abstract: methods, systems, and devices for loading data in a tiered memory system are described. a respective allocation of computing resources may be determined for each node in a cluster, where at least one of the nodes may include multiple memory tiers, and a data set to be processed by the nodes may be analyzed. based on the allocation of computing resources and the analysis of the data set, respective data processing instructions indicating respective portions of the data set to be processed by respective nodes may be generated and sent to the respective nodes. the respective data processing instructions may also indicate a respective distribution of subsets of the respective portions of the data set across the multiple memory tiers at the respective nodes.
Inventor(s): Keun-Soo Song of Yokohama JP for micron technology, inc.
IPC Code(s): G06F13/16
CPC Code(s): G06F13/1689
Abstract: disclosed are methods, systems, and apparatuses for semiconductor memory devices (e.g., dynamic random access memory (dram)) that include a command/address inversion (cai) input signal indicating whether command/address inputs to the memory devices are inverted. the cai input signal may be generated by a memory controller, a registering clock driver (rcd), or other component coupled to the memory devices, and the component may generate the cai input signal differently for the different memory devices to which the component is coupled. as described herein, the component may dynamically generate the cai input signal based on the values of the command/address inputs so as to reduce power consumption by the memory devices while retaining signal integrity.
Inventor(s): Poorna Kale of Folsom CA US for micron technology, inc., Jaime Cummins of Bainbridge Island WA US for micron technology, inc.
IPC Code(s): G06N3/08, G06N5/04
CPC Code(s): G06N3/08
Abstract: systems, devices, and methods related to a deep learning accelerator and memory are described. an integrated circuit may be configured with: a central processing unit, a deep learning accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an artificial neural network executable by the deep learning accelerator and second instructions of an application executable by the central processing unit; one or connections among the random access memory, the deep learning accelerator and the central processing unit; and an input/output interface to an external peripheral bus. while the deep learning accelerator is executing the first instructions to convert sensor data according to the artificial neural network to inference results, the central processing unit may execute the application that uses inference results from the artificial neural network.
Inventor(s): Alyssa N. Scarbrough of Boise ID US for micron technology, inc.
IPC Code(s): G06T19/00, G06Q50/10
CPC Code(s): G06T19/006
Abstract: systems and methods for determining an activity for first and second subgroups at a venue are disclosed including receiving information from a user interface of a user device associated with a group of users, determining a first estimated time for a first activity for the first subgroup, evaluating a plurality of activities to determine at least one of a second activity for the second subgroup or a third activity for the group proceeding the first and second activities to reduce an idle time of the group before the third activity, including using the determined first estimated time for the first activity for the first subgroup, and causing information about the determined second activity or the determined third activity to be displayed on a user experience application associated with the group.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID US for micron technology, inc., Mingdong Cui of Folsom CA US for micron technology, inc., Richard E. Fackenthal of Carmichael CA US for micron technology, inc.
IPC Code(s): G11C5/02, G11C5/06, G11C8/14, H10B12/00
CPC Code(s): G11C5/025
Abstract: methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. a memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. for example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.
Inventor(s): Dean E. Walker of Allen TX US for micron technology, inc., Tony Brewer of Plano TX US for micron technology, inc.
IPC Code(s): G06F9/4401
CPC Code(s): G11C7/1006
Abstract: a method includes setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets; and programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet.
Inventor(s): Stephen Hanna of Fort Collins CO US for micron technology, inc., Jonathan S. Parry of Boise ID US for micron technology, inc.
IPC Code(s): G11C7/10, G11C29/52
CPC Code(s): G11C7/1096
Abstract: methods, systems, and devices for serial pass-through techniques for memory device interfaces are described. memory interface circuitry may be configured to receive a command via a first interface having a first set of terminals to configure the memory interface circuitry for a pass-through mode. as part of the pass-through mode, the memory interface circuitry may receive data from an external device via the first interface and output the data to one or more memory devices via a second interface having a second set of terminals. in some examples, the received data may be associated with a write burst, in which the memory interface circuitry may serially receive multiple portions of the data to write to a buffer of the memory interface circuitry. after reaching a threshold quantity of data, the buffer may output the portions of the data to the one or more memory devices via the second interface.
Inventor(s): Hideo Shimizu of Sagamihara JP for micron technology, inc., Yutaka Uemura of Sagamihara JP for micron technology, inc.
IPC Code(s): G11C7/22, G11C7/10
CPC Code(s): G11C7/222
Abstract: an example apparatus includes a data bus including a first portion having a timing domain which is controlled based on a first timing signal and further including a second portion having a timing domain which is controlled based on a second timing signal, and a data transfer circuit coupled to the data bus, the data transfer circuit including a data driver between the first portion of the data bus and the second portion of the data bus and a timing control circuit coupled to the data driver. the timing control circuit includes a variable delay to add an amount of delay to a first control signal to generate a second control signal. the data driver is configured to drive data from the second portion of the data bus to the first portion of the data bus responsive to the second control signal.
Inventor(s): Leon Zlotnik of Camino CA US for micron technology, inc.
IPC Code(s): G11C7/22, G11C7/10
CPC Code(s): G11C7/222
Abstract: an example method can include performing a first sensing operation associated with circuitry on a system on chip (soc) to determine a first data value, performing a second sensing operation associated with circuitry of a sensor the soc to determine a second data value, responsive to the first data value and the second data value being the same data value, determining that a clock margin is sufficient, and responsive to the first data value and the second data value being different data values, determining that a clock margin is insufficient. in some examples, a voltage-frequency operating combination associated with at least one operation of the soc can be adjusted to a particular stored voltage-frequency operating combination that provides a sufficient clocking margin.
Inventor(s): Randall J. Rooney of Boise ID US for micron technology, inc., Jeremy Chritz of Seattle WA US for micron technology, inc.
IPC Code(s): G11C11/406
CPC Code(s): G11C11/406
Abstract: a controller performs an access operation on a word line which is in a portion of a memory array in a memory device. the controller counts accesses on a portion-by-portion basis (e.g., a bank-by-bank basis, a sub-bank-by-sub-bank basis, etc.). the memory counts accesses on a word line-by-word line basis. the memory sets a refresh management (rfm) flag for a portion based on the counts associated with the word lines in that portion. the controller checks the rfm flag for a portion based on the access count for the portion. the controller issues an rfm command after checking the rfm flag if the rfm flag is set.
Inventor(s): Yang Lu of Boise ID US for micron technology, inc., Michael A. Shore of Boise ID US for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/4093
CPC Code(s): G11C11/4091
Abstract: single (1t) and multi (mt) memory cell architectures may be included in a same memory array. in some embodiments, the individual memory cells of the mt memory cells may have a same polarity. in some embodiments, the individual memory cells of the mt memory cells may have complementary polarity. in some examples, digit lines at memory mats and edge memory mats may be folded for mt memory cells. in some examples, digit lines may be rerouted through local input-output line breaks for the mt memory cells. in some examples, the lio lines from the mt memory cells may be twisted. in some examples, larger sense amplifiers may be used for the mt memory cells.
Inventor(s): Yang Lu of Boise ID US for micron technology, inc., Toby D. Robbs of Boise ID US for micron technology, inc., Christopher J. Kawamura of Boise ID US for micron technology, inc., Kang-Yong Kim of Boise ID US for micron technology, inc.
IPC Code(s): G11C11/4091, G11C5/06, G11C11/4097
CPC Code(s): G11C11/4091
Abstract: single (1 t) and multi (mt) memory cell architectures may be included in a same memory array. in some embodiments, the individual memory cells of the mt memory cells may have a same polarity. in some embodiments, the individual memory cells of the mt memory cells may have complementary polarity. in some examples, digit lines at memory mats and edge memory mats may be folded for mt memory cells. in some examples, digit lines may be rerouted through local input-output line breaks for the mt memory cells. in some examples, the lio lines from the mt memory cells may be twisted. in some examples, larger sense amplifiers may be used for the mt memory cells.
Inventor(s): Yang Lu of Boise ID US for micron technology, inc., Song Guo of Boise ID US for micron technology, inc., Yuan He of Boise ID US for micron technology, inc., Kang-Yong Kim of Boise ID US for micron technology, inc.
IPC Code(s): G11C11/4091, G11C5/06, G11C11/4097
CPC Code(s): G11C11/4091
Abstract: single (1t) and multi (mt) memory cell architectures may be included in a same memory array. in some embodiments, the individual memory cells of the mt memory cells may have a same polarity. in some embodiments, the individual memory cells of the mt memory cells may have complementary polarity. in some examples, digit lines at memory mats and edge memory mats may be folded for mt memory cells. in some examples, digit lines may be rerouted through local input-output line breaks for the mt memory cells. in some examples, the lio lines from the mt memory cells may be twisted. in some examples, larger sense amplifiers may be used for the mt memory cells.
20250118356. APPARATUS INCLUDING CLOCK INPUT BUFFER_simplified_abstract_(micron technology, inc.)
Inventor(s): Yasuhiro Takai of Sagamihara JP for micron technology, inc., Shuichi Tsukada of Sagamihara JP for micron technology, inc.
IPC Code(s): G11C11/4093, G11C11/4076
CPC Code(s): G11C11/4093
Abstract: embodiments of the disclosure provide an apparatus comprising: first and second input transistors of a first type and first and second load transistors of a second type coupled in series, respectively; at least one resistor coupled to gate nodes of the load transistors; and first and second capacitive devices. gate nodes of the first and second input transistors are coupled to first and second inputs, respectively. the first input transistor and the first load transistor are coupled to a first output. the second input transistor and the second load transistor are coupled to a second output. the gate nodes of the first and second load transistors are coupled to a bias voltage through the resistor. the first and second capacitive devices are coupled to the first and second inputs and to the gate nodes of the first and second load transistors, respectively.
Inventor(s): Yang Lu of Boise ID US for micron technology, inc., Toby D. Robbs of Boise ID US for micron technology, inc., Christopher J. Kawamura of Boise ID US for micron technology, inc., Kang-Yong Kim of Boise ID US for micron technology, inc.
IPC Code(s): G11C11/4097, G11C7/06, G11C7/18
CPC Code(s): G11C11/4097
Abstract: single (1t) and multi (mt) memory cell architectures may be included in a same memory array. in some embodiments, the individual memory cells of the mt memory cells may have a same polarity. in some embodiments, the individual memory cells of the mt memory cells may have complementary polarity. in some examples, digit lines at memory mats and edge memory mats may be folded for mt memory cells. in some examples, digit lines may be rerouted through local input-output line breaks for the mt memory cells. in some examples, the lio lines from the mt memory cells may be twisted. in some examples, larger sense amplifiers may be used for the mt memory cells.
Inventor(s): Murong Lang of San Jose CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc., Jian Huang of Union City CA US for micron technology, inc., Tingjun Xie of Milpitas CA US for micron technology, inc., Jiangli Zhu of San Jose CA US for micron technology, inc., Nagendra Prasad Ganesh Rao of Folsom CA US for micron technology, inc., Sead Zildzic of Folsom CA US for micron technology, inc.
IPC Code(s): G11C11/56
CPC Code(s): G11C11/5628
Abstract: a difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (tu) of memory cells and a current time stamp for the open tu is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. it is determined, based on a current temperature for the open tu and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open tu is in a coarse programming state. a programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.
Inventor(s): Hong-Yan Chen of San Jose CA US for micron technology, inc., Priya Vemparala Guruswamy of Boise ID US for micron technology, inc., Pamela Castalino of Boise ID US for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA US for micron technology, inc.
IPC Code(s): G11C11/56, G11C16/08
CPC Code(s): G11C11/5635
Abstract: control logic in a memory device causes a programming pulse to be applied to a set of wordlines, where the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions. the control logic executes a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions. the control logic executes a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.
20250118366. Drift Aware Read Operations_simplified_abstract_(micron technology, inc.)
Inventor(s): Karthik Sarpatwari of Boise ID US for micron technology, inc., Nevil N. Gajera of Meridian ID US for micron technology, inc., Lingming Yang of Meridian ID US for micron technology, inc., John F. Schreck of Lucas TX US for micron technology, inc.
IPC Code(s): G06F3/06, G11C16/04, G11C16/08, G11C16/10, G11C16/24, G11C16/26
CPC Code(s): G11C13/004
Abstract: systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. the reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. in response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.
Inventor(s): Mattia Robustelli of Milano IT for micron technology, inc., Innocenzo Tortorelli of Cernusco Sul Naviglio IT for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/22, G11C16/26, G11C16/30, G11C16/32, G11C16/34
CPC Code(s): G11C16/102
Abstract: methods, systems, and devices for improving write latency and energy using asymmetric cell design are described. a memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. for example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. that is, the asymmetric memory cell design may enable an asymmetric read window budget. for example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.
Inventor(s): Tomoharu Tanaka of Yokohama JP for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/04, G11C16/08
CPC Code(s): G11C16/26
Abstract: a memory device includes an array associated with a plurality of wordlines and control logic that causes a first voltage to be applied to a first wordline associated with a selected memory cell, causes a second voltage, having a lower magnitude than the first voltage, to be applied to a second wordline adjacent to the first wordline and associated with a first neighbor memory cell, and causes a third voltage, having a lower magnitude than the first voltage, to be applied to a third wordline adjacent to the first wordline and associated with a second neighbor memory cell. the control logic identifies a first corrective read voltage in response to determining that current flows through the first and second neighbor memory cells and the selected memory cell and causes the first corrective read voltage to be applied to the first wordline during a read operation for the selected memory cell.
20250118382. MEDIA MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Donghua Zhou of Suzhou City CN for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G11C16/349
Abstract: a method includes determining a gap between a difference in a first health characteristic value and a second health characteristic value of blocks of memory cells and a health threshold associated with the blocks of memory cells, determining the gap is greater than or equal to a gap threshold from the health threshold, performing a pseudo media management operation on the blocks of memory cells, and determining an updated first health characteristic value of the blocks of memory cells.
20250118385. TESTING CIRCUIT FOR A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Chunqiang Weng of Shanghai CN for micron technology, inc., Jingwei Cheng of Shanghai CN for micron technology, inc.
IPC Code(s): G11C29/56
CPC Code(s): G11C29/1201
Abstract: methods, systems, and devices for testing circuit for a memory device are described. an apparatus may include a memory system including contacts that route signals to different regions of the memory system. the apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. the apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. the first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. the first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.
Inventor(s): Shadden Kerstetter of Kuna ID US for micron technology, inc., Raghukiran Sreeramaneni of Frisco TX US for micron technology, inc., Nevil N. Gajera of Meridian ID US for micron technology, inc., Chikara Kondo of Tokyo JP for micron technology, inc.
IPC Code(s): G11C29/36, G11C7/10
CPC Code(s): G11C29/36
Abstract: disclosed are methods, systems, and apparatuses for a memory device with test circuitry-based processing-in-memory (pim). the memory device utilizes circuitry used to control, sequence, and/or perform test functions, found on a die of the memory device (e.g., an interface die and/or memory die), to perform pim functions. for example, the memory device may utilize a memory built-in self-test (mbist) automatic pattern generator (apg) for pim sequencing. to control pim operations, the mbist apg may fetch and decode microcode instructions local to the die. the microcode instructions may be fetched from a read-only memory (rom) and/or non-volatile memory. microcode instructions to perform desired pim operations may be written to the non-volatile memory by a host device coupled to the memory device.
20250118388. METADATA STORAGE AT A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID US for micron technology, inc., Aaron P. Boehm of Boise ID US for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G11C29/42
Abstract: methods, systems, and devices for metadata storage at a memory device are described to support storage of metadata information and error control information at a memory device. the metadata information and error control information may be received at the memory device via a sideband channel and corresponding pin. for example, a set of bits received via the pin may include a subset of error control bits and a subset of metadata bits. circuitry at the memory device may receive the set of bits via the pin and may identify metadata information and error control information within the set of bits. the circuitry may route the metadata information to a corresponding subset of memory cells and the error control information to an error control circuit, where the error control circuit may route the error control information to a corresponding subset of memory cells.
Inventor(s): Manuj Nahar of Boise ID US for micron technology, inc., Ashonita A. Chavan of Boise ID US for micron technology, inc.
IPC Code(s): H10D30/69, H10B51/30, H10B53/30, H10D1/66, H10D64/68
CPC Code(s): H01G4/10
Abstract: a method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. at least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. the multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. the composite stack is subjected to a temperature of at least 200� c. after the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. after the subjecting, the composite stack is ferroelectric. conductive material is formed and that is adjacent the composite stack. devices are also disclosed.
Inventor(s): Sanh D. Tang of Boise ID US for micron technology, inc., Roger W. Lindsay of Boise ID US for micron technology, inc., Krishna K. Parat of Palo Alto CA US for micron technology, inc.
IPC Code(s): H01L23/52, G11C13/00, H01L23/528, H10B41/27, H10B41/35, H10B43/27, H10B43/35, H10B63/00, H10N70/00
CPC Code(s): H01L23/52
Abstract: a method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. the features extend horizontally though a primary portion of the stack with at least some of the features extending extend farther in the horizontal direction in an end portion. operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. the lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. other aspects and implementations are disclosed.
Inventor(s): Bharat Bhushan of Boise ID US for micron technology, inc., Kunal R. Parekh of Boise ID US for micron technology, inc., Akshay N. Singh of Boise ID US for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/768, H01L23/498, H01L25/18, H10B80/00
CPC Code(s): H01L24/08
Abstract: methods, systems, and devices for techniques for semiconductor die coupling in stacked memory architectures are described. a semiconductor system may include a semiconductor unit formed by multiple semiconductor dies, where each semiconductor die may be fabricated to be individually separable. each semiconductor die may include a respective portion of circuitry associated with the semiconductor unit. the multiple semiconductor dies may be coupled with a carrier, and each semiconductor die may be coupled (e.g., electrically, communicatively) with at least one other semiconductor die. at least some of the semiconductor dies may be coupled with a respective set of one or more memory arrays, where each memory array may be operable based on the coupling between the multiple semiconductor dies.
Inventor(s): Chan H. Yoo of Boise ID US for micron technology, inc., Owen R. Fay of Meridian ID US for micron technology, inc.
IPC Code(s): H01L25/18, H01L23/00, H01L23/48, H01L23/522, H01L25/00
CPC Code(s): H01L25/18
Abstract: a semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. the substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. the substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (cmos) circuits. the first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. a method of making a semiconductor device assembly includes applying cmos processing to a silicon substrate, forming back end of line (beol) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the beol layers, and forming a redistribution layer on the second side of the substrate.
Inventor(s): Flavio PACE of Filiano (PZ) IT for micron technology, inc., Laura FERRANTE of San Giorgio a Cremano (NA) IT for micron technology, inc., Dario BARBIERI of Casamicciola Terme (NA) IT for micron technology, inc.
IPC Code(s): H04K1/00
CPC Code(s): H04K1/00
Abstract: the disclosed embodiments relate to securely delivering firmware to memory devices. in some aspects, the techniques described herein relate to a system including: a firmware generator; a memory device; and an emulation platform, the emulation platform configured to: receive a firmware image from the firmware generator, scramble the firmware image using a scrambler module to obtain a scrambled firmware image, and transmit the scrambled firmware image to the memory device.
Inventor(s): Md Zakir Ullah of Singapore SG for micron technology, inc., Xiaosong Zhang of Boise ID US for micron technology, inc., Adam L. Olson of Boise ID US for micron technology, inc., Mohammad Moydul Islam of Singapore SG for micron technology, inc., Tien Minh Quan Tran of Singapore SG for micron technology, inc., Chao Zhu of Singapore SG for micron technology, inc., Zhigang Yang of Singapore SG for micron technology, inc., Merri L. Carlson of Boise ID US for micron technology, inc., Hui Chin Chong of Singapore SG for micron technology, inc., David A. Kewley of Boise ID US for micron technology, inc., Kok Siak Tang of Singapore SG for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. first and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. in one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. the pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. related methods are also disclosed.
Inventor(s): Lorenzo Fratin of Buccinasco IT for micron technology, inc., Paolo Fantini of Vimercate IT for micron technology, inc., Fabio Pellizzer of Boise ID US for micron technology, inc.
IPC Code(s): H10B63/00, H10N70/00, H10N70/20
CPC Code(s): H10B63/845
Abstract: methods for, apparatuses with, and vertical 3d memory devices are described. a vertical 3d memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a dielectric material positioned between the first plurality and the second plurality of word line plates, the dielectric material extending in a serpentine shape over the substrate; a plurality of pillars formed over and coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, wherein the recess is of an arch-shape, and the chalcogenide material in the recess contacts the respective word line plate.
Inventor(s): Michael J. Bernhardt of Boise ID US for micron technology, inc.
IPC Code(s): H01L33/62, H01L33/00, H01L33/06, H01L33/20, H01L33/32, H01L33/40, H01L33/42, H01L33/44
CPC Code(s): H10H20/857
Abstract: various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. in one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series. the bonding material contains nickel (ni). the method also includes placing the light emitting structure onto a silicon substrate with the bonding material in contact with the silicon substrate and annealing the light emitting structure and the silicon substrate. as a result, a nickel silicide (nisi) material is formed at an interface between the silicon substrate and the bonding material to mechanically couple the light emitting structure to the silicon substrate.
MICRON TECHNOLOGY, INC. patent applications on April 10th, 2025
- MICRON TECHNOLOGY, INC.
- G06F3/06
- CPC G06F3/0613
- Micron technology, inc.
- CPC G06F3/0625
- CPC G06F3/0644
- CPC G06F3/0647
- CPC G06F3/0653
- CPC G06F3/0655
- CPC G06F3/0659
- G06F8/65
- G06F21/57
- H04L9/08
- CPC G06F8/65
- G06F11/07
- CPC G06F11/0751
- G06F11/10
- CPC G06F11/1068
- G06F12/02
- G06F12/06
- CPC G06F12/0246
- G06F12/0862
- CPC G06F12/0862
- G06F13/16
- CPC G06F13/1689
- G06N3/08
- G06N5/04
- CPC G06N3/08
- G06T19/00
- G06Q50/10
- CPC G06T19/006
- G11C5/02
- G11C5/06
- G11C8/14
- H10B12/00
- CPC G11C5/025
- G06F9/4401
- CPC G11C7/1006
- G11C7/10
- G11C29/52
- CPC G11C7/1096
- G11C7/22
- CPC G11C7/222
- G11C11/406
- CPC G11C11/406
- G11C11/4091
- G11C11/4093
- CPC G11C11/4091
- G11C11/4097
- G11C11/4076
- CPC G11C11/4093
- G11C7/06
- G11C7/18
- CPC G11C11/4097
- G11C11/56
- CPC G11C11/5628
- G11C16/08
- CPC G11C11/5635
- G11C16/04
- G11C16/10
- G11C16/24
- G11C16/26
- CPC G11C13/004
- G11C16/22
- G11C16/30
- G11C16/32
- G11C16/34
- CPC G11C16/102
- CPC G11C16/26
- CPC G11C16/349
- G11C29/56
- CPC G11C29/1201
- G11C29/36
- CPC G11C29/36
- CPC G11C29/42
- H10D30/69
- H10B51/30
- H10B53/30
- H10D1/66
- H10D64/68
- CPC H01G4/10
- H01L23/52
- G11C13/00
- H01L23/528
- H10B41/27
- H10B41/35
- H10B43/27
- H10B43/35
- H10B63/00
- H10N70/00
- CPC H01L23/52
- H01L23/00
- H01L21/768
- H01L23/498
- H01L25/18
- H10B80/00
- CPC H01L24/08
- H01L23/48
- H01L23/522
- H01L25/00
- CPC H01L25/18
- H04K1/00
- CPC H04K1/00
- H10B41/10
- H10B43/10
- CPC H10B43/27
- H10N70/20
- CPC H10B63/845
- H01L33/62
- H01L33/00
- H01L33/06
- H01L33/20
- H01L33/32
- H01L33/40
- H01L33/42
- H01L33/44
- CPC H10H20/857
