Lam Research Corporation patent applications on February 13th, 2025
Patent Applications by Lam Research Corporation on February 13th, 2025
Lam Research Corporation: 19 patent applications
Lam Research Corporation has applied for patents in the areas of H01J37/32 (8), C23C16/455 (6), H01L21/67 (4), C23C16/04 (3), H01L21/02 (3) H01L21/0228 (2), H01J37/32183 (2), C23C16/045 (1), H01J37/32724 (1), H01L21/67017 (1)
With keywords such as: substrate, layer, plasma, signal, mask, methods, feature, circuit, process, and surface in patent application abstracts.
Patent Applications by Lam Research Corporation
20250051908. LARGE GRAIN TUNGSTEN GROWTH IN FEATURES_simplified_abstract_(lam research corporation)
Inventor(s): Kevin Qiwen CHEN of Fremont CA (US) for lam research corporation, Yu PAN of San Jose CA (US) for lam research corporation, Chan Myae Myae SOE of Santa Clara CA (US) for lam research corporation, Esther JENG of Los Altos CA (US) for lam research corporation, Juwen GAO of San Jose CA (US) for lam research corporation
IPC Code(s): C23C16/04, C23C16/02, C23C16/36, C23C16/455
CPC Code(s): C23C16/045
Abstract: methods of filling a feature with large grain tungsten include deposition of a tungsten carbon nitride (wcn) or tungsten nitride (wn) film that lines the feature. the wcn or wn film may be treated. it provides a template for subsequent growth of large grain tungsten. the top of the feature is treated with nitrogen to inhibit nucleation, facilitating bottom-up growth. in some embodiments, single grain tungsten is grown from the bottom up. methods of at least partially filling a feature with single grain tungsten include treatment of the feature. in some embodiments, single grain tungsten is grown without a liner layer in the feature.
Inventor(s): Alon Ganany of Portland OR (US) for lam research corporation, Pawan M. Patil of Mumbai (IN) for lam research corporation, John F. Stumpf of Wilsonville OR (US) for lam research corporation
IPC Code(s): C23C16/458, C23C16/46, C23C16/52, H05B3/78
CPC Code(s): C23C16/4586
Abstract: a gas conditioning apparatus comprising a substrate block comprising one or more fluid ports on an upper surface of the substrate block. the substrate block has a first length along a sidewall. the substrate block comprises an inlet port at a first end and an outlet port at a second end. a flow passage extends within the substrate block between the inlet port and the outlet port and is in fluidic communication with the one or more fluid ports. at least one heater strip is on the sidewall of the substrate block. the at least one heater strip extends between the first end and the second end and is to control an internal temperature within a zone of the substrate block. the zone has a second length that is less than or substantially equal to the first length.
Inventor(s): Stephen J. Banik, II of San Mateo CA (US) for lam research corporation, Aaron Berke of Portland OR (US) for lam research corporation, Gabriel Hay Graham of Portland OR (US) for lam research corporation, Gregory J. Kearns of West Linn OR (US) for lam research corporation, Lee Peng Chua of Beaverton OR (US) for lam research corporation, Bryan L. Buckalew of Tualatin OR (US) for lam research corporation
IPC Code(s): C25D17/00, C25D5/08, C25D7/12, C25D21/12
CPC Code(s): C25D17/001
Abstract: the embodiments herein relate to apparatuses and methods for electroplating one or more materials onto a substrate. embodiments herein utilize a cross flow conduit in the electroplating cell to divert flow of fluid from a region between a substrate and a channeled ionically resistive plate positioned near the substrate down to a level lower than level of fluid in a fluid containment unit for collecting overflow fluid from the plating system for recirculation. the cross flow conduit can include channels cut into components of the plating cell to allow diverted flow, or can include an attachable diversion device mountable to an existing plating cell to divert flow downwards to the fluid containment unit. embodiments also include a flow restrictor which may be a plate or a pressure relief valve for modulating flow of fluid in the cross flow conduit during plating.
Inventor(s): Rohit Ode of Portland OR (US) for lam research corporation, Troy Alan Gomm of Tigard OR (US) for lam research corporation
IPC Code(s): F16B33/06, F16B33/00, H01J37/32
CPC Code(s): F16B33/06
Abstract: disclosed herein are fasteners for use in a semiconductor wafer process chamber. the fasteners may be used to secure hardware. the fasteners may include outermost surfaces that are provided by multiple different coatings, e.g., a hard coating and a dry lubricant coating. the hard coating may provide outermost surfaces of the fastener that are exposed to a plasma when a remote plasma clean is performed and may be used to prevent particle generation when the fastener is subjected to the remote plasma clean. the dry lubricant coating may provide outermost surfaces of a threaded portion of the fastener and may be used to prevent galling.
Inventor(s): Jeffrey Marks of Saratoga CA (US) for lam research corporation, George Andrew Antonelli of Portland OR (US) for lam research corporation, Richard A. Gottscho of Menlo Park CA (US) for lam research corporation, Dennis M. Hausmann of Lake Oswego OR (US) for lam research corporation, Adrien LaVoie of Newberg OR (US) for lam research corporation, Thomas Joseph Knisley of Beaverton OR (US) for lam research corporation, Sirish K. Reddy of Portland OR (US) for lam research corporation, Bhadri N. Varadarajan of Beaverton OR (US) for lam research corporation, Artur Kolics of Lake Oswego OR (US) for lam research corporation
IPC Code(s): G03F1/76, C23C14/56, C23C16/44, C23C18/14, C23C18/16, C23C18/18, G03F7/00, G03F7/004, G03F7/16, G03F7/26, G03F7/36, H01L21/033, H01L21/3213, H01L21/67
CPC Code(s): G03F1/76
Abstract: vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. a metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. the metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. for example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as euv lithography.
Inventor(s): Eric Calvin Hansen of San Jose CA (US) for lam research corporation, Chenghao Wu of San Jose CA (US) for lam research corporation, Timothy William Weidman of Sunnyvale CA (US) for lam research corporation
IPC Code(s): G03F7/004, G03F7/16, G03F7/20, G03F7/36
CPC Code(s): G03F7/0042
Abstract: the present disclosure relates to a film formed with an organometallic precursor and an organic co-reactant, as well as methods for forming and employing such films. in particular embodiments, the films can be incubated after exposure to radiation, which can provide enhanced material differences between the exposed and unexposed regions. in non-limiting embodiments, the radiation can include extreme ultraviolet (euv) or deep ultraviolet (duv) radiation.
Inventor(s): Nizan Kenane of San Francisco CA (US) for lam research corporation, Timothy William Weidman of Sunnyvale CA (US) for lam research corporation, Eric Calvin Hansen of San Jose CA (US) for lam research corporation, Chenghao Wu of San Jose CA (US) for lam research corporation, Kevin Li Gu of Mountain View CA (US) for lam research corporation, Benjamin Kam of Heverlee (BE) for lam research corporation
IPC Code(s): G03F7/36, G03F7/004, G03F7/38, G03F7/40
CPC Code(s): G03F7/36
Abstract: the present disclosure relates to use of aqueous acid for developing or treating a radiation-sensitive film. the aqueous acid can be employed to form a pattern by a positive tone wet development process or to treat a developed pattern by further removing residual resist components.
Inventor(s): Shen PENG of Dublin CA (US) for lam research corporation
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32183
Abstract: a transformer coupled capacitive tuning (tcct) match network includes coarse and fine adjustment circuits. the coarse adjustment circuit receives a first rf signal and includes a first tune variable capacitance circuit and a first load variable capacitance circuit. the first tune variable capacitance circuit adjusts a frequency of the first rf signal to generate a second rf signal. the first load variable capacitance circuit is connected to a ground reference terminal and configured to adjust an impedance of the tcct match network. the fine adjustment circuit includes a second tune variable capacitance circuit and a second load variable capacitance circuit. the second tune variable capacitance circuit fine tunes a frequency of the second rf signal. the second load variable capacitance circuit is connected to the ground reference terminal and fine tunes the impedance of the transformer coupled capacitive tuning match network.
Inventor(s): Ranadeep Bhowmick of San Jose CA (US) for lam research corporation, Alexei Marakhtanov of Albany CA (US) for lam research corporation, Felix Leib Kozakevich of Sunnyvale CA (US) for lam research corporation, John Holland of San Jose CA (US) for lam research corporation
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32183
Abstract: a first radiofrequency signal generator is set to generate a low frequency signal. a second radiofrequency signal generator is set to generate a high frequency signal. an impedance matching system has a first input connected to an output of the first radiofrequency signal generator and a second input connected to an output of the second radiofrequency signal generator. the impedance matching system controls impedances at the outputs of the first and second radiofrequency signal generators. an output of the impedance matching system is connected to a radiofrequency supply input of a plasma processing system. a control module monitors reflected voltage at the output of the second radiofrequency signal generator. the control module determines when the reflected voltage indicates a change in impedance along a transmission path of the high frequency signal that is indicative of a particular process condition and/or event within the plasma processing system.
20250054734. SHOWERHEAD FACEPLATE CONFIGURATIONS_simplified_abstract_(lam research corporation)
Inventor(s): Bin LUO of Beaverton OR (US) for lam research corporation, Stephen TOPPING of Portland OR (US) for lam research corporation, Keith Joseph MARTIN of Tualatin OR (US) for lam research corporation, Weifeng CHENG of Portland OR (US) for lam research corporation, Yogesh BABBAR of Hillsboro OR (US) for lam research corporation, Pramod SUBRAMONIUM of Portland OR (US) for lam research corporation
IPC Code(s): H01J37/32, C23C16/455
CPC Code(s): H01J37/32449
Abstract: a showerhead for processing a substrate comprises a backplate and a faceplate attached to the backplate. the faceplate comprises a first surface facing the backplate, a second surface opposite to the first surface, and a plurality of through holes extending between the first and second surfaces. at least one of the first and second surfaces is at least partially contoured.
Inventor(s): Patrick G. BREILING of Tigard OR (US) for lam research corporation, Sergey G. BELOSTOTSKIY of Sherwood OR (US) for lam research corporation, Timothy S. THOMAS of Wilsonville OR (US) for lam research corporation, Joel HOLLINGSWORTH of Portland OR (US) for lam research corporation, Ramesh CHANDRASEKHARAN of Lake Oswego OR (US) for lam research corporation, Mahmoud VAHIDI of Beaverton OR (US) for lam research corporation
IPC Code(s): H01J37/32, H01L21/683
CPC Code(s): H01J37/32715
Abstract: described is a wafer chuck assembly comprising a platen with one or more plasma electrodes, and a radio frequency (rf) assembly comprising at least one rf conductor electrically coupled to the one or more plasma electrodes. the at least one rf conductor comprises a rod with a rod tip coupled to the one or more plasma electrodes, and a rod stem mechanically coupled to a thermal choke with a hollow interior. the rod comprises a first electrically conductive material and has a first width and a first length. the thermal choke comprises a second electrically conductive material, and has a second width and a second length; and the second width is equal or greater than the first width.
Inventor(s): Dan Marohl of San Jose CA (US) for lam research corporation, David Setton of Danville CA (US) for lam research corporation, Craig Rosslee of San Jose CA (US) for lam research corporation, Gautam Bhattacharyya of San Ramon CA (US) for lam research corporation
IPC Code(s): H01J37/32, H01L21/67, H01L21/683, H01L21/687
CPC Code(s): H01J37/32724
Abstract: a substrate support for a substrate processing chamber configured to implement a rapid alternating process includes a baseplate and a heating plate arranged on the baseplate. the heating plate includes a first zone including a first heating element configured to adjust a first temperature of the first zone of the heating plate and a second zone including a second heating element configured to adjust a second temperature of the second zone of the heating plate. a first thermally conductive bond layer is arranged between the heating plate and the baseplate. the first thermally conductive bond layer is configured to transfer heat from the heating plate to the baseplate during the rapid alternating process. the rapid alternating process includes a plurality of alternating deposition steps and etching steps.
20250054747. CONFORMAL DEPOSITION OF SILICON NITRIDE_simplified_abstract_(lam research corporation)
Inventor(s): Awnish Gupta of Hillsboro OR (US) for lam research corporation, Bart J. Van Schravendijk of Palo Alto CA (US) for lam research corporation, Dustin Zachary Austin of Tigard OR (US) for lam research corporation, Frank Loren Pasquale of Tigard OR (US) for lam research corporation
IPC Code(s): H01L21/02, C23C16/455, H01L21/027, H01L21/768
CPC Code(s): H01L21/0217
Abstract: high quality silicon nitride (silicon nitride characterized by low wet etch rate in dilute hydrofluoric acid) is deposited on a semiconductor substrate having one or more recessed features in a highly conformal manner. the deposition involves exposing the semiconductor substrate to a silicon-containing precursor (e.g., an aminosilane) to form an adsorbed layer of the silicon-containing precursor on the substrate. the adsorbed layer is then treated with a plasma formed in a process gas that includes n, at a temperature of 300-750� c. and a pressure of at least about 15 torr (e.g., 15-30 torr) to convert the precursor to silicon nitride. the exposure to precursor and conversion to silicon nitride are repeated in the same process chamber over many deposition cycles until a conformal silicon nitride of desired thickness is formed. in some embodiments the deposited films are hydrogen-free as evidenced by ir spectra.
Inventor(s): Awnish Gupta of Hillsboro OR (US) for lam research corporation, Bart J. Van Schravendijk of Palo Alto CA (US) for lam research corporation, Aaron Blake Miller of West Linn OR (US) for lam research corporation, Jon Henri of West Linn OR (US) for lam research corporation
IPC Code(s): H01L21/02, C23C16/34, C23C16/44, C23C16/455
CPC Code(s): H01L21/0228
Abstract: the present disclosure relates to methods, systems, and apparatuses for depositing films. in particular, a film is deposited using an atomic layer deposition process where some steps of the ald process are performed at a temperature above a pyrolysis temperature of a film precursor.
Inventor(s): Dustin Zachary Austin of Tigard OR (US) for lam research corporation, Joseph R. Abel of West Linn OR (US) for lam research corporation
IPC Code(s): H01L21/02, C23C16/02, C23C16/04, C23C16/40, C23C16/455, C23C16/56
CPC Code(s): H01L21/0228
Abstract: methods of filling a gap with a dielectric material including using an inhibition plasma during deposition. the inhibition plasma increases a nucleation barrier of the deposited film. the inhibition plasma selectively interacts near the top of the feature, inhibiting deposition at the top of the feature compared to the bottom of the feature, enhancing bottom-up fill. the inhibition plasma may also be used to etch portions of the feature to reduce void formation.
20250054760. CARBON MASK DEPOSITION_simplified_abstract_(lam research corporation)
Inventor(s): Daniela ANJOS RIGSBY of Tualatin OR (US) for lam research corporation, Kapu Sirish REDDY of Portland OR (US) for lam research corporation, Todd SCHROEDER of Sherwood OR (US) for lam research corporation
IPC Code(s): H01L21/033, C23C16/02, C23C16/04, C23C16/26, C23C16/455, C23C16/505, H01J37/32, H10B12/00, H10B41/20, H10B43/20
CPC Code(s): H01L21/0337
Abstract: examples are disclosed that relate to depositing a carbon mask to thicken a partially etched mask. one example provides a method comprising forming a mask layer on a substrate, and etching the substrate to partially form one or more etched features, the etching of the substrate also causing etching of the mask layer. the method further comprises, after etching a portion of the one or more etched features but before completing etching of the one or more etched features, depositing, by plasma-enhanced chemical vapor deposition (pecvd), a carbon mask over the mask layer.
Inventor(s): Hsu-Cheng HUANG of Newark CA (US) for lam research corporation, Sang Jun CHO of San Ramon CA (US) for lam research corporation, Sriharsha JAYANTI of Fremont CA (US) for lam research corporation, Gerardo DELGADINO of Milpitas CA (US) for lam research corporation, Steven CHUANG of Fremont CA (US) for lam research corporation
IPC Code(s): H01L21/3105, H01L21/311
CPC Code(s): H01L21/31055
Abstract: a patterning method includes etching a mask formed above a stack of two or more layers where the mask comprises a first patterned structure, a second patterned structure above the first patterned structure, where portions of the second patterned structure intersect the first patterned structure to form intersections and at least an opening. the mask includes a structure vertically between portions of the second patterned structure and the stack. the method includes etching a first layer of the stack through the opening and exposing a top surface of a second layer below the first layer, etching and removing the first patterned structure and the second patterned structure selectively to the first layer and the top surface of the second layer to form a planar mask comprising the first layer. the method further includes etching the second layer of the stack using the planar mask.
Inventor(s): Anthony DE LA LLERA of Fremont CA (US) for lam research corporation, Pratik MANKIDY of Fremont CA (US) for lam research corporation, John HOLLAND of San Jose CA (US) for lam research corporation
IPC Code(s): H01L21/67, H01J37/32, H01L21/687
CPC Code(s): H01L21/67017
Abstract: an assembly for a processing chamber of a substrate processing system includes a first component, a second component, and a thermal interface material arranged between the first component and the second component. at least one of the first component and the second component is configured to be exposed to plasma within the processing chamber, the thermal interface material has a first surface that faces and is in direct contact with the first component and a second surface that faces and is in direct contact with the second component the thermal interface material is comprised of a silicon polymer with at least one of aligned carbon fibers and carbon nanotubes (cnts), wherein the at least one of the carbon fibers and the cnts are aligned in a direction perpendicular to the first surface and the second surface.
Inventor(s): Changyou Jing of Livermore CA (US) for lam research corporation
IPC Code(s): H01L21/67, H03K3/017, H03K5/156, H05B1/02
CPC Code(s): H01L21/67248
Abstract: systems and methods for identifying a single failure in a heater array and compensating for the failure are described. the methods include identifying two x buses and two y buses of the heater array having a location of the failure. a confirmation of the single failure within the heater array is performed after identifying the two x and two y buses. once the single failure is confirmed, the location of the failure is identified. the methods include compensating for the single failure by adjusting a duty cycle of a heater at the location of the failure, adjusting additional duty cycles of heaters along the same x bus as the failed heater and the same y bus as the failed heater, and maintaining remaining duty cycles of power provided to remaining heaters of the heater array.
Lam Research Corporation patent applications on February 13th, 2025
- Lam Research Corporation
- C23C16/04
- C23C16/02
- C23C16/36
- C23C16/455
- CPC C23C16/045
- Lam research corporation
- C23C16/458
- C23C16/46
- C23C16/52
- H05B3/78
- CPC C23C16/4586
- C25D17/00
- C25D5/08
- C25D7/12
- C25D21/12
- CPC C25D17/001
- F16B33/06
- F16B33/00
- H01J37/32
- CPC F16B33/06
- G03F1/76
- C23C14/56
- C23C16/44
- C23C18/14
- C23C18/16
- C23C18/18
- G03F7/00
- G03F7/004
- G03F7/16
- G03F7/26
- G03F7/36
- H01L21/033
- H01L21/3213
- H01L21/67
- CPC G03F1/76
- G03F7/20
- CPC G03F7/0042
- G03F7/38
- G03F7/40
- CPC G03F7/36
- CPC H01J37/32183
- CPC H01J37/32449
- H01L21/683
- CPC H01J37/32715
- H01L21/687
- CPC H01J37/32724
- H01L21/02
- H01L21/027
- H01L21/768
- CPC H01L21/0217
- C23C16/34
- CPC H01L21/0228
- C23C16/40
- C23C16/56
- C23C16/26
- C23C16/505
- H10B12/00
- H10B41/20
- H10B43/20
- CPC H01L21/0337
- H01L21/3105
- H01L21/311
- CPC H01L21/31055
- CPC H01L21/67017
- H03K3/017
- H03K5/156
- H05B1/02
- CPC H01L21/67248
