Kioxia Corporation patent applications on March 20th, 2025
Patent Applications by Kioxia Corporation on March 20th, 2025
Kioxia Corporation: 54 patent applications
Kioxia Corporation has applied for patents in the areas of G11C16/04 (8), G11C16/34 (6), H10B43/27 (6), G11C16/10 (5), H01L23/00 (4) G06F12/0246 (3), H10B43/27 (3), H10B12/30 (2), G01R1/07314 (1), H03M13/1108 (1)
With keywords such as: memory, data, layer, semiconductor, voltage, circuit, third, device, direction, and cell in patent application abstracts.
Patent Applications by Kioxia Corporation
Inventor(s): Hiroki KAMATA of Yokohama JP for kioxia corporation
IPC Code(s): G01R1/073, G01R31/28
CPC Code(s): G01R1/07314
Abstract: in one embodiment, a prober includes a stage configured to hold a substrate as an inspection object. the prober further includes a housing configured to hold a probe card that can be electrically connected to the substrate, and hold a performance board that can be electrically connected to the probe card. moreover, the housing is configured to function as a ground line, and includes a connection path configured to electrically connect the probe card and the performance board.
20250093919. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Teruyuki NARITA of Machida Tokyo JP for kioxia corporation
IPC Code(s): G06F1/18
CPC Code(s): G06F1/183
Abstract: a semiconductor storage device includes a substrate, a semiconductor memory, a controller, and an electronic part. the substrate has opposing first and second faces extending in a first direction, a third face extending in a thickness direction of the substrate, a recess provided in the third face and extending in the thickness direction, and a conductive portion provided on an inner face of the recess. the electronic part has a main body and a lead protruding from the main body. the lead has a first portion, which protrudes linearly from the main body toward the recess in the first direction, and a second portion bent from the first portion and extending linearly along the inner face of the recess in the thickness direction, and the second portion is fixed to the conductive portion such that one portion of the first portion overlaps the recess when viewed in the first direction.
20250093927. INFORMATION PROCESSING APPARATUS_simplified_abstract_(kioxia corporation)
Inventor(s): Akihisa FUJIMOTO of Sagamihara JP for kioxia corporation, Atsushi KONDO of Yokohama JP for kioxia corporation
IPC Code(s): G06F1/26, G11C5/14, G11C16/04, G11C16/30, H02M3/04
CPC Code(s): G06F1/26
Abstract: according to one embodiment, an information processing apparatus includes a connecting portion connectable to a removable memory device and a power supply circuit configured to apply a first voltage and a second voltage to the removable memory device. when the removable memory device is connected to the connecting portion, one of a pair of first feedback wires is electrically connected to one of the first power supply terminals to which the first voltage is applicable, and the other of the pair of first feedback wires is electrically connected to one of the power supply ground terminals connectable to a ground level, the power supply circuit is configured to control the first voltage, based on a voltage between the pair of first feedback wires.
20250094055. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Kenta INAKAGATA of Ota Tokyo JP for kioxia corporation, Mitsunori TADOKORO of Fujisawa Kanagawa JP for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: a controller of a memory system issues a first memory read request for reading first data at a head of data to be read from a first memory die to the first memory die. when remaining data following the first data is included in the data to be read, the controller transfers a first identifier from a first command queue to a second command queue corresponding to a second memory die in which second data at a head of the remaining data is stored. the controller issues a second memory read request for reading the second data from the second memory die to the second memory die in response to transferring the first identifier to the second command queue.
Inventor(s): Sie Pook LAW of San Jose CA US for kioxia corporation
IPC Code(s): G06F3/06, G06F11/20, G06F12/0802
CPC Code(s): G06F3/0688
Abstract: an array controller for connection between a solid state drive controller and multiple non-volatile storage units is provided. the array controller comprises a plurality of enable outputs, each of which is connected to an enable input of one of the non-volatile storage units, and a buffer in which data to be written into or read from the non-volatile storage units is stored. the array controller further comprises a control unit configured to enable a communication path between the solid state drive controller and one of the non-volatile storage units according to an address received from the solid state drive controller.
20250094279. MEMORY SYSTEM AND DATA REARRANGEMENT METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Masato INOUE of Yokohama JP for kioxia corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1068
Abstract: according to one embodiment, a controller includes a counter counting a number of accesses of data in a nonvolatile memory, in a first unit which is a unit of access to data from the host. the controller determines whether a received read command is a sequential read command or a random read command, increments a value of the counter, which corresponds to data specified by the received read command, when the received read command is the random read command, and in a process of moving first data of a first block to a second block, controls rearrangement of the first data of the first block to the second block based on the value of the counter when the first data has a size of the first unit and needs to be arranged across two pages in the second block.
Inventor(s): Suguru NISHIKAWA of Tokyo JP for kioxia corporation, Takehiko AMAKI of Yokohama Kanagawa JP for kioxia corporation, Shunichi IGAHARA of Fujisawa Kanagawa JP for kioxia corporation, Toshikatsu HIDA of Yokohama Kanagawa JP for kioxia corporation, Yoshihisa KOJIMA of Kawasaki Kanagawa JP for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: according to an embodiment, a memory system includes a nonvolatile memory including memory cells and a memory controller coupled to the nonvolatile memory. each of the plurality of memory cells is configured to store, in a nonvolatile manner, a plurality of bits of data. the memory controller is configured to, in a case where a first memory cell stores valid first bit data as a first bit and does not store data as a second bit, and a second memory cell stores valid second bit data as the first bit and does not store data as the second bit, and upon reception of a flush command from a host, read the second bit data from the second memory cell and write the second bit data read from the second memory cell to the first memory cell as the second bit.
Inventor(s): Yuki SASAKI of Kamakura JP for kioxia corporation, Aurelien Nam Phong TRAN of Yokohama JP for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: according to one embodiment, a controller of a memory system provides a host with logical address spaces. a plurality of queues of the host include one or more queues allocated to each of the logical address spaces. the controller calculates first use amounts of a nonvolatile memory corresponding to the logical address spaces, respectively, selects a queue from which a command is to be fetched among the plurality of queues, based on the first use amounts, fetches a command from the queue, calculates a predicted use amount of the nonvolatile memory in accordance with the command, and updates a second use amount corresponding to a first logical address space to which the first queue is allocated among the first use amounts by using the predicted use amount.
Inventor(s): Yuki SASAKI of Kamakura JP for kioxia corporation, Shinichi KANNO of Ota JP for kioxia corporation, Takahiro KURITA of Sagamihara JP for kioxia corporation
IPC Code(s): G06F12/02, G06F12/1009
CPC Code(s): G06F12/0246
Abstract: according to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. the data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. the second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.
20250094345. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Shinichi KANNO of Ota Tokyo JP for kioxia corporation, Yuki SASAKI of Kamakura Kanagawa JP for kioxia corporation, Kensaku YAMAGUCHI of Kawasaki Kanagawa JP for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0292
Abstract: a memory system includes a non-volatile memory and a controller that is configured to: write n pieces of address translation information repeatedly in a first block according to a first order; write the n pieces of address translation information repeatedly in a second block of the non-volatile memory according to a second order that is offset from the first order by n/2; write an update log in the first and second blocks each time one of the n pieces is written; and in response to power to the memory system being restored after shutdown, read from the first block, n/2 pieces of address translation information and n/2 update logs last written thereinto, read from the second block, n/2 pieces of address translation information and n/2 update logs last written thereinto, and reconstruct a logical-to-physical address translation table from the information read from the non-volatile memory.
20250094374. NAND SWITCH_simplified_abstract_(kioxia corporation)
Inventor(s): Sie Pook LAW of San Jose CA US for kioxia corporation
IPC Code(s): G06F13/40, G06F13/16
CPC Code(s): G06F13/40
Abstract: in a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. the switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. in addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. the switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.
Inventor(s): Gaku UCHIDA of Yokohama Kanagawa JP for kioxia corporation
IPC Code(s): G06F16/2455, G06F16/22
CPC Code(s): G06F16/24561
Abstract: a method for searching data from a storage is provided. the method includes, in response to a query, selecting one or more candidate posting lists among a plurality of posting lists, based on a distance between a query vector corresponding to the query and a representative vector of each of the plurality of posting lists, acquiring the one or more candidate posting lists from the storage, decompressing one or more compressed posting lists included in the one or more candidate posting lists, after the decompressing, selecting one or more vectors included in the one or more candidate posting lists based on a distance between the query vector and each of vectors included in the one or more candidate posting lists, and outputting one or more searchable data pieces corresponding to the selected one or more vectors as an answer to the query.
20250094648. MEMORY SYSTEM AND METHOD FOR VERIFYING SAFETY_simplified_abstract_(kioxia corporation)
Inventor(s): Narufumi KOYA of Kawasaki Kanagawa JP for kioxia corporation
IPC Code(s): G06F21/79, G06F21/64
CPC Code(s): G06F21/79
Abstract: according to one embodiment, a memory system includes a nonvolatile memory and a controller. the controller verifies safety of a request source requesting to write data to or read data from the nonvolatile memory using a challenge-response type attestation.
20250094874. INFORMATION PROCESSING DEVICE AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Daiki KOYAMA of Yokohama Kanagawa JP for kioxia corporation, Yusuke UMEZAWA of Yokohama Kanagawa JP for kioxia corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: according to an embodiment, a first data set is a set of inspection results for chips formed on a wafer or cut out from the wafer. the inspection results are obtained by executing a first inspection on the chips. a second data set indicates, for each chip, presence or absence of early failure obtained by executing a second inspection on the chips. a processor determines, based on the first data set, a cluster of chips not satisfying a first criterion. the processor calculates a third data set being a set of feature amounts of chips related to a distance to the cluster. the processor executes training of a machine learning model by using, as input data, the first data set and the third data set and using the second data set as correct answer data. the processor outputs the machine learning model of which the training has been executed.
20250095692. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takafumi MASUDA of Kawasaki Kanagawa JP for kioxia corporation, Mutsumi OKAJIMA of Yokkaichi Mie JP for kioxia corporation, Nobuyoshi SAITO of Ota Tokyo JP for kioxia corporation, Keiji IKEDA of Kawasaki Kanagawa JP for kioxia corporation
IPC Code(s): G11C5/06, G11C11/22, H10B51/10, H10B51/20
CPC Code(s): G11C5/06
Abstract: a semiconductor memory device includes: a first via-wiring extending in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring; memory portions arranged in the first direction and electrically connected to the first semiconductor layers; first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers; first wirings arranged in the first direction and electrically connected to the plurality of first gate electrodes; second semiconductor layers arranged in the first direction and electrically connected to the first wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and second wirings arranged in the first direction and electrically connected to the second semiconductor layers.
20250095695. MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yuichi ITO of Seoul KR for kioxia corporation
IPC Code(s): G11C5/08, H10B61/00, H10N50/10
CPC Code(s): G11C5/08
Abstract: according to one embodiment, a magnetic memory device includes a first wiring line extending along a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending along a second direction, a memory cell provided between the first wiring line and the second wiring line, including a bottom surface connected to the first wiring line and a top surface connected to the second wiring line, and including a magnetoresistance effect element and a switching element stacked in a third direction, and a contact including a top surface connected to the second wiring line, the top surface of the contact being located higher than the top surface of the memory cell.
Inventor(s): Shinya KOIZUMI of Kamakura JP for kioxia corporation
IPC Code(s): G11C7/22, G06F1/08, G06F13/16, G06F13/18, G06F13/42, G11C7/10
CPC Code(s): G11C7/222
Abstract: a memory system includes a memory chip and a memory controller that controls the memory chip. in a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. in a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. the second clock has a frequency different from a frequency of the first clock. in the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.
20250095705. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Naoki MATSUSHITA of Seoul KR for kioxia corporation
IPC Code(s): G11C11/16, G11C5/06
CPC Code(s): G11C11/1655
Abstract: according to one embodiment, a memory device includes: a memory cell array including first to ninth areas; first and second column switch circuits; first and second row switch circuits. in a case where a cell in the sixth area is selected, the first and second column switch circuits and the first row switch circuit are activated, and in a case where a cell in the seventh area is selected, the second column switch circuit and the first and second row switch circuits are activated, and in a case where a cell in the eighth area is selected, the first and second column switch circuits and the second row switch circuit are activated, and in a case where a cell in the ninth area is selected, the first column switch circuit and the first and second row switch circuits are activated.
20250095706. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroaki MAEKAWA of Yokohama Kanagawa JP for kioxia corporation
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1673
Abstract: a semiconductor storage device includes a memory cell and a control circuit. in an overall read operation, the control circuit performs a first read operation to detect a first voltage and determine first data from the detected first voltage, writes second data to the memory cell, performs a second read operation to detect a second voltage and determine the second data from the detected second voltage, and compares the first data and the second data based on the first voltage and the second voltage to determine a value of the first data. when the first data and the second data are different, the control circuit performs a sequence of operations that includes a second write operation to write the first data and a verify read operation. based on third data detected by the verify read operation, the control circuit ends the overall read operation or repeats the sequence of operations.
Inventor(s): Masanobu SHIRAKAWA of Chigasaki JP for kioxia corporation, Takayuki AKAMINE of Yokohama JP for kioxia corporation
IPC Code(s): G11C11/56, G06F11/10, G11C16/04, G11C16/34, G11C29/04, G11C29/52, H03M13/29
CPC Code(s): G11C11/5642
Abstract: according to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). when receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. after receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
20250095729. STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kazuya MATSUZAWA of Kamakura Kanagawa JP for kioxia corporation
IPC Code(s): G11C13/00
CPC Code(s): G11C13/004
Abstract: a storage device includes: a first wiring; a second wiring; a memory cell provided between the first wiring and the second wiring, the memory cell including a resistance change storage element configured in a first resistance state or a second resistance state, and a selector connected to the resistance change storage element and configured to shift from off-state to on-state when voltage higher than a first threshold voltage is applied; a switching element configured to input a first signal from the second wiring and output a second signal to a third wiring; a voltage application circuit configured to apply a first voltage to the first wiring at a first time point; and a determination circuit configured to determine the resistance state of the resistance change storage element based on the second signal output to the third wiring at a second time point after the first time point.
Inventor(s): Dandan ZHAO of Yokohama Kanagawa JP for kioxia corporation, Hidenori MIYAGAWA of Yokohama Kanagawa JP for kioxia corporation, Masakazu GOTO of Moriya Ibaraki JP for kioxia corporation
IPC Code(s): G11C13/00, G11C5/06
CPC Code(s): G11C13/0069
Abstract: a storage device includes a memory cell including a first layer, a second layer, and a memory layer between the first and second layers and can switch between states including a first state and a second state in which electrical resistance is higher, and a circuit executing a write process. the control circuit is configured to, in the process to switch the memory layer from the second to first state, alternately apply to the second layer a first voltage having positive polarity and a second voltage having negative polarity, an absolute value of the second voltage being larger than the first voltage, and in the process to switch the memory layer from the first to second state, alternately apply to the second layer a third voltage having negative polarity and a fourth voltage having positive polarity, an absolute value of the fourth voltage being larger than the third voltage.
20250095737. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kouji Matsuo of Ama Aichi JP for kioxia corporation, Hiroshi Nakamura of Fujisawa Kanagawa JP for kioxia corporation
IPC Code(s): G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): G11C16/0483
Abstract: according to one embodiment, a memory device includes: a first semiconductor and a first insulator provided at a first position in a first direction intersecting a substrate; a first conductor extending in the first direction and having a first portion facing the first semiconductor without interposing the first insulator and a second portion facing the first insulator without interposing the first semiconductor; and a first charge storage film provided between the first portion and the first semiconductor and not provided between the second portion and the first insulator.
20250095741. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Xu LI of Yokohama Kanagawa JP for kioxia corporation
IPC Code(s): G11C16/08, G11C16/04, G11C16/10, G11C16/16, G11C16/24, G11C16/30, G11C16/32, G11C16/34, H10B69/00
CPC Code(s): G11C16/08
Abstract: a semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. the source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.
20250095743. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Tatsuo OGURA of Yokkaichi Mie JP for kioxia corporation, Masaki KONDO of Yokkaichi Mie JP for kioxia corporation, Takashi MAEDA of Kamakura Kanagawa JP for kioxia corporation
IPC Code(s): G11C16/10, G11C16/04, G11C16/24, G11C16/26, G11C16/34, H01L25/065, H10B43/30, H10B43/40
CPC Code(s): G11C16/10
Abstract: a semiconductor memory device includes: a first conductive layer; and a second conductive layer adjacent to the first conductive layer. write loops each include: a first program operation that applies the first conductive layer with a program voltage and applies a bit line with a first bit line voltage; and a second program operation that applies the first conductive layer with the program voltage and applies the bit line with a second bit line voltage larger than the first bit line voltage. the write operation includes a state judging operation that judges whether a memory cell corresponding to the semiconductor layer and the second conductive layer has been controlled to a low-state, or not. when the memory cell has been controlled to the low-state, the first program operation is executed, and when the memory cell has not been controlled to the low-state, the second program operation is executed.
20250095748. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Akio SUGAHARA of Yokohama Kanagawa JP for kioxia corporation, Akihiro IMAMOTO of Kawasaki Kanagawa JP for kioxia corporation, Toshifumi WATANABE of Yokohama Kanagawa JP for kioxia corporation, Mami KAKOI of Yokohama Kanagawa JP for kioxia corporation, Kohei MASUDA of Yokohama Kanagawa JP for kioxia corporation, Masahiro YOSHIHARA of Yokohama Kanagawa JP for kioxia corporation, Naofumi ABIKO of Kawasaki Kanagawa JP for kioxia corporation
IPC Code(s): G11C16/14, G11C16/26, G11C16/30, G11C16/34
CPC Code(s): G11C16/14
Abstract: a semiconductor memory device includes plural planes each including plural blocks each including a memory cell, a voltage generator which supplies power to the plural planes, an input/output circuit which receives a command set sent from a memory controller to the semiconductor memory device, and a sequencer which executes an operation in response to the command set. upon receiving a first command set instructing execution of a first operation, the sequencer executes the first operation. upon receiving a command set instructing operation of a second operation during execution of the first operation, the sequencer executes the first and second operations in parallel. upon receiving a third command set instructing execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
20250095752. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Yoshikazu TAKEYAMA of Fujisawa Kanagawa JP for kioxia corporation, Keisuke TAKAHASHI of Yokohama Kanagawa JP for kioxia corporation
IPC Code(s): G11C16/30, G06N3/0455, G11C16/04, G11C16/10, G11C16/14, G11C16/26
CPC Code(s): G11C16/30
Abstract: a semiconductor memory device includes a memory cell array, a control circuit, and a voltage generation circuit. the control circuit is configured to perform a first operation to access the memory cell array and then a second operation to access the memory cell array. the voltage generation circuit is configured to generate a first operation voltage, which is supplied from an output terminal of the voltage generation circuit to the memory cell array during the first operation, and a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation. the control circuit is configured to control the voltage generation circuit to maintain a voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation.
Inventor(s): Hajime SANO of Katsushika Tokyo JP for kioxia corporation
IPC Code(s): G11C16/34, G11C16/10, G11C16/12
CPC Code(s): G11C16/3404
Abstract: a semiconductor memory device includes memory cell transistors and a control circuit. the control circuit is configured to set a threshold voltage of each memory cell transistor to be in one of voltage ranges to store multi-bit data in each memory cell transistor. the voltage ranges include a first range corresponding to a first multi-bit value, a second range lower than the first range and corresponding to a second multi-bit value, and a third range that is the lowest. when a target memory cell transistor in which data of the second multi-bit value is to be written currently stores data of the first multi-bit value, the control circuit is configured to apply a first voltage to a gate of the target memory cell transistor, to shift the threshold voltage of the target memory cell transistor to be in the second range without dropping into the third range.
20250095760. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takatoshi MINAMOTO of Kamakura Kanagawa JP for kioxia corporation
IPC Code(s): G11C16/34, G11C16/04, G11C16/10
CPC Code(s): G11C16/3459
Abstract: according to embodiments, a semiconductor memory device includes a memory string including a first select transistor, a first memory cell, and a second memory cell, a bit line, a first word line, a second word line, and a control circuit configured to execute a write operation including a program operation and a program verify operation. the control circuit is configured to raise a voltage of the second word line to a first voltage based on a first condition, in a case of executing the program verify operation of the first memory cell, and to raise a voltage of the first word line to the first voltage based on a second condition different from the first condition, in a case of executing the program verify operation of the second memory cell.
20250095763. TEST APPARATUS AND TEST METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Michiru HOGYOKU of Yokohama JP for kioxia corporation
IPC Code(s): G11C29/50, G01R31/317
CPC Code(s): G11C29/50004
Abstract: according to one embodiment, in a test apparatus, a controller obtains a threshold voltage of a memory cell by performing first processing on a read characteristic. the first processing is processing of, when a subthreshold region in the read characteristic is defined as a first region, focusing on a second region being a region of a read voltage larger than a maximum read voltage of the first region. the controller calculates a first slope in a first threshold characteristic indicating a relationship between a write voltage and the threshold voltage in the write processing, based on the threshold voltage obtained in the first processing. the controller subtracts the first slope from a slope in a predetermined threshold characteristic to obtain a first slope degradation component.
20250095767. NON-VOLATILE MEMORY AND MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Mitsuaki HONMA of Fujisawa Kanagawa JP for kioxia corporation
IPC Code(s): G11C29/52, G11C7/10
CPC Code(s): G11C29/52
Abstract: a nonvolatile memory includes a memory cell transistor storing information of a plurality of bits including first through third bits, a word line, a sense amplifier unit, and a control circuit which controls the word line and the sense amplifier unit. the control circuit includes first through third latch circuits, and performs plural read operations including a first read operation to read out the first bit into the first latch circuit and generate data in the second and third latch circuits, a second read operation performed after the first read operation to read out the second bit into the first latch circuit and update the data in the second and third latch circuits, and a third read operation performed after the second read operation to read out the third bit into the first latch circuit and update the data in the second and third latch circuits.
Inventor(s): Takahiro KAWATA of Yokkaichi Mie JP for kioxia corporation, Shinsuke KIMURA of Yokkaichi Mie JP for kioxia corporation, Satoshi NAKAOKA of Yokkaichi Mie JP for kioxia corporation, Satoru OHGATA of Yokkaichi Mie JP for kioxia corporation
IPC Code(s): H01L21/67
CPC Code(s): H01L21/67034
Abstract: a semiconductor manufacturing apparatus includes a chamber, an opening/closing portion, and a pressure control circuit. the chamber includes first and second portions, both of which are capable of accommodating a wafer. the opening/closing portion is provided between the first portion and the second portion, and is movable to open and close a space between the first and second portions. the pressure control circuit is configured to control a pressure difference between the first portion and the second portion.
Inventor(s): Yoshio MIZUTA of Yokkaichi Mie JP for kioxia corporation
IPC Code(s): H01L21/683, H01L21/687
CPC Code(s): H01L21/6835
Abstract: according to one embodiment, a substrate peeling device including an adsorption stage and a light source is provided. a bonded body including multiple substrates is adsorbed to the adsorption stage. the adsorption stage includes a first region and a second region. the second region is inside the first region. the light source can sequentially apply a laser beam toward the first region and the second region. the adsorption stage has weaker power of adsorbing the bonded body in the second region than in the first region.
Inventor(s): Kazuma HASEGAWA of Fujisawa Kanagawa JP for kioxia corporation, Tomoya SANUKI of Yokkaichi Mie JP for kioxia corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/31, H01L23/34, H01L25/065, H01L25/10
CPC Code(s): H01L23/49838
Abstract: a semiconductor storage device of an embodiment includes a substrate, a seal member, a first memory chip, and a non-signal wiring. the non-signal wiring has a wiring main body. the wiring main body includes a first portion, a second portion, a third portion. the first portion extends in a second direction intersecting the first direction. the second portion is folded back from an end of the first portion to a first side in the second direction. the second portion extends parallel to the first portion. the third portion is folded back from an end of the second portion to a second side in the second direction. the second side is a side opposite to the first side in the second direction. the third portion extends parallel to the second portion.
20250096115. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hisashi KATO of Yokkaichi JP for kioxia corporation
IPC Code(s): H01L23/522, H01L23/528, H10B43/27, H10B43/35
CPC Code(s): H01L23/5226
Abstract: according to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. the first pillar is passing through the second conductor layers. the first pillar includes a first semiconductor layer and a second insulator layer. the first semiconductor layer includes a side surface partially in contact with the first conductor layer. the first contact is passing through the second conductor layers. the first contact includes a third conductor layer and a third insulator layer. the third conductor layer includes a side surface partially in contact with the first conductor layer. the source line drive circuit is electrically coupled to the first conductor layer via the first contact.
20250096118. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kunio OTA of Yokohama JP for kioxia corporation
IPC Code(s): H01L23/522, H01L23/00, H01L23/31, H01L23/498, H01L23/64, H01L25/065, H01L25/18
CPC Code(s): H01L23/5227
Abstract: a semiconductor device includes an interposer substrate including a plurality of wiring layers inside, a first semiconductor chip disposed on the interposer substrate, and a power circuit configured to transform externally supplied voltage and supply the transformed voltage to the first semiconductor chip. the power circuit includes an inductor and a capacitor, the inductor being constituted by a plurality of coil patterns respectively formed in at least two of the plurality of wiring layers.
Inventor(s): Mikio SHIRAISHI of Yokohama Kanagawa JP for kioxia corporation
IPC Code(s): H03K3/037, H03K19/21
CPC Code(s): H03K3/037
Abstract: according to an embodiment, a clock signal is input to clock terminals of first and second ffs. a first signal from a q terminal of the first ff is input to a d terminal of the second ff. a first inverter performs inversion calculation on a second signal from a q terminal of the second ff. a signal from the first inverter is input to a d terminal of the first ff. a second inverter performs inversion calculation on the first signal. (l−1) adders each calculate a different bit of a gray code by an addition operation based on a carry signal. a circuit block generates a carry signal for a first adder based on a logical product of the first/second signals. the circuit block generates carry signals of second to (l−1)th adders based on the second signal and a signal from the second inverter.
Inventor(s): Go URAKAWA of Yokohama Kanagawa JP for kioxia corporation
IPC Code(s): H03L7/089, H03L7/093, H03L7/099
CPC Code(s): H03L7/0895
Abstract: according to one embodiment, a charge pump circuit includes: a current source; a first current mirror including an input terminal connected to the current source; a second current mirror including an input terminal connected to an output terminal of the first current mirror; a third current mirror including an input terminal connected to a first output terminal of the second current mirror; a first switch including a first end connected to a second output terminal of the second current mirror via a first node, and including a second end; and an output terminal connected to an output terminal of the third current mirror and the second end of the first switch via a second node.
20250096816. MEMORY SYSTEM AND CONTROL METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Yuta KUMANO of Kawasaki Kanagawa JP for kioxia corporation, Hironori UCHIKAWA of Fujisawa Kanagawa JP for kioxia corporation
IPC Code(s): H03M13/11, H03M13/00
CPC Code(s): H03M13/1108
Abstract: a memory system includes a non-volatile memory and a memory controller. the memory controller is configured to read data from the non-volatile memory, obtain a plurality of decoded words based on a syndrome calculated from a soft decision input data based on the read data, calculate a plurality of metrics for the plurality of decoded words, generate a metric array using the calculated metrics. further, the memory controller is configured to, based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtain a soft decision output data corresponding to the soft decision input data.
Inventor(s): Hirotaka HIGASHI of Kawasaki JP for kioxia corporation, Manabu WATANABE of Kawasaki JP for kioxia corporation, Junji WADATSUMI of Tokyo JP for kioxia corporation
IPC Code(s): H04L1/00, H04L1/1607
CPC Code(s): H04L1/0072
Abstract: according to one embodiment, a communication system includes a host controller, a plurality of communication devices, and a communication path coupling the host controller and the communication devices in a ring shape and configured to transmit a communication frame for serial communications, wherein the host controller and the communication devices each includes an ecc circuit configured to detect and correct an error and having a variable error correction capability, and the host controller is configured to set an error correction capability of the ecc circuit in accordance with an error caused in the communication path.
20250097071. COMMUNICATION DEVICE AND COMMUNICATION SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Hirotaka HIGASHI of Kawasaki JP for kioxia corporation, Manabu WATANABE of Kawasaki JP for kioxia corporation, Junji WADATSUMI of Tokyo JP for kioxia corporation
IPC Code(s): H04L12/42, H04L12/40
CPC Code(s): H04L12/42
Abstract: according to one embodiment, a communication device connected in a ring shape, the communication device comprising: receiving circuitry; first circuitry configured to be capable of executing insertion and extraction of data; and transmitting circuitry configured to transmit a communication frame based on a result of the first circuitry, wherein after the receiving circuitry receives a first container including, as transmission destinations, the communication device and a first device, the transmitting circuitry is configured to transmit a second communication frame including the first container including the first device as a new transmission destination, with the communication device being excluded from the transmission destinations of the first container.
20250097082. ELECTRONIC DEVICE AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Akinori BITO of Yokohama Kanagawa JP for kioxia corporation
IPC Code(s): H04L25/03, H04L25/02
CPC Code(s): H04L25/03878
Abstract: an electronic device includes a first control circuit and a second control circuit. the first control circuit can acquire, when a first reception circuit and a first transmission circuit transition from a first state of communicating at a first communication speed conforming to a first specification to a second state of communicating at a second communication speed conforming to a second specification, a first adjustment value related to one setting value applied to a third transmission circuit, and transmit the first adjustment value to the second control circuit. the second control circuit can determine, when a second reception circuit and a second transmission circuit transition from the first state to the second state, a second adjustment value which is one setting value applied to a fourth transmission circuit, based on the first adjustment value transmitted from the first control circuit.
Inventor(s): Kiyohito NISHIHARA of Hiratsuka Kanagawa JP for kioxia corporation
IPC Code(s): H05K1/11, H01L23/00, H01L23/31, H01L23/367, H01L25/18, H05K1/18, H10B80/00
CPC Code(s): H05K1/117
Abstract: a semiconductor storage device includes a first substrate including a first layer and a second layer on the first layer, a memory chip on the first layer, a controller disposed on the first layer and configured to control the memory chip, and molding resin that covers the first layer, the memory chip, and the controller. the second layer of the first substrate includes a conductive pattern including a plurality of terminals, and an insulating layer partially covering the conductive pattern and the first layer, and at a part of the first layer not covered by the insulating layer, one or both of the conductive pattern and the insulating layer form first concaves at predetermined intervals.
20250098141. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Mutsumi OKAJIMA of Yokkaichi Mie JP for kioxia corporation
IPC Code(s): H10B12/00, H01L23/00, H01L25/065, H01L25/18, H10B80/00
CPC Code(s): H10B12/30
Abstract: a semiconductor memory device includes: a substrate; a first wiring; a first semiconductor layer disposed between the substrate and the first wiring; second semiconductor layers disposed between the first semiconductor layer and the first wiring; a first via-wiring connected to the first and the second semiconductor layers; a first memory portion connected to the first semiconductor layer; a first gate electrode opposed to the first semiconductor layer; a second wiring connected to the first gate electrode; connection electrodes connected to the second semiconductor layers; second gate electrodes opposed to the second semiconductor layers; third wirings disposed between the second and the first wiring and connected to the second gate electrodes; a fourth wiring connected to the first memory portion; a fifth wiring connected to the connection electrodes in common; and an insulating layer disposed between the fourth wiring and the fifth wiring.
20250098143. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Ryota NARASAKI of Yokkaichi Mie JP for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: according to an embodiment a semiconductor memory device includes a laminated structure with first layers and second layers alternately stacked in a first direction. a first and second bit line extends through the laminated structure. the second bit line is spaced from the first bit line in a second direction. each first layer has a word line that extends in the second direction, a first semiconductor layer that extends alongside word line and is connected to the first bit line, a second semiconductor layer that extends alongside the word line and is spaced from the first semiconductor layer in the second direction, a gate insulating layer between the word line and the first or second semiconductor layer, a part of a first capacitor connected to the first semiconductor layer, and a part of a second capacitor connected to the second semiconductor layer.
Inventor(s): Keiichi Sawa of Yokkaichi JP for kioxia corporation
IPC Code(s): H10B41/27, H01L29/66, H01L29/788, H10B41/10, H10B41/35
CPC Code(s): H10B41/27
Abstract: according to one embodiment, a nonvolatile semiconductor memory device includes a plurality of u-shaped memory strings, each of the plurality of u-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. the conductive connection body connects the first columnar body and the second columnar body. a plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. the plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. a plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
Inventor(s): Toshimichi NISHIMURA of Yokkaichi JP for kioxia corporation, Yosuke TAKEUCHI of Yokkaichi JP for kioxia corporation
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: according to one embodiment, a semiconductor memory device includes first and second stacked bodies. in each of the first and second stacked bodies, conductive layers and insulating layers are alternately stacked one by one. the semiconductor memory device includes first and second bridging members. the first bridging member penetrates the first stacked body and connects first interlayer insulating films covering a first staircase part on both sides. the first bridging member is provided on an upper end of a first platy member. the second bridging member penetrates the second stacked body and connects second interlayer insulating films covering a second staircase part on both sides. the second bridging member is provided on an upper end of a second platy member. lower ends of the first and second bridging members are positioned above uppermost conductive layers of the first and second stacked bodies, respectively.
20250098165. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Fumie KIKUSHIMA of Yokkaichi Mie JP for kioxia corporation, Michiko ISHIDA of Yokkaichi Mie JP for kioxia corporation, Yosuke MURAKAMI of Mie Mie JP for kioxia corporation, Hideomi AOIKE of Tsu Mie JP for kioxia corporation, Tatsuya ISHIKAWA of Yokkaichi Mie JP for kioxia corporation, Ryo YOUGAUCHI of Yokkaichi Mie JP for kioxia corporation, Tatsuo OGURA of Yokkaichi Mie JP for kioxia corporation
IPC Code(s): H10B43/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: in one embodiment, a semiconductor memory device includes a stacked body of a first conductive films and first insulation films alternately stacked with each other in a first direction. a plurality of columnar bodies is in the stacked body. each columnar body includes a first semiconductor part extending in the first direction, a first insulation part between the first semiconductor part and the stacked body, a second insulation part between the first insulation part and the stacked body, third insulation parts between the second insulation part and the first conductive films, and fourth insulation parts between the second insulation part and the first insulation films. each second insulation part has first portions between the first insulation part and the first conductive films and second portions between the first insulation part and the first insulation film. the second portions are thinner than the first portions in a second direction.
Inventor(s): Tomoo HISHIDA of Yokohama-shi JP for kioxia corporation, Yoshihisa IWATA of Yokohama-shi JP for kioxia corporation
IPC Code(s): H10B43/27, G11C5/02, G11C5/04, G11C5/06, G11C7/18, G11C8/12, G11C16/04, H01L23/528, H01L29/792, H10B43/30, H10B43/50
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
20250098173. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kojiro SHIMIZU of Yokkaichi JP for kioxia corporation
IPC Code(s): H10B43/50, H10B43/10, H10B43/27
CPC Code(s): H10B43/50
Abstract: according to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. the second area includes a first contact area including first to third sub-areas. the conductive layers include first to fourth conductive layers. the first conductive layer includes a first terrace portion in the first sub-area. the second conductive layer includes a second terrace portion in the third sub-area. the third conductive layer includes a third terrace portion in the first sub-area. the fourth conductive layer includes a fourth terrace portion in the third sub-area.
20250098247. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Tomohiro KOSUGI of Yokkaichi Mie JP for kioxia corporation
IPC Code(s): H01L29/04, H01L29/16, H10B43/30
CPC Code(s): H10D62/40
Abstract: according to one embodiment, a semiconductor storage device has a laminated body comprising conductive layers alternating with insulating layers in a first direction. a column extends into the laminated body and includes a first polycrystalline semiconductor film extending along the column in the first direction and a first insulating film extending along the column in the first direction. the first insulating film is between the conductive layers and the first polycrystalline semiconductor film. the first polycrystalline semiconductor film includes a first section corresponding in position along the first direction to an uppermost conductive layer among the conductive layers in the laminated body and a second section that is between the first section and a substrate in the first direction. an average grain diameter of the first section is smaller than an average grain diameter of the second section.
Inventor(s): Masaya NAKATA of Yokkaichi Mie JP for kioxia corporation, Kota TAKAHASHI of Yokkaichi Mie JP for kioxia corporation, Yusuke MIKI of Yokkaichi Mie JP for kioxia corporation, Takuma DOI of Yokkaichi Mie JP for kioxia corporation, Kazuhiro MATSUO of Kuwana Mie JP for kioxia corporation, Akifumi GAWASE of Kuwana Mie JP for kioxia corporation, Kenichiro TORATANI of Yokkaichi Mie JP for kioxia corporation
IPC Code(s): H01L29/26, C23C16/52, H01J37/32, H01L21/02, H01L21/3213, H01L29/66
CPC Code(s): H10D62/80
Abstract: a semiconductor device manufacturing method of embodiments includes: forming a first conductive film containing indium on a substrate; forming a first insulating film; forming a second conductive film; forming a second insulating film; forming an opening penetrating the second insulating film, the second conductive film, and the first insulating film to reach the first conductive film; forming a third insulating film in the opening so as to be in contact with bottom and side surfaces of the opening; removing the third insulating film at a bottom of the opening to expose the first conductive film at the bottom of the opening; performing a first treatment using a first gas containing silicon or a second treatment using a second gas containing oxygen; and forming a semiconductor film in the opening without exposing the substrate to an atmosphere with a pressure equal to or more than atmospheric pressure.
20250098544. MANUFACTURING APPARATUS AND MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takuya SHIMANO of Seoul KR for kioxia corporation, Kenichi YOSHINO of Seongnam-si Gyeonggi-do KR for kioxia corporation, Naoki AKIYAMA of Seoul KR for kioxia corporation
IPC Code(s): H10N50/01, H10B61/00, H10N50/10, H10N50/80
CPC Code(s): H10N50/01
Abstract: according to one embodiment, a manufacturing apparatus includes: a wafer holding unit configured to hold a wafer; an ion source configured to output an ion beam; a shutter holding unit configured to hold a shutter and place the shutter between the wafer holding unit and the ion source in a case of preventing irradiation of the wafer with the ion beam; and a target holding unit configured to hold a target including a through hole, and place the target between the wafer holding unit and the ion source in a case of forming, on the wafer, a first layer including a member of the target.
20250098545. MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kenji FUKUDA of Seoul KR for kioxia corporation, Tadaaki OIKAWA of Seoul KR for kioxia corporation, Kazuya SAWADA of Seoul KR for kioxia corporation, Soichi OIKAWA of Seoul KR for kioxia corporation
IPC Code(s): H10N50/10, G11C11/16, H10B61/00, H10N50/85
CPC Code(s): H10N50/10
Abstract: according to one embodiment, a magnetic memory device includes a first ferromagnetic layer having a fixed magnetization direction, a second ferromagnetic layer having a variable magnetization direction, a first nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, and a second nonmagnetic layer provided on an opposite side to a side on which the first nonmagnetic layer is provided with respect to the second ferromagnetic layer. at least one of the first nonmagnetic layer and the second nonmagnetic layer is an oxide layer including magnesium (mg) and a group element. the group element includes at least one element selected from a group consisting of zirconium (zr), hafnium (hf), and rutherfordium (rf).
- Kioxia Corporation
- G01R1/073
- G01R31/28
- CPC G01R1/07314
- Kioxia corporation
- G06F1/18
- CPC G06F1/183
- G06F1/26
- G11C5/14
- G11C16/04
- G11C16/30
- H02M3/04
- CPC G06F1/26
- G06F3/06
- CPC G06F3/0613
- G06F11/20
- G06F12/0802
- CPC G06F3/0688
- G06F11/10
- CPC G06F11/1068
- G06F12/02
- CPC G06F12/0246
- G06F12/1009
- CPC G06F12/0292
- G06F13/40
- G06F13/16
- CPC G06F13/40
- G06F16/2455
- G06F16/22
- CPC G06F16/24561
- G06F21/79
- G06F21/64
- CPC G06F21/79
- G06N20/00
- CPC G06N20/00
- G11C5/06
- G11C11/22
- H10B51/10
- H10B51/20
- CPC G11C5/06
- G11C5/08
- H10B61/00
- H10N50/10
- CPC G11C5/08
- G11C7/22
- G06F1/08
- G06F13/18
- G06F13/42
- G11C7/10
- CPC G11C7/222
- G11C11/16
- CPC G11C11/1655
- CPC G11C11/1673
- G11C11/56
- G11C16/34
- G11C29/04
- G11C29/52
- H03M13/29
- CPC G11C11/5642
- G11C13/00
- CPC G11C13/004
- CPC G11C13/0069
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- CPC G11C16/0483
- G11C16/08
- G11C16/10
- G11C16/16
- G11C16/24
- G11C16/32
- H10B69/00
- CPC G11C16/08
- G11C16/26
- H01L25/065
- H10B43/30
- H10B43/40
- CPC G11C16/10
- G11C16/14
- CPC G11C16/14
- G06N3/0455
- CPC G11C16/30
- G11C16/12
- CPC G11C16/3404
- CPC G11C16/3459
- G11C29/50
- G01R31/317
- CPC G11C29/50004
- CPC G11C29/52
- H01L21/67
- CPC H01L21/67034
- H01L21/683
- H01L21/687
- CPC H01L21/6835
- H01L23/498
- H01L23/00
- H01L23/31
- H01L23/34
- H01L25/10
- CPC H01L23/49838
- H01L23/522
- H01L23/528
- CPC H01L23/5226
- H01L23/64
- H01L25/18
- CPC H01L23/5227
- H03K3/037
- H03K19/21
- CPC H03K3/037
- H03L7/089
- H03L7/093
- H03L7/099
- CPC H03L7/0895
- H03M13/11
- H03M13/00
- CPC H03M13/1108
- H04L1/00
- H04L1/1607
- CPC H04L1/0072
- H04L12/42
- H04L12/40
- CPC H04L12/42
- H04L25/03
- H04L25/02
- CPC H04L25/03878
- H05K1/11
- H01L23/367
- H05K1/18
- H10B80/00
- CPC H05K1/117
- H10B12/00
- CPC H10B12/30
- H01L29/66
- H01L29/788
- CPC H10B41/27
- CPC H10B43/27
- G11C5/02
- G11C5/04
- G11C7/18
- G11C8/12
- H01L29/792
- H10B43/50
- CPC H10B43/50
- H01L29/04
- H01L29/16
- CPC H10D62/40
- H01L29/26
- C23C16/52
- H01J37/32
- H01L21/02
- H01L21/3213
- CPC H10D62/80
- H10N50/01
- H10N50/80
- CPC H10N50/01
- H10N50/85
- CPC H10N50/10