Kioxia Corporation patent applications on December 19th, 2024
Patent Applications by Kioxia Corporation on December 19th, 2024
Kioxia Corporation: 25 patent applications
Kioxia Corporation has applied for patents in the areas of H10B43/27 (7), H01L23/528 (4), H01L23/00 (4), G11C16/08 (4), H10B80/00 (4) G11C16/08 (2), H01L25/0652 (2), H01L23/5283 (2), G03F7/162 (1), H01L23/5226 (1)
With keywords such as: memory, semiconductor, layer, film, device, cell, portion, conductive, data, and substrate in patent application abstracts.
Patent Applications by Kioxia Corporation
Inventor(s): Tomoya AKAZAWA of Yokkaichi (JP) for kioxia corporation
IPC Code(s): G03F7/16, B05C5/02, B05C13/00, H01L21/66
CPC Code(s): G03F7/162
Abstract: according to one embodiment, a coating processing apparatus includes a rotary table being rotatable while holding a substrate on which a coating film is to be formed; a first discharge part discharging a first coating liquid to a first discharge position that is a central portion of the substrate to form a first liquid film; a second discharge part discharging a second coating liquid to a second discharge position outside the first discharge position of the substrate to form a second liquid film; an imaging device configured to image contours of the first and second liquid films spreading outside the substrate by rotation of the substrate; and a control device configured to control at least one of a rotation speed of the substrate and the second discharge position based on an imaging result by the imaging device so that a distance between the contours falls within a predetermined range.
Inventor(s): Yoshio MIZUTA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): G03F7/00
CPC Code(s): G03F7/70516
Abstract: an exposure apparatus according to one embodiment includes a stage and a control device. in an exposure process, the control device is configured to: calculate a calculated value of a magnification component by performing function approximation on measurement results of three or more alignment marks arranged on the substrate; set a first lower limit value and/or a first upper limit value for an alignment correction value of a magnification component; in a case where the first lower limit value is set and the calculated value is less than the first lower limit value, set the alignment correction value of the magnification component to a second correction value that is larger than the calculated value and smaller than the first correction value.
20240419200. VOLTAGE REGULATOR_simplified_abstract_(kioxia corporation)
Inventor(s): Masayuki USUDA of Ota Tokyo (JP) for kioxia corporation
IPC Code(s): G05F1/569, G05F1/575
CPC Code(s): G05F1/569
Abstract: a voltage regulator includes an operational amplifier that compares a feedback voltage that is proportional to an output voltage and a predetermined reference voltage that corresponds to a desired output voltage. the operational amplifier controls the conduction state of an output transistor according to the comparison. a detecting circuit monitors the operating state of the operational amplifier, and in the case that the operational amplifier is not operating, outputs a signal which causes the output transistor to be placed in a non-conductive state.
20240419236. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Akihiro KIMURA of Aichi (JP) for kioxia corporation, Hiroki MATSUSHITA of Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F1/3234, G06F3/06, G06F11/14, G06F12/02, G11C5/14
CPC Code(s): G06F1/3275
Abstract: according to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. the controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.
20240419359. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Koichi NAGAI of Ota (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: according to one embodiment, a controller of a memory system manages a current extended pointer that includes a pointer and cycle counter. the controller identifies, for each time the first time elapses, a first time range whose an end time matches a time that is prior to a specific time from a current time. the controller acquires a first extended pointer stored in a first entry among the plurality of entries that corresponds to the first time range. the controller identifies one or more commands stored in the first queue within the first time range by using the first extended pointer. the controller aborts the identified one or more commands.
20240419528. INFORMATION PROCESSING APPARATUS AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Fumio YOSHIYA of Tachikawa Tokyo (JP) for kioxia corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0769
Abstract: an information processing apparatus includes a processor, an interface circuit connectable to a device external to the information processing apparatus, a memory accessible by the processor and accessible by the device via the interface circuit; and a signal processing circuit. the signal processing circuit is disposed in a signal path between the interface circuit and the memory and configured to detect output of data read from the memory even when the interface circuit receives a read request from the device and causes the memory to perform a read operation in response to the read request, and generate an error notification when the memory notifies the signal processing circuit of normal output of the data. the interface circuit is configured to return, to the device, an error response corresponding to the error notification in response to the read request.
20240419536. MEMORY CONTROLLER AND MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Masaki NAKAMURA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: a memory controller includes a memory interface circuit, a memory device, and an error correction circuit. the memory interface circuit receives, during a read operation executed in a semiconductor memory device, a data signal from the semiconductor memory device to acquire the data from the data signal. the error correction circuit is configured to store in the memory device likelihood information of the data acquired from the data signal, revise the likelihood information of the data acquired from the data signal, and perform an error correction process on the data based on the revised likelihood information.
20240420764. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroshi MAEJIMA of Tokyo (JP) for kioxia corporation
IPC Code(s): G11C16/08, H01L23/00, H01L25/065, H01L25/18, H10B80/00
CPC Code(s): G11C16/08
Abstract: according to one embodiment, a memory device includes: a first chip including a first memory cell array; a second chip in contact with the first chip and including a second memory cell array; and a third chip in contact with the second chip and including a control circuit. the first memory cell array includes first and second transistors coupled in series. the second memory cell array includes third and fourth transistors coupled in series. the control circuit includes: fifth, sixth, and seventh transistors respectively having first ends coupled to gates of the first, third, and second and fourth transistors; a first decoder configured to switch a state of the fifth transistor; and a second decoder configured to switch a state of the sixth transistor independently of the state of the fifth transistor.
20240420765. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Mai SHIMIZU of Kamakura Kanagawa (JP) for kioxia corporation, Koji KATO of Yokohama Kanagawa (JP) for kioxia corporation, Yoshihiko KAMATA of Yokohama Kanagawa (JP) for kioxia corporation, Mario SAKO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/08, G11C11/56, G11C16/04, G11C16/24, G11C16/26, G11C16/30, G11C16/32, G11C16/34
CPC Code(s): G11C16/08
Abstract: a semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. during a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
Inventor(s): Jun NAKAI of Yokohama (JP) for kioxia corporation, Noboru SHIBATA of Kawasaki (JP) for kioxia corporation
IPC Code(s): G11C16/16, G11C16/14, G11C16/26, G11C16/34
CPC Code(s): G11C16/16
Abstract: according to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. the memory cell array includes a plurality of memory cells arranged in a matrix. the control unit erases data of the memory cells. the control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
20240420778. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Tsukasa TOKUTOMI of Kamakura (JP) for kioxia corporation, Masanobu SHIRAKAWA of Chigasaki (JP) for kioxia corporation, Kengo KUROSE of Tokyo (JP) for kioxia corporation, Marie TAKADA of Yokohama (JP) for kioxia corporation, Ryo YAMAKI of Yokohama (JP) for kioxia corporation, Kiyotaka IWASAKI of Yokohama (JP) for kioxia corporation, Yoshihisa KOJIMA of Kawasaki (JP) for kioxia corporation
IPC Code(s): G11C16/26, G06F3/06, G06F11/10, G11C11/56, G11C16/04, G11C16/08, G11C29/52, H10B43/27, H10B43/35
CPC Code(s): G11C16/26
Abstract: according to one embodiment, a memory system includes a nonvolatile memory and a memory controller. the memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.
20240420782. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroki DATE of Chigasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/34, G11C16/08, G11C16/10
CPC Code(s): G11C16/3459
Abstract: according to one embodiment, a semiconductor memory device includes a first memory cell and a second memory cell arranged adjacent to each other and coupled in series; and a control circuit, wherein the control circuit is configured to: at a time of the program operation in a first program loop operation targeted for the first memory cell, during a first period, while suppling a first write voltage to the first memory cell, supply a first voltage smaller than the first write voltage to the second memory cell, and during a second period, while supplying a second voltage smaller than the first voltage to the first memory cell, supply a third voltage greater than the second voltage to the second memory cell.
Inventor(s): Shunsuke OKADA of Suzuka (JP) for kioxia corporation, Yoshifumi NISHIO of Kuwana (JP) for kioxia corporation
IPC Code(s): H01L21/66, G01K11/00, H01L21/02, H01L21/265
CPC Code(s): H01L22/20
Abstract: a semiconductor wafer temperature measurement method according to the present embodiment includes introducing an impurity into a first surface of a wafer to form an amorphous layer on a side of the first surface of the wafer. the present temperature measurement method includes measuring a first film thickness that is the film thickness of the amorphous layer. the present temperature measurement method includes thermally treating the wafer to recrystallize part of the amorphous layer. the present temperature measurement method includes measuring a second film thickness that is the film thickness of the amorphous layer after the thermal treatment. the present temperature measurement method includes measuring the temperature of the wafer at the thermal treatment based on a film thickness difference between the first film thickness and the second film thickness.
20240421071. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Ha HOANG of Kuwana Mie (JP) for kioxia corporation, Kazuhiro MATSUO of Kuwana Mie (JP) for kioxia corporation, Mutsumi OKAJIMA of Yokkaichi Mie (JP) for kioxia corporation, Takamitsu OCHI of Nagoya Aichi (JP) for kioxia corporation, Tsuyoshi SUGISAKI of Yokkaichi Mie (JP) for kioxia corporation, Isamu UJIIE of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L23/522, G11C5/06, H01L23/528, H10B41/10, H10B41/27, H10B43/10, H10B43/27
CPC Code(s): H01L23/5226
Abstract: a semiconductor memory device includes a plurality of memory layers arranged in a first direction, a first via-wiring extending in the first direction, a second via-wiring in a position different from a position of the first via-wiring in a second direction and extending in the first direction. one of the plurality of memory layers includes a first wiring disposed between the first and the second via-wiring and extending in a third direction, a first semiconductor layer electrically connected to the first via-wiring, a first gate electrode opposed to the first semiconductor layer and electrically connected to the first wiring, a first memory portion electrically connected to the first semiconductor layer, a second semiconductor layer electrically connected to the second via-wiring, a second gate electrode opposed to the second semiconductor layer and electrically connected to the first wiring, and a second memory portion electrically connected to the second semiconductor layer.
Inventor(s): Tatsuya KOGISO of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H01L23/528, H10B41/20
CPC Code(s): H01L23/5283
Abstract: in one embodiment, a semiconductor device includes a first insulator, and a first interconnect including a first layer that is provided on side and upper faces of the first insulator in the first insulator, and includes a first element as a metal element, and a second layer that is provided on side and upper faces of the first layer in the first insulator, and includes a second element as a metal element different from the first element, and a third element different from the first and second elements. the second layer includes a first portion, an intermediate region, and a second portion that are provided on the side face of the first layer in order. a concentration of the third element in the intermediate region is higher than that of the third element in the first portion, and that of the third element in the second portion.
Inventor(s): Kyosuke NANAMI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L23/528, H01L23/532, H10B41/27, H10B43/27
CPC Code(s): H01L23/5283
Abstract: a semiconductor storage device includes a stacked body having a plurality of conductive layers and a plurality of first insulating layers that are alternately stacked, and a staircase portion in which the plurality of conductive layers have been processed into a staircase shape, a contact disposed in the staircase portion and connected to a first conductive layer, which is one of the plurality of conductive layers, and a first pillar that extends in a stacking direction of the stacked body in a portion of the stacked body different from the staircase portion and forms memory cells at each intersection of the first pillar and at least a part of the plurality of conductive layers. the contact penetrates a second conductive layer, which is not one of the plurality of conductive layers and disposed above the first conductive layer, and reaches the first conductive layer to be in contact therewith.
20240421121. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Masayuki MIURA of Ota Tokyo (JP) for kioxia corporation, Kazuma HASEGAWA of Fujisawa Kanagawa (JP) for kioxia corporation, Hideko MUKAIDA of Taito Tokyo (JP) for kioxia corporation, Kana KUDO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L25/065, H10B80/00
CPC Code(s): H01L25/0652
Abstract: a semiconductor device according to an embodiment includes a substrate, a first stack, a second stack, a first bonding layer, a second bonding layer, a first wire, and a second wire. the first stack has a plurality of first semiconductor chips. the second stack has a plurality of second semiconductor chips. the first bonding layer is provided at a lower part of each of the plurality of first semiconductor chips. the second bonding layer is provided at a lower part of each of the plurality of second semiconductor chips. the first wire electrically connects the first semiconductor chips and the second semiconductor chips to one another. the second wire electrically connects the substrate and the second semiconductor chips. the first bonding layer provided at the lower part of the first semiconductor chip in a lowest stage has a thickness different from the thickness of the other first bonding layers.
20240421122. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Masayuki MIURA of Ota (JP) for kioxia corporation, Kazuma HASEGAWA of Fujisawa (JP) for kioxia corporation, Yuichi SANO of Setagaya (JP) for kioxia corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/498, H01L23/528, H10B80/00
CPC Code(s): H01L25/0652
Abstract: a semiconductor device according to an embodiment includes a substrate, a plurality of first semiconductor chips, a plurality of first resins, and a second semiconductor chip. the substrate has a first surface. the plurality of first semiconductor chips are stacked while being displaced in a direction substantially parallel to the first surface. the plurality of first resins are provided on respective lower surfaces of the plurality of first semiconductor chips. the second semiconductor chip is provided on the first surface. at least one of the plurality of first resins is in contact with an upper surface of the second semiconductor chip.
Inventor(s): Huy Cu NGO of Isehara Kanagawa (JP) for kioxia corporation
IPC Code(s): H03K5/135, H03K3/037, H03K19/00
CPC Code(s): H03K5/135
Abstract: according to one embodiment, a semiconductor integrated circuit includes: a first buffer including an input end to which a first signal is configured to be supplied; a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node; a first capacitor including a first end coupled to the first node and a grounded second end; a second switching element including a first end coupled to the first node and a second end coupled to a second node; a second buffer including an input end coupled to the second node; and a first converter configured to determine a first bit string from a first output from the second buffer. the first and second switching elements being configured to switch between states based on a first clock signal.
Inventor(s): Taichi EJIRI of Yokohama Kanagawa (JP) for kioxia corporation, Kentaro UMESAWA of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): H04L9/32, H04L9/08
CPC Code(s): H04L9/3247
Abstract: an information processing device includes a first determination unit that determines whether instruction information for issuing an instruction to switch from a first verification method of verifying validity of firmware by using a digital signature generated based on public key encryption to a second verification method of verifying the validity of the firmware by using a message authentication code generated using a message authentication key generated based on a random number has been received, a random number generator that generates the random number, a first generation unit that generates the message authentication key used to generate the message authentication code, based on the random number, when it is determined by the first determination unit that the instruction information has been received, and a second generation unit that generates the message authentication code of the firmware using the message authentication key.
20240422971. SEMICONDUCTOR STORAGE DEVICE WITH PILLAR_simplified_abstract_(kioxia corporation)
Inventor(s): Kazuharu YAMABE of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/20, H01L23/00, H10B41/10, H10B41/20, H10B41/40, H10B43/10, H10B43/40
CPC Code(s): H10B43/20
Abstract: a semiconductor storage device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers, a first gate insulating film that extends in the first direction and covers an outer peripheral surface of the first semiconductor layer, a first insulating layer that extends in the first direction and has an outer peripheral surface covered with the first semiconductor layer, and a second conductive layer that is farther from the substrate than the plurality of first conductive layers and is connected to one end in the first direction of the first semiconductor layer. the first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region. the second conductive layer is connected to an inner peripheral surface and an outer peripheral surface of the second region of the first semiconductor layer and is in contact with one end in the first direction of the first insulating layer.
Inventor(s): Kazuki MATSUNAGA of Yokkaichi Mie (JP) for kioxia corporation, Shinya OKUDA of Yokkaichi Mie (JP) for kioxia corporation, Shuichi TSUBATA of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: a semiconductor device includes a stacked film including electrode layers and first insulating films alternately stacked in a first direction, wherein the stacked film includes a first portion with a non-stepped shape and a second portion with a stepped shape; a second insulating film provided on the second portion; a columnar portion extending through the first portion and including a charge storage layer; a third insulating film extending through the second portion and the second insulating film; a plug provided on any of the electrode layers in the second portion; and a first region provided in the second portion and the second insulating film and including an element. a concentration of the element in the first region is higher than a concentration of the element in a region outside the first region in the second insulating film.
Inventor(s): Daisuke KITAGAWA of Yokkaichi Mie (JP) for kioxia corporation, Kensei TAKAHASHI of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H10B43/30, H10B43/27
CPC Code(s): H10B43/30
Abstract: a semiconductor device according to the present embodiment includes a first insulator, a conductive layer, and a film. the film is provided between the first insulator and the conductive layer and contains carbon (c) or silicon (si). the semiconductor device further comprises a stacked body in which insulating layers and the conductive layers are alternately stacked in a first direction, a semiconductor layer disposed in the first direction in the stacked body, a second insulator disposed in the first direction between the stacked body and the semiconductor layer, a third insulator disposed in the first direction between the stacked body and the second insulator, and a fourth insulator disposed in the first direction between the stacked body and the third insulator. the first insulator is disposed between the conductive layers and the insulating layers and between the conductive layers and the fourth insulator.
Inventor(s): Hiroki TOKUHIRA of Kawasaki (JP) for kioxia corporation, Takahisa KANEMURA of Yokohama (JP) for kioxia corporation, Shigeo KONDO of Yokkaichi (JP) for kioxia corporation, Michiru HOGYOKU of Yokohama (JP) for kioxia corporation
IPC Code(s): H10B43/35, H01L21/28, H10B43/27
CPC Code(s): H10B43/35
Abstract: a semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. the semiconductor pillar includes a first part, a second part, and a third part. the charge storage film includes a first charge storage portion and a second charge storage portion. the charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. the insulating film provides in at least a portion between the intermediate conductive layer and the first part. the insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
20240422985. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Tomoaki SHINO of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B43/40, G11C16/30, H01L23/00, H01L25/065, H01L25/18, H10B43/27, H10B80/00
CPC Code(s): H10B43/40
Abstract: a transistor for a semiconductor memory device includes a gate insulating film on a semiconductor substrate, a gate electrode on the gate insulating film, a side wall insulating film on both side surfaces of the gate electrode, a first diffusion layer disposed in the semiconductor substrate, connected to a contact electrode extending in a first direction intersecting a surface of the semiconductor substrate, and containing a first conductive-type impurity, a second diffusion layer disposed in the semiconductor substrate between the first diffusion layer and a region of the semiconductor substrate underneath the gate electrode, and containing the first conductive-type impurity, and a third diffusion layer disposed in the semiconductor substrate between the first diffusion layer and the second diffusion layer, connected to the second diffusion layer, and containing the first conductive-type impurity. a concentration of the second diffusion layer is higher than a concentration of the third diffusion layer.
Kioxia Corporation patent applications on December 19th, 2024
- Kioxia Corporation
- G03F7/16
- B05C5/02
- B05C13/00
- H01L21/66
- CPC G03F7/162
- Kioxia corporation
- G03F7/00
- CPC G03F7/70516
- G05F1/569
- G05F1/575
- CPC G05F1/569
- G06F1/3234
- G06F3/06
- G06F11/14
- G06F12/02
- G11C5/14
- CPC G06F1/3275
- CPC G06F3/0659
- G06F11/07
- CPC G06F11/0769
- G06F11/10
- CPC G06F11/1004
- G11C16/08
- H01L23/00
- H01L25/065
- H01L25/18
- H10B80/00
- CPC G11C16/08
- G11C11/56
- G11C16/04
- G11C16/24
- G11C16/26
- G11C16/30
- G11C16/32
- G11C16/34
- G11C16/16
- G11C16/14
- CPC G11C16/16
- G11C29/52
- H10B43/27
- H10B43/35
- CPC G11C16/26
- G11C16/10
- CPC G11C16/3459
- G01K11/00
- H01L21/02
- H01L21/265
- CPC H01L22/20
- H01L23/522
- G11C5/06
- H01L23/528
- H10B41/10
- H10B41/27
- H10B43/10
- CPC H01L23/5226
- H10B41/20
- CPC H01L23/5283
- H01L23/532
- CPC H01L25/0652
- H01L23/31
- H01L23/498
- H03K5/135
- H03K3/037
- H03K19/00
- CPC H03K5/135
- H04L9/32
- H04L9/08
- CPC H04L9/3247
- H10B43/20
- H10B41/40
- H10B43/40
- CPC H10B43/20
- CPC H10B43/27
- H10B43/30
- CPC H10B43/30
- H01L21/28
- CPC H10B43/35
- CPC H10B43/40