KABUSHIKI KAISHA TOSHIBA patent applications on March 27th, 2025
Patent Applications by KABUSHIKI KAISHA TOSHIBA on March 27th, 2025
KABUSHIKI KAISHA TOSHIBA: 33 patent applications
KABUSHIKI KAISHA TOSHIBA has applied for patents in the areas of H01L29/06 (8), H01L29/66 (6), H01L23/00 (6), H01L29/739 (5), H01L29/78 (5) H10D12/481 (3), H10D30/668 (2), H01L24/05 (2), H01L23/49838 (2), B23K3/08 (1)
With keywords such as: semiconductor, region, insulating, electrode, part, third, device, surface, portion, and fourth in patent application abstracts.
Patent Applications by KABUSHIKI KAISHA TOSHIBA
20250100059. HEAT TREATMENT FURNACE APPARATUS_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Masanori HOSHINO of Yokohama JP for kabushiki kaisha toshiba, Hiromasa KATO of Nagareyama JP for kabushiki kaisha toshiba, Hideki SATO of Yokohama JP for kabushiki kaisha toshiba
IPC Code(s): B23K3/08, B23K3/04, B23K103/18
CPC Code(s): B23K3/08
Abstract: a heat treatment furnace apparatus according to an embodiment heats, when a metal plate is brazed to a ceramic substrate, at least one storage container made of stainless steel, in which a plurality of ceramic metal substrates are stored, to subject the plurality of ceramic metal substrates to a heat treatment at 600 degrees celsius or more and less than 950 degrees celsius. the heat treatment furnace apparatus includes: a heater provided outside a furnace body;
20250100059. HEAT TREATMENT FURNACE APPARATUS_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Masanori HOSHINO of Yokohama JP for kabushiki kaisha toshiba, Hiromasa KATO of Nagareyama JP for kabushiki kaisha toshiba, Hideki SATO of Yokohama JP for kabushiki kaisha toshiba
IPC Code(s): B23K3/08, B23K3/04, B23K103/18
CPC Code(s): B23K3/08
Abstract: a rail section that transports the storage container placed inside the furnace body; and a transport device that transports the storage container placed on the rail section in a predetermined transport direction along the rail section while moving the storage container in a direction perpendicular to the rail section.
Inventor(s): Takafumi USHIYAMA of Sagamihara JP for kabushiki kaisha toshiba, Atsushi SUGAHARA of Kawasaki JP for kabushiki kaisha toshiba
IPC Code(s): B65G47/91
CPC Code(s): B65G47/917
Abstract: according to one embodiment, a control device controls a holding device capable of holding an object. the control device calculates a first position at which a first object is held by the holding device. the control device determines whether the holding device is capable of coming into contact with another object when the holding device is present at the first position. in a case where the holding device is capable of coming into contact with the other object, the control device calculates a second position at which the holding device comes into contact with the first object and does not come into contact with the other object.
Inventor(s): Akiyo MIZUTANI of Kawasaki Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): G01N29/02, G01N29/24, G01N33/00, G11B33/06
CPC Code(s): G01N29/022
Abstract: a disk device according to one embodiment includes a housing, a magnetic disk, a circuit board, a first oscillator, and a first adsorption film. the housing is provided with an internal space. the magnetic disk is disposed in the internal space. the circuit board is attached to the housing outside the internal space. the first oscillator is disposed away from an electric circuit in the internal space. the electric circuit is electrically connected to the circuit board. the first adsorption film is formed on the first oscillator, exposed to the internal space, and configured to adsorb a first substance.
Inventor(s): Takeshi Yasuda of Yokohama Kanagawa JP for kabushiki kaisha toshiba, Toshiaki Yoshida of Kawasaki Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): G05D1/683, A01M29/16, F41H13/00, G05D105/50, G05D109/20, G05D111/30
CPC Code(s): G05D1/683
Abstract: according to an embodiment, a hunting drone includes a hunting mechanism, a net gun, a flying mechanism, and a control unit. the hunting mechanism captures a target. the net gun generates a sound at the time of firing a hunting net. after approaching the target to a predetermined distance, the hunting drone captures the target using the hunting mechanism, while avoiding false recognition of the target by using the sound generated at the time of firing the net gun as a threatening sound to repel a wrong target such as a bird.
Inventor(s): Xiaotao SHAN of Bristol GB for kabushiki kaisha toshiba, Marius David JURT of Bristol GB for kabushiki kaisha toshiba, Yichao JIN of Bristol GB for kabushiki kaisha toshiba
IPC Code(s): G05D1/698
CPC Code(s): G05D1/698
Abstract: provided is a decentralised multi-robot task allocation method comprising: performing, by a first robot of a plurality of robots, the steps of: obtaining information regarding a new task comprising at least one single robot task, srt, and at least one multi-robot task, mrt; determining which srts each remaining robot of the plurality of robots is likely to select; determining a preferred mrt for the first robot to perform, and potential coalition partners for performing the preferred mrt with the first robot; consulting with the remaining robots of the plurality of robots to determine a coalition of robots including the first robot to perform an mrt of the at least one mrt; and performing at least one of the at least one srt or the at least one mrt based on the determination of which srts each robot from the subset of robots is likely to select, the determination of which mrts each robot from the subset of robots is likely to select, and the consultation.
20250103080. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Tomohiro ANDO of Yokohama Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): G05F3/26, G01R19/00, H03F3/45
CPC Code(s): G05F3/262
Abstract: according to one embodiment, a semiconductor device includes: a first circuit configured to drive a load couplable to a first terminal by supplying a load current to the load; and a third circuit including a second circuit configured to copy the load current based on a first voltage of the first terminal and output a first current obtained by copying the load current, the third circuit being configured to monitor a second current based on the first current. the third circuit further includes a fourth circuit configured to adjust the second current in a case where the load current is not supplied to the load.
Inventor(s): Alexander HERZOG of Bristol GB for kabushiki kaisha toshiba, Marcello BULLO of Bristol GB for kabushiki kaisha toshiba, Pietro Edoardo CARNELLI of Bristol GB for kabushiki kaisha toshiba, Aftab KHAN of Bristol GB for kabushiki kaisha toshiba
IPC Code(s): G06N3/098
CPC Code(s): G06N3/098
Abstract: a computer-implemented method for training a machine learning model in a distributed system, the distributed system comprises a plurality of nodes that exchange updates to communally train the machine learning model. each node of the plurality of nodes maintains a local version of the machine learning model. the local version of the machine learning model of each of the plurality of nodes has been initialised with the same one or more respective parameter values. the method comprises a node: receiving an update to a local model from at least one other node in the distributed system, the local model comprising the local version of the machine learning model and the update comprising a dense array of one or more first parameter deltas, the one or more first parameter deltas being ordered in the dense array in an order determined by a reference model, each first parameter delta representing a difference between a parameter of the local model and a corresponding parameter of an updated version of the machine learning model that is maintained by the at least other node; updating the local model based on the received update and the reference model to determine an updated local model; determining one or more second parameter deltas, each second parameter delta representing a difference between a parameter of the updated local model and a corresponding parameter of a previous version of the local model; and sending an update to the at least one other node in the distributed system, wherein the update comprises a dense array of the one or more second parameter deltas, the one or more second parameter deltas being ordered in the dense array in an order determined by the reference model.
Inventor(s): Kazuhide SAWA of Kawasaki JP for kabushiki kaisha toshiba, Seiji TOKURA of Kawasaki JP for kabushiki kaisha toshiba, Kazuma HIRAGURI of Yokohama JP for kabushiki kaisha toshiba, Harutoshi CHATANI of Yokohama JP for kabushiki kaisha toshiba, Akihito OGAWA of Fujisawa JP for kabushiki kaisha toshiba
IPC Code(s): G06T7/00, B25J9/16, G06T7/70, G06V20/52
CPC Code(s): G06T7/0004
Abstract: according to one embodiment, a processing device is configured to obtain first events indicating that a holding part of a handling robot has passed through respective predetermined passing-through positions. the processing device is configured to obtain a plurality of images of the handling robot. the processing device is configured to identify, when obtaining a second event indicating an abnormality in the handling robot, a first period that is between two of the plurality of first events and includes occurrence timing of the second event, or a second period that is from one of the plurality of first events immediately before the occurrence timing to the occurrence timing. the processing device is configured to extract at least one of the plurality of images obtained in the first period or the second period from the plurality of images.
20250104734. DISK APPARATUS_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Yusuke NOJIMA of Yokohama Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): G11B5/48, G11B5/53, G11B5/82
CPC Code(s): G11B5/4833
Abstract: a disk apparatus includes a carriage, a magnetic disk, a base plate, a load beam, a flexure, and a magnetic head. the carriage rotates around a first rotation axis. the base plate includes a first surface facing the magnetic disk and is attached to the carriage. the load beam is attached to the base plate. the flexure includes a plurality of wirings and is attached to the base plate and the load beam. the magnetic head is attached to the flexure and electrically connected to at least one of the plurality of wirings. the flexure includes a thin portion that is thinner than other portions of the flexure. the thin portion includes a first portion which covers the first surface and at which the plurality of wirings extends in non-parallel directions with respect to each other.
Inventor(s): Takao FURUHASHI of Kawasaki Kanagawa JP for kabushiki kaisha toshiba, Kaori KIMURA of Yokohama Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): G11B5/60, G11B5/00, G11B5/012, G11B5/02, G11B5/455
CPC Code(s): G11B5/607
Abstract: according to one embodiment, a method of adjusting a magnetic recording and reproducing device is a method of adjusting a magnetic recording and reproducing device incorporating a heat-assisted magnetic recording head and a magnetic disk, and the method includes performing a first write operation at a first position on a recording surface, measuring a first error rate at a second position different in radial position from the first position, performing a second write operation and then measuring a second error rate, obtaining a first difference between the first error rate and the second error rate, measuring a third error rate at the first position, performing a third write operation and then measuring a fourth error rate, calculating a second difference between the third error rate and the fourth error rate, comparing the first difference with the second difference and determining a change in flying height.
20250104740. MAGNETIC DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Tomoki YAGUCHI of Kawasaki Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): G11B33/04, G11B5/54, G11B5/82, G11B19/20
CPC Code(s): G11B33/045
Abstract: a magnetic disk device according to one embodiment includes a base, five or more magnetic disks in the base, a head actuator, and a spindle motor. the base has a bottom wall having a second thickness and a side wall. the spindle motor includes a sleeve with a first hole, fixed to the bottom wall, a shaft inserted in the first hole rotatably, and a hub rotatable integrally with the shaft. the hub includes a first part, a second part extending from a lowermost surface of the first part in a first direction being from the magnetic disks toward the bottom wall, and a third part having a first thickness and extending from a lowermost surface of the second part in a second direction orthogonal to the first direction. a value obtained by dividing the second thickness by the first thickness is greater than or equal to 1.89.
20250104741. DISK DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Shino ZAIMA of Kamakura Kanagawa JP for kabushiki kaisha toshiba, Akiyo MIZUTANI of Kawasaki Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): G11B33/14
CPC Code(s): G11B33/146
Abstract: according to one embodiment, a disk device includes a magnetic disk, a housing, a first filter unit, and a second filter unit. the housing is provided with an internal space and is provided with a first through hole. the first filter unit includes a first case with a first accommodation space which is in communication with the first through hole, a first adsorbent in the first accommodation space, and a first filter. the first accommodation space is in communication with the internal space through the first filter. the second filter unit includes a second case with a second accommodation space which is separated from the first accommodation space, a second adsorbent in the second accommodation space, and a second filter. the second accommodation space is in communication with the internal space through the second filter.
20250105014. ETCHING METHOD_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Hiroki KAWAKAMI of Yokohama JP for kabushiki kaisha toshiba, Kazuhito HIGUCHI of Yokohama JP for kabushiki kaisha toshiba, Susumu OBATA of Yokohama JP for kabushiki kaisha toshiba, Takayuki TAJIMA of Sagamihara JP for kabushiki kaisha toshiba
IPC Code(s): H01L21/306
CPC Code(s): H01L21/30604
Abstract: according to one embodiment, an etching method is provided. the etching method includes: forming a layer containing a first metal catalyst at a surface containing a semiconductor; first etching using the first metal catalyst; forming a layer containing a second metal catalyst having a larger diffusion coefficient than that of the first metal catalyst at the layer containing the first metal catalyst; and second etching using the second metal catalyst.
20250105067. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Taira TABAKOYA of Fuchu Tokyo JP for kabushiki kaisha toshiba, Toshihiro TSUJIMURA of Ota Tokyo JP for kabushiki kaisha toshiba
IPC Code(s): H01L23/04, H01L23/00, H01L23/498
CPC Code(s): H01L23/04
Abstract: a semiconductor device includes a first substrate, a second substrate, a first semiconductor element, a second semiconductor element, a connection conductor, a connection conductor, and a sealing part. the first substrate includes a first surface, a second surface, a first insulating substrate, and a first conductive layer. the second substrate includes a third surface, a fourth surface, a second insulating substrate, and a second conductive layer. the first semiconductor element includes a first semiconductor layer, a first electrode, a second electrode, and a first control electrode. the second semiconductor element includes a second semiconductor layer, a third electrode, a fourth electrode, and a second control electrode. the connection conductor electrically connects the first and fourth electrodes. the sealing part covers a portion of the first substrate, a portion of the second substrate, the first semiconductor element, and the second semiconductor element.
Inventor(s): Yoshihito YAMAGATA of Yokohama JP for kabushiki kaisha toshiba, Katsuyuki AOKI of Yokohama JP for kabushiki kaisha toshiba
IPC Code(s): H01L23/15, H01L23/498
CPC Code(s): H01L23/15
Abstract: a ceramic substrate according to an embodiment includes a ratio a/b of an arc discharge voltage a to a dielectric breakdown voltage b of not less than 0.3 when the arc discharge voltage a (kv) is measured when an arc discharge is detected when applying an ac voltage of 50 hz or 60 hz between a front surface and a back surface of the ceramic substrate at a voltage increase rate of 200 v/s, and when the dielectric breakdown voltage b (kv) between the front surface and the back surface is measured according to iec 672-2.
Inventor(s): Shunsuke SHOJI of Nomi Ishikawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L23/31, H01L21/782, H01L23/29, H01L29/739, H01L29/78
CPC Code(s): H01L23/3135
Abstract: a semiconductor device according to an embodiment includes: a semiconductor part including a first main surface and a second main surface on an opposite side of the first main surface; a surface structure part provided on the first main surface, the surface structure part including a first electrode; a second electrode provided on the second main surface; a first protective resin film configured to cover an upper surface of the surface structure part; and a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part.
20250105124. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Toyokazu SHIBATA of Kawasaki Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L23/498, H01L23/00
CPC Code(s): H01L23/49838
Abstract: a semiconductor device includes a first conductive member, a second conductive member, a semiconductor chip, a connection plate, a first bonding member, a second bonding member, and a resin part. the second conductive member includes a first part and a second part. the second part includes a lead part. the semiconductor chip is located between the first part and the first conductive member. the connection plate is located between the semiconductor chip and the first part. the first bonding member is positioned between the semiconductor chip and the connection plate. the second bonding member is positioned between the first part and the connection plate. the resin part covers the semiconductor chip, the connection plate, and the first part. the resin part does not cover a portion of the lead part and a portion of the first conductive member.
20250105125. ISOLATOR_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Daisuke KOIKE of Tama Tokyo JP for kabushiki kaisha toshiba
IPC Code(s): H01L23/498, H01L23/00, H01L25/065
CPC Code(s): H01L23/49838
Abstract: an isolator according to one embodiment, includes a substrate and a plurality of leads. the substrate includes a lower surface, a plurality of coils, and a plurality of conductive parts. the lower surface has a quadrilateral shape. the plurality of coils includes a first coil, and a second coil. the plurality of conductive parts includes a first conductive part, a second conductive part, a third conductive part, and a fourth conductive part. the first conductive part includes a first terminal. the second conductive part includes a second terminal. the third conductive part includes a third terminal. the fourth conductive part includes a fourth terminal. the plurality of leads includes a first lead, a second lead, a third lead, and a fourth lead. the plurality of leads includes a metal.
Inventor(s): Teppei TSUKAMOTO of Kamakura JP for kabushiki kaisha toshiba
IPC Code(s): H01L23/00, C25D5/02, C25D7/12, H01L21/768, H01L23/522, H01L23/528
CPC Code(s): H01L24/05
Abstract: a semiconductor device according to an embodiment includes a transistor, and a plurality of metal layers that is respectively arranged in a plurality of layers stacked above the transistor, in which the plurality of metal layers includes a first metal layer that is arranged in a lowermost layer of the plurality of layers, a second metal layer that is arranged in an uppermost layer of the plurality of layers and that is thicker than the first metal layer, and a third metal layer that is arranged in the uppermost layer and that is thicker than the second metal layer.
20250105177. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Shogo MINAMI of Ota Tokyo JP for kabushiki kaisha toshiba, Keiichiro MATSUO of Yokohama Kanagawa JP for kabushiki kaisha toshiba, Tetsuya YAMAMOTO of Sagamihara Kangawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L23/00, H01L23/31
CPC Code(s): H01L24/05
Abstract: a semiconductor device according to an embodiment including: a semiconductor element placed on an insulating substrate and having an electrode on a surface ; a bonding wire bonded to the electrode and electrically coupling the semiconductor element ; and a first resin material covering a bonding portion between the electrode and the bonding wire , the bonding portion includes a non-bonding region where the electrode and the bonding wire are not bonded.
20250105827. OSCILLATION CIRCUIT_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Kazuki MIYAO of Kawasaki Kanagawa JP for kabushiki kaisha toshiba, Tomoharu KAMBASHI of Hiratsuka Kanagawa JP for kabushiki kaisha toshiba, Hiroshi YOSHINO of Yokohama Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): H03K3/03, H03K17/687
CPC Code(s): H03K3/0315
Abstract: according to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.
20250105844. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Eriko Shigesawa of Tokyo JP for kabushiki kaisha toshiba, Akio Ogura of Yokohama Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): H03K19/017, H03K17/16, H03K17/30, H03K19/00
CPC Code(s): H03K19/01742
Abstract: according to one embodiment, a semiconductor device includes a first terminal which is coupled to a first node and to which a control signal is externally input, a first circuit coupled to the first node, configured to switch based on a logic level of the first node between a first state where a first voltage is not output to a second node and a second state where the first voltage is output to the second node, and configured to control a slew rate of an output voltage at a time of switching from the first state to the second state, and a second circuit including a switch circuit which includes one end coupled to the first node and another end applied with a second voltage, and configured to control the switch circuit based on a voltage at the second node.
20250107125. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Kazutoshi NAKAMURA of Nonoichi Ishikawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/739, H01L27/06, H01L29/06, H01L29/423, H01L29/861
CPC Code(s): H10D12/481
Abstract: a semiconductor device of embodiments includes a transistor region and a diode region. the transistor region includes: a first conductive type first semiconductor region, a second conductive type second semiconductor region, a first conductive type third semiconductor region in this order in a semiconductor layer; a second conductive type fourth semiconductor region and a first conductive type fifth semiconductor region on the third semiconductor region and arranged alternately in a first direction; a first conductive type sixth semiconductor region between the third and the fourth semiconductor region a first trench spaced from the sixth semiconductor region; a gate electrode in the first trench; a first electrode having a first portion, a bottom surface of the first portion being in contact with the third semiconductor region and side surfaces of the first portion being in contact with the fourth, the fifth, and the sixth semiconductor regions; and a second electrode.
Inventor(s): Tomohiro TANIGUCHI of Nomi Ishikawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/739, C23C18/54, H01L23/00, H01L29/66
CPC Code(s): H10D12/481
Abstract: a semiconductor device according to an embodiment includes a semiconductor substrate; a first electrode provided on the semiconductor substrate, and the first electrode containing aluminum; a second electrode provided on the semiconductor substrate, the second electrode being provided separately from the first electrode, and the second electrode containing aluminum; a third electrode provided on the first electrode, and the third electrode containing aluminum oxide.
Inventor(s): Yuichiro SASAKI of Nonoichi Ishikawa JP for kabushiki kaisha toshiba, Takeshi SHIBATA of Nonoichi Ishikawa JP for kabushiki kaisha toshiba, Daiki YOSHIKAWA of Kanazawa Ishikawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/739, H01L23/64, H01L29/04, H01L29/06, H01L29/66
CPC Code(s): H10D12/481
Abstract: according to one embodiment, a semiconductor device includes a first electrode, a second electrode separated from the first electrode, and a semiconductor part located between the first electrode and the second electrode. the semiconductor part includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to a first direction that is from the first electrode toward the second electrode. the third region includes a tenth semiconductor region of the first conductivity type located on the first electrode, and a current blocking region located between the sixth semiconductor region and the ninth semiconductor region in the second direction and located on the tenth semiconductor region.
Inventor(s): Masaharu SHIMABAYASHI of Ibo Hyogo JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/66, H01L21/28
CPC Code(s): H10D30/0291
Abstract: in a method for manufacturing a semiconductor device according to one embodiment, an opening is formed in an upper surface of a first semiconductor region of a first conductivity type. in the method, a gap is formed at a lower portion of the opening by performing atomic layer deposition to plug the opening by forming a first insulating layer at an upper portion of the opening. in the atomic layer deposition, adsorption of an inhibitor to an inner surface of the lower portion of the opening, or termination of dangling bonds of a semiconductor material present at the inner surface of the lower portion of the opening, and adsorption of a precursor to an inner surface of the upper portion of the opening are repeatedly performed.
20250107141. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Takuya YASUTAKE of Kanazawa Ishikawa JP for kabushiki kaisha toshiba, Tsuyoshi KACHI of Kanazawa Ishikawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/78, H01L29/06, H01L29/40, H01L29/423, H01L29/66
CPC Code(s): H10D30/668
Abstract: a semiconductor device includes first to fourth electrodes, first to third semiconductor regions, first and second insulating parts, and a connection part. the third electrode includes first to third electrode regions. the third electrode region connects the first electrode region and the second electrode region. the first insulating part includes first to third insulating regions. the first insulating region includes first and second insulating portions. the second insulating region includes third and fourth insulating portions. the third insulating region connects the first insulating region and the second insulating region. the third insulating region includes fifth and sixth insulating portions. the connection part includes first and second connection parts. the first connection part is positioned between the third insulating region and the second insulating part. the second connection part is positioned between the third insulating region and the first connection part.
20250107142. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Takuya YASUTAKE of Kanazawa Ishikawa JP for kabushiki kaisha toshiba, Hiroaki KATOU of Nonoichi Ishikawa JP for kabushiki kaisha toshiba, Tatsuya NISHIWAKI of Yokohama Kanagawa JP for kabushiki kaisha toshiba, Kenya KOBAYASHI of Nonoichi Ishikawa JP for kabushiki kaisha toshiba, Tsuyoshi KACHI of Kanazawa Ishikawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/78, H01L29/06, H01L29/40, H01L29/423, H01L29/66
CPC Code(s): H10D30/668
Abstract: a semiconductor device includes first to fourth electrodes, first to third semiconductor regions, and first and second insulating parts. the third electrode includes first to third electrode regions. the third electrode region connects the first electrode region and the second electrode region. the first insulating part includes first to third insulating regions. the first insulating region includes first and second insulating portions. the second insulating region includes third and fourth insulating portions. the third insulating region connects the first insulating region and the second insulating region. the third insulating region includes fifth and sixth insulating portions. a lower end of the sixth insulating portion is positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion.
20250107163. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Kazuyuki SATO of Nonoichi Ishikawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/06, H01L23/522, H01L23/528, H01L29/423, H01L29/78
CPC Code(s): H10D62/102
Abstract: a semiconductor device includes a first electrode, a semiconductor part located on the first electrode, an insulating member located in the semiconductor part, a first insulating film located on a portion of the semiconductor part, a second insulating film located on another portion of the semiconductor part, a second electrode located in the insulating member, a first wiring part connected to the second electrode, and a third electrode located on the semiconductor part, on the insulating member, and on the first insulating film. the second insulating film is thicker than the first insulating film. the first wiring part is located on the insulating member and on the second insulating film but not on the first insulating film.
Inventor(s): Ko HYODO of Nonoichi Ishikawa JP for kabushiki kaisha toshiba, Daiki YOSHIKAWA of Kanazawa Ishikawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/06, H01L29/66, H01L29/739
CPC Code(s): H10D62/103
Abstract: a manufacturing method of a semiconductor device according to an embodiment includes: forming a semiconductor portion including a transistor region and a diode region; forming a first lifetime control region in a lower portion of the semiconductor portion in the diode region, with ion irradiated from an upper side of the semiconductor portion; and forming a second lifetime control region in an upper portion of the semiconductor portion, with ion irradiated through a mask from the upper side of the semiconductor portion, the second lifetime control region being formed simultaneously with the first lifetime control region so as not to overlap with the first lifetime control region.
20250107182. SEMICONDUCTOR DEVICE_simplified_abstract_(kabushiki kaisha toshiba)
Inventor(s): Takuya YASUTAKE of Kanazawa I JP for kabushiki kaisha toshiba, Kenya KOBAYASHI of Nonoichi JP for kabushiki kaisha toshiba, Hiroaki KATOU of Nonoichi JP for kabushiki kaisha toshiba, Tsuyoshi KACHI of Kanazawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/06, H01L29/41
CPC Code(s): H10D62/126
Abstract: a semiconductor device includes first to fourth electrodes, first to fourth semiconductor regions, and first and second insulating parts. the third electrode includes first to third electrode regions. the first insulating part includes first to third insulating regions. the first insulating region includes first and second insulating portions. the second insulating region includes third and fourth insulating portions. the third insulating region includes fifth and sixth insulating portion. the fourth electrode is arranged with the first semiconductor region and the third electrode. the second insulating part is located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode. the fourth semiconductor region is located under the sixth insulating portion.
Inventor(s): Kanako KOMATSU of Yokohama Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/49, H01L21/285, H01L21/762
CPC Code(s): H10D64/668
Abstract: a semiconductor device includes a semiconductor substrate, an insulating film located on the semiconductor substrate, a silicon film located on the insulating film, a silicide layer located on the silicon film, and a first contact and a second contact connected to portions of the silicide layer. a first recess is formed in an upper surface of the insulating film. the silicon film includes an impurity. a second recess is formed in an upper surface of the silicon film in a region directly above the first recess. the silicide layer contacts the silicon film. a region directly above the second recess is interposed between the portions.
Inventor(s): Kanako KOMATSU of Yokohama Kanagawa JP for kabushiki kaisha toshiba
IPC Code(s): H01L29/78, H01L29/06, H01L29/45, H01L29/49
CPC Code(s): H10D84/151
Abstract: according to one embodiment, a semiconductor device includes a substrate having a first surface and an insulator that surrounds a first region of the first surface. a gate electrode is on the first region and has a first resistivity. a first conductor is also on the first region. the first conductor comprises a same material as the gate electrode, but has a second resistivity that is different from the first resistivity. the resistivity may be different, for example, by either use of different dopants/impurities or different concentrations of dopants/impurities. resistivity may also be different due to inclusion of a metal silicide on the conductors or not.
KABUSHIKI KAISHA TOSHIBA patent applications on March 27th, 2025
- KABUSHIKI KAISHA TOSHIBA
- B23K3/08
- B23K3/04
- B23K103/18
- CPC B23K3/08
- Kabushiki kaisha toshiba
- B65G47/91
- CPC B65G47/917
- G01N29/02
- G01N29/24
- G01N33/00
- G11B33/06
- CPC G01N29/022
- G05D1/683
- A01M29/16
- F41H13/00
- G05D105/50
- G05D109/20
- G05D111/30
- CPC G05D1/683
- G05D1/698
- CPC G05D1/698
- G05F3/26
- G01R19/00
- H03F3/45
- CPC G05F3/262
- G06N3/098
- CPC G06N3/098
- G06T7/00
- B25J9/16
- G06T7/70
- G06V20/52
- CPC G06T7/0004
- G11B5/48
- G11B5/53
- G11B5/82
- CPC G11B5/4833
- G11B5/60
- G11B5/00
- G11B5/012
- G11B5/02
- G11B5/455
- CPC G11B5/607
- G11B33/04
- G11B5/54
- G11B19/20
- CPC G11B33/045
- G11B33/14
- CPC G11B33/146
- H01L21/306
- CPC H01L21/30604
- H01L23/04
- H01L23/00
- H01L23/498
- CPC H01L23/04
- H01L23/15
- CPC H01L23/15
- H01L23/31
- H01L21/782
- H01L23/29
- H01L29/739
- H01L29/78
- CPC H01L23/3135
- CPC H01L23/49838
- H01L25/065
- C25D5/02
- C25D7/12
- H01L21/768
- H01L23/522
- H01L23/528
- CPC H01L24/05
- H03K3/03
- H03K17/687
- CPC H03K3/0315
- H03K19/017
- H03K17/16
- H03K17/30
- H03K19/00
- CPC H03K19/01742
- H01L27/06
- H01L29/06
- H01L29/423
- H01L29/861
- CPC H10D12/481
- C23C18/54
- H01L29/66
- H01L23/64
- H01L29/04
- H01L21/28
- CPC H10D30/0291
- H01L29/40
- CPC H10D30/668
- CPC H10D62/102
- CPC H10D62/103
- H01L29/41
- CPC H10D62/126
- H01L29/49
- H01L21/285
- H01L21/762
- CPC H10D64/668
- H01L29/45
- CPC H10D84/151