Intel corporation (20250113529). INTEGRATED CIRCUIT STRUCTURES HAVING FIN CUTS
INTEGRATED CIRCUIT STRUCTURES HAVING FIN CUTS
Organization Name
Inventor(s)
Leonard P. Guler of Hillsboro OR US
Jessica Panella of Banks OR US
Manjunath Chinnappamudaliar Rajagopal of Hillsboro OR US
Sharanya Subramaniam of Beaverton OR US
Robert Joachim of Beaverton OR US
Dario Farias of Portland OR US
INTEGRATED CIRCUIT STRUCTURES HAVING FIN CUTS
This abstract first appeared for US patent application 20250113529 titled 'INTEGRATED CIRCUIT STRUCTURES HAVING FIN CUTS
Original Abstract Submitted
integrated circuit structures having fin cuts, and methods of fabricating integrated circuit structures having fin cuts, are described. for example, an integrated circuit structure includes a first fin structure or nanowire stack and sub-fin pairing separated from a second fin structure or nanowire stack and sub-fin pairing by a cut, wherein an end of the first fin structure or nanowire stack and sub-fin pairing is facing toward an end of the second fin structure or nanowire stack and sub-fin pairing. a first gate structure is overlying the first fin structure or nanowire stack and sub-fin pairing, and a second gate structure is overlying the second fin structure or nanowire stack and sub-fin pairing. a first isolation structure is overlying the end of the first fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the first gate structure, and a second isolation structure is overlying the end of the second fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the second gate structure.
- Intel corporation
- Leonard P. Guler of Hillsboro OR US
- Jessica Panella of Banks OR US
- Manjunath Chinnappamudaliar Rajagopal of Hillsboro OR US
- Sharanya Subramaniam of Beaverton OR US
- Robert Joachim of Beaverton OR US
- Dario Farias of Portland OR US
- H01L29/78
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/786
- CPC H10D30/6211