Intel corporation (20250098230). INTEGRATED CIRCUIT STRUCTURES HAVING DUAL STRESS GATES
INTEGRATED CIRCUIT STRUCTURES HAVING DUAL STRESS GATES
Organization Name
Inventor(s)
Dan S. Lavric of Beaverton OR US
Sean Pursel of Hillsboro OR US
Dimitri Kioussis of San Jose CA US
Lukas Baumgartel of Portland OR US
Mahdi Ahmadi of Portland OR US
Cortnie S. Vogelsberg of Beaverton OR US
Mengcheng Lu of Portland OR US
Omar Kyle Hite of Beaverton OR US
Justin E. Mueller of Portland OR US
INTEGRATED CIRCUIT STRUCTURES HAVING DUAL STRESS GATES
This abstract first appeared for US patent application 20250098230 titled 'INTEGRATED CIRCUIT STRUCTURES HAVING DUAL STRESS GATES
Original Abstract Submitted
integrated circuit structures having dual stress gates are described. for example, an integrated circuit structure includes a first vertical stack of horizontal nanowires, and a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires. an nmos gate electrode is over the first vertical stack of horizontal nanowires, the nmos gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires. a pmos gate electrode is over the second vertical stack of horizontal nanowires, the pmos gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires. the tensile layer of the nmos gate electrode is not included in the pmos gate electrode.
- Intel corporation
- Dan S. Lavric of Beaverton OR US
- Sean Pursel of Hillsboro OR US
- Dimitri Kioussis of San Jose CA US
- Lukas Baumgartel of Portland OR US
- Mahdi Ahmadi of Portland OR US
- Cortnie S. Vogelsberg of Beaverton OR US
- Mengcheng Lu of Portland OR US
- Omar Kyle Hite of Beaverton OR US
- Justin E. Mueller of Portland OR US
- Lily Mao of Portland OR US
- H01L29/78
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H10D30/794