Intel corporation (20250006591). STANDARD-CELL CIRCUITS TO MITIGATE SCALING-RELATED PARASITICS
STANDARD-CELL CIRCUITS TO MITIGATE SCALING-RELATED PARASITICS
Organization Name
Inventor(s)
Nischal Arkali Radhakrishna of Hillsboro OR US
Chinhsuan Chen of Portland OR US
Sivakumar Venkataraman of Hillsboro OR US
Somashekar Bangalore Prakash of Portland OR US
Marni Nabors of Portland OR US
STANDARD-CELL CIRCUITS TO MITIGATE SCALING-RELATED PARASITICS
This abstract first appeared for US patent application 20250006591 titled 'STANDARD-CELL CIRCUITS TO MITIGATE SCALING-RELATED PARASITICS
Original Abstract Submitted
an integrated circuit (ic) device may include standard cells with multiple parallel paths interconnecting transistors at a device level and over a transistor, in a higher layer of an interconnect structure. the parallel paths may include multiple power supply via contacts on a transistor source structure and multiple supply interconnect lines over the transistor and coupling the transistor to an associated power supply. the parallel paths may include multiple output via contacts on an integrated transistor drain structure and multiple output interconnect lines over a complementary transistor device. the parallel paths may include separate, rather than shared or integrated, adjacent source structures coupled to a same power supply.
- Intel corporation
- Nischal Arkali Radhakrishna of Hillsboro OR US
- Chinhsuan Chen of Portland OR US
- Sivakumar Venkataraman of Hillsboro OR US
- Somashekar Bangalore Prakash of Portland OR US
- Marni Nabors of Portland OR US
- H01L23/48
- H01L23/522
- H01L23/528
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- CPC H01L23/481