Intel corporation (20240404917). SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS

SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS

Organization Name

intel corporation

Inventor(s)

Sikandar Abbas of Forest Grove OR (US)

Chanaka Munasinghe of Portland OR (US)

Leonard Guler of Hillsboro OR (US)

Reza Bayati of Portland OR (US)

Madeleine Stolt of Beaverton OR (US)

Makram Abd El Qader of Hillsboro OR (US)

Pratik Patel of Portland OR (US)

Anindya Dasgupta of Portland OR (US)

SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS

This abstract first appeared for US patent application 20240404917 titled 'SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS

Original Abstract Submitted

devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. a device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.