Intel Corporation patent applications on May 8th, 2025
Patent Applications by Intel Corporation on May 8th, 2025
Intel Corporation: 33 patent applications
Intel Corporation has applied for patents in the areas of H01L23/538 (5), H01L25/065 (4), H01L23/00 (4), H01L23/498 (4), H01L29/06 (3) H10D62/121 (2), B29C45/14655 (1), H04L1/1812 (1), H10D64/254 (1), H10D64/01 (1)
With keywords such as: structure, layer, data, source, drain, epitaxial, surface, fin, having, and embodiments in patent application abstracts.
Patent Applications by Intel Corporation
20250144857. MOLDING SYSTEM AND MOLDING METHOD_simplified_abstract_(intel corporation)
Inventor(s): Zhixin XIE of Chandler AZ US for intel corporation, Yi LI of Chandler AZ US for intel corporation, Jesse JONES of Chandler AZ US for intel corporation, Gang DUAN of Chandler AZ US for intel corporation, Andrew JIMENEZ of Mesa AZ US for intel corporation, Jung Kyu HAN of Chandler AZ US for intel corporation, Yekan WANG of Chandler AZ US for intel corporation
IPC Code(s): B29C45/14, B29C45/26
CPC Code(s): B29C45/14655
Abstract: various aspects may provide a molding system. the molding system may include a molding unit which includes a first mold panel and a second mold panel. the first mold panel and the second mold panel may include a mold cavity which surrounds a semiconductor workpiece along a side surface of the semiconductor workpiece, with the first mold panel and the second mold panel engaged with the semiconductor workpiece. various aspects may also provide a molding method which utilize the molding system.
Inventor(s): Junyi Qiu of Portland OR US for intel corporation, Mozhgan Mansuri of Portland OR US for intel corporation, Beom-Taek Lee of Beaverton OR US for intel corporation
IPC Code(s): G02B6/12, H04J14/02
CPC Code(s): G02B6/12011
Abstract: a wavelength multiplexing optical fiber transmitter, receiver, or transceiver where multiple emitters and/or photodetectors of different center wavelengths are coupled to a single optical fiber core terminus through multiple waveguides, which may be directly printed in free space. the optical assemblies described are suitable for optical data link applications, for example, to reduce a number of optical fibers needed for a given bandwidth or increase the bandwidth of a give number of optical fibers. bidirectional fiber termination may also be implemented with an emitter and a photodetector pair coupled to a single optical fiber core terminus through multiple waveguides.
Inventor(s): Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Gang Chen of Milpitas CA US for intel corporation, Supratim Pal of Folsom CA US for intel corporation, Jorge Eduardo Parra Osorio of El Dorado Hills CA US for intel corporation, Arthur Hunter of Cameron Park CA US for intel corporation, Boris Kuznetsov of Gdansk PL for intel corporation, Deepak N K of Palakkad IN for intel corporation, Siva Kumar Seemakurthi of Folsom CA US for intel corporation, James Valerio of Scottsdale AZ US for intel corporation, Shubham Dinesh Chavan of Bengaluru IN for intel corporation, Abhishek Kumar Singh of Bengaluru IN for intel corporation, Samir Pandya of Folsom CA US for intel corporation, Sandeep Tippannanavar Niranjan of Bangalore IN for intel corporation, Alan Curtis of El Dorado Hills CA US for intel corporation, Jain Philip of Bangalore IN for intel corporation, Maltesh Kulkarni of Cambridge GB for intel corporation, Fangwen Fu of Folsom CA US for intel corporation, John Wiegert of Aloha OR US for intel corporation, Brent Schwartz of Sacramento CA US for intel corporation
IPC Code(s): G06F9/30, G06T15/00
CPC Code(s): G06F9/30134
Abstract: described herein is a graphics processor having processing resources with configurable thread and register configurations. program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.
20250147822. MICROSERVICES ARCHITECTURE_simplified_abstract_(intel corporation)
Inventor(s): Vadim Sukhomlinov of Santa Clara CA US for intel corporation, Kshitij A. Doshi of Tempe AZ US for intel corporation
IPC Code(s): G06F9/54, G06F9/50
CPC Code(s): G06F9/541
Abstract: a computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
20250147886. I/O CACHE PARTITIONING_simplified_abstract_(intel corporation)
Inventor(s): Zhan Xue of Shanghai CN for intel corporation, Muhammad Ahmed of Hayward CA US for intel corporation, Bo Cui of Shanghai CN for intel corporation, Jie Wang of Shanghai CN for intel corporation, Tao Yu of Shanghai CN for intel corporation
IPC Code(s): G06F12/0811, G06F12/0831, G06F12/0846
CPC Code(s): G06F12/0811
Abstract: a computing device includes last level cache (llc) for processing cores and a separate input/output (i/o) llc for use in facilitating data transfers between the computing device and one or more i/o devices. the i/o llc is configured to include a set of partitions corresponding to a set of classes. usage of the partitions in the set of partitions is monitored and the set of partitions is dynamically adjusted based on the usage. a process in a particular one of the classes makes a data request and a particular one of the partitions associated with the particular class is used in the data request.
Inventor(s): David M. Durham of Beaverton OR US for intel corporation, Michael LeMay of Hillsboro OR US for intel corporation, Hans Goran Liljestrand of Helsinki FI for intel corporation
IPC Code(s): G06F21/60
CPC Code(s): G06F21/602
Abstract: techniques for instruction prefix encoding for cryptographic computing capability data types are described. in an embodiment, an apparatus includes an instruction decoder to decode a first instruction including a first prefix; and cryptography circuitry to perform a cryptographic operation on data, the cryptographic operation to be based at least in part on the first prefix and a relative enumeration in a pointer to the data.
Inventor(s): Dongqi CAI of Beijing CN for intel corporation, Anbang YAO of Beijing CN for intel corporation, Chao LI of Beijing CN for intel corporation, Shandong WANG of Beijing CN for intel corporation, Yurong CHEN of Beijing CN for intel corporation
IPC Code(s): G06V10/771, G06T5/20, G06V10/40, G06V20/64
CPC Code(s): G06V10/771
Abstract: the disclosure provides an apparatus, method, device and medium for 3d dynamic sparse convolution. the method includes: receiving an input feature map of a 3d data sample; performing input feature map partition to divide the input feature map into a plurality of disjoint input feature map groups; performing a shared 3d dynamic sparse convolution to the plurality of disjoint input feature map groups respectively to obtain a plurality of output feature maps corresponding to the plurality of disjoint input feature map groups, wherein the shared 3d dynamic sparse convolution comprises a shared 3d dynamic sparse convolutional kernel; and performing output feature map grouping to sequentially stack the plurality of output feature maps to obtain an output feature map corresponding to the input feature map. (fig. ).
20250149145. PHYSICAL THERAPY ASSISTANT AS A SERVICE_simplified_abstract_(intel corporation)
Inventor(s): Sharon Talmor Marcovici of Kfar-Saba IL for intel corporation, Rajasekaran Andiappan of Raseborg FI for intel corporation, Dan Horovitz of Rishon Letzion IL for intel corporation, Amit Gur of Ein Vered IL for intel corporation, Lakshman Krishnamurthy of Portland OR US for intel corporation
IPC Code(s): G16H20/30
CPC Code(s): G16H20/30
Abstract: physical therapy assistant-as-a-service (ptaas) enables the automatic evaluation of a patient's performance of physical therapy exercises and the automatic provision of feedback to the patient on their exercise performance in real-time. a patient device can provide real-time patient exercise video to a ptaas backend that performs checks prior to the patient performing the exercise (pre-checks) and checks during patient performance of the exercise (live checks). if any of the checks fail, the ptaas can provide feedback to the patient, such as if the patient is in an incorrect starting pose or has a body part at an incorrect angle before beginning the exercise or if the patient's form or posture during performance of the exercise needs to be adjusted. the ptaas can automatically generate exercise metrics, reports, and physical therapy insights that a physical therapy clinician can access from a clinician portal.
Inventor(s): Ziyin LIN of Chandler AZ US for intel corporation, Karumbu MEYYAPPAN of Portland OR US for intel corporation, Gregorio R. MURTAGIAN of Phoenix AZ US for intel corporation, Dingying David XU of Chandler AZ US for intel corporation
IPC Code(s): H01L23/498, H01L23/00
CPC Code(s): H01L23/49811
Abstract: embodiments disclosed herein include an interconnect structure. in an embodiment, the interconnect structure is an apparatus that comprises a substrate with a well through a thickness of the substrate. in an embodiment, the substrate comprises a polymer foam. in an embodiment, a liquid metal is in the opening, and the liquid metal comprises voids.
Inventor(s): Jeremy Ecton of Gilbert AZ US for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L25/065
CPC Code(s): H01L23/49822
Abstract: disclosed herein are microelectronic assemblies and related devices and methods. in some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a positive-type photo-imageable dielectric (pid) material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.
Inventor(s): Hongxia FENG of Chandler AZ US for intel corporation, Dingying David XU of Chandler AZ US for intel corporation, Sheng C. LI of Gilbert AZ US for intel corporation, Matthew L. TINGEY of Hillsboro OR US for intel corporation, Meizi JIAO of San Jose CA US for intel corporation, Chung Kwang Christopher TAN of Chandler AZ US for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/13, H01L23/538
CPC Code(s): H01L23/49838
Abstract: a package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. a method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
Inventor(s): Nicholas Haehn of Scottsdale AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/15, H01L23/31, H01L23/48, H01L25/065
CPC Code(s): H01L23/5383
Abstract: disclosed herein are microelectronic assemblies and related devices and methods. in some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a polyimide or a dielectric material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.
Inventor(s): Burak Baylav of Hillsboro OR US for intel corporation, Dhananjay Bhawe of Hillsboro OR US for intel corporation
IPC Code(s): H01L23/538, G06F30/392, H01L23/522
CPC Code(s): H01L23/5386
Abstract: an integrated circuit structure includes a plurality of interconnect lines and a plurality of dummy lines that are co-planar with the plurality of interconnect lines, where a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions. the regions are of approximately equal area within a rectangular grid array.
20250149462. EMBEDDED DIE ON INTERPOSER PACKAGES_simplified_abstract_(intel corporation)
Inventor(s): John S. GUZEK of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L21/56, H01L23/13, H01L23/31, H01L23/48, H01L23/498, H01L25/065, H01L25/07
CPC Code(s): H01L23/5389
Abstract: integrated circuit (ic) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. for example, in some embodiments, an ic package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. in some embodiments, a die may be disposed on the back side of an ic package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. in some embodiments, a second ic package in a package-on-package (pop) arrangement may be disposed on the back side of an ic package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.
Inventor(s): Rahul JAIN of Gilbert AZ US for intel corporation, Ji Yong PARK of Chandler AZ US for intel corporation, Kyu Oh LEE of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L24/81
Abstract: examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. the die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. the die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. the die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. a surface of the first interface structure and a surface of the second interface structure are at the same height.
20250150103. COMMUNICATION DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Abhishek AGRAWAL of Portland OR US for intel corporation, Ritesh A. BHAT of Portland OR US for intel corporation, Steven CALLENDER of Denver CO US for intel corporation, Brent R. CARLTON of Portland OR US for intel corporation, Christopher D. HULL of Portland OR US for intel corporation, Stefano PELLERANO of Beaverton OR US for intel corporation, Mustafijur RAHMAN of Hillsboro OR US for intel corporation, Peter SAGAZIO of Portland OR US for intel corporation, Woorim SHIN of Portland OR US for intel corporation
IPC Code(s): H04B1/04
CPC Code(s): H04B1/0458
Abstract: various aspects provide a transceiver and a communication device including the transceiver. in an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.
Inventor(s): Walid EL HAJJ of Antibes FR for intel corporation, Mythili HEGDE of Bangalore IN for intel corporation, Nawfal ASRIH of Mandelieu-la-Napoule FR for intel corporation, Manuel BLAZQUEZ DE PINEDA of Antibes FR for intel corporation, John Michael ROMAN of Hillsboro OR US for intel corporation
IPC Code(s): H04B1/3827, H04W52/36
CPC Code(s): H04B1/3838
Abstract: methods and device to implement the use of proximity sensor data and time-averaging specific absorption rate methods in determining whether to apply or remove a power back-off to a radio frequency transmitter. the methods and devices may be configured to detect whether a body is proximately located based on obtained proximity sensor data; define an upper threshold for a radio frequency (rf) transmit power and a lower threshold for the rf transmit power; calculate an average power of an rf transmitter over a fixed time period; and based on whether the body is detected, the average power, and a comparison of the average power to the upper threshold or the lower threshold, determine whether to apply or remove a power back-off to the rf transmitter.
Inventor(s): Salvatore Talarico of Santa Clara CA US for intel corporation, Kilian Roth of Munich DE for intel corporation, Alexey Khoryaev of Santa Clara CA US for intel corporation, Sergey Panteleev of Kildare IE for intel corporation, Mikhail Shilov of Santa Clara CA US for intel corporation
IPC Code(s): H04L1/1812, H04L1/1867, H04W72/0446, H04W72/25, H04W72/30, H04W92/18
CPC Code(s): H04L1/1812
Abstract: various embodiments herein provide techniques related to hybrid automatic repeat request (harq) feedback of a new radio (nr) sidelink (sl) transmission. specifically, in embodiments, a user equipment (ue) may perform, in a first slot of a plurality of slots, a listen before talk (lbt) procedure related to a nr sl transmission. the ue may further identify a subset of two or more candidate slots of the plurality of slots for transmission of a harq message related to the lbt procedure. the ue may further transmit the harq message in a candidate slot of the two or more candidate slots. other embodiments may be described and/or claimed.
20250150296. CONFERENCE CALL SYSTEM WITH FEEDBACK_simplified_abstract_(intel corporation)
Inventor(s): Venkat Raghavulu of Bangalore IN for intel corporation, Ke Han of Shanghai CN for intel corporation, Sean Jude William Lawrence of Bangalore IN for intel corporation
IPC Code(s): H04L12/18, G06F3/16
CPC Code(s): H04L12/1895
Abstract: particular embodiments described herein provide for an electronic device that is configured to receive audio data related to a conference call from a network conference engine, sample the audio data at a frame rate, determine an amount of missing samples of audio data for a predetermined amount of time, and communicate, to the network conference engine, a notification when the amount of missing samples of audio data for the predetermined amount of time is greater than a lost sample threshold. the electronic device can also be configured to receive visual content and visual content verification data from the network conference engine and use the visual content verification data to determine if visual content to be rendered on a display of the electronic device is the same or similar to the received visual content from the network conference engine.
Inventor(s): Yingyang Li of Beijing CN for intel corporation, Yi Wang of Beijing CN for intel corporation, Gang Xiong of Beaverton OR US for intel corporation, Debdeep Chatterjee of San Jose CA US for intel corporation, Toufiqul Islam of Santa Clara CA US for intel corporation
IPC Code(s): H04L27/26, H04L5/00, H04W74/0833
CPC Code(s): H04L27/26025
Abstract: a computer-readable storage medium stores instructions to configure one or more processors of a further reduced capacity (f-redcap) ue for operation in a 5g nr network, and to cause the f-redcap ue to perform operations including decoding a pbch to obtain a numerology parameter. a maximum resource block (rb) allocation is determined for a bandwidth associated with the numerology parameter. the maximum rb allocation is adjusted based on a reduced bandwidth associated with the f-redcap ue to obtain an adjusted rb allocation. a maximum data rate is determined based on the numerology parameter and the adjusted rb allocation. data is encoded for an uplink (ue) transmission to a base station. the ue transmission uses the maximum data rate.
Inventor(s): Francesc Guim Bernat of Barcelona ES for intel corporation, Ned Smith of Beaverton OR US for intel corporation, Kshitij Doshi of Tempe AZ US for intel corporation, Alexander Bachmutsky of Sunnyvale CA US for intel corporation, Suraj Prabhakaran of Aachen DE for intel corporation
IPC Code(s): H04L41/5006, H04L41/12, H04L41/5019, H04L67/1004, H04L67/1021, H04L67/1023
CPC Code(s): H04L41/5006
Abstract: network apparatus, communicatively coupled to a provider of services, that includes gateway circuitry to receive application programming interface (api) request data from a computing device that indicates a requested service. the gateway circuitry is to (1) select, based upon the api request data, at least one of the services corresponding to the requested service, and (2) generate, based upon mapping of the api request data to the at least one of the services, corresponding request data specifically for use in invoking the at least one of the services. the gateway circuitry is to (1) generate the corresponding request data by performing at least one programmable transformation, (2) be used in association with at least one proxy-related operation, (3) register the services for use in association with service discovery, and (4) verify the api request data and an identity associated with the computing device.
Inventor(s): Rameshkumar Illikkal of Folsom CA US for intel corporation, Anna Drewek-Ossowicka of Gdansk PL for intel corporation, Dharmisha Ketankumar Doshi of Folsom CA US for intel corporation, Qian Li of Stanford CA US for intel corporation, Andrzej Kuriata of Gdansk PL for intel corporation, Andrew J. Herdrich of Hillsboro OR US for intel corporation, Teck Joo Goh of Saratoga CA US for intel corporation, Daniel Richins of Orem UT US for intel corporation, Slawomir Putyrski of Gdynia PL for intel corporation, Wenhui Shu of Shanghai CN for intel corporation, Long Cui of Shanghai CN for intel corporation, Jinshi Chen of Shanghai City CN for intel corporation, Mihai Daniel Dodan of Bucharest RO for intel corporation
IPC Code(s): H04L41/5019, G06F9/50
CPC Code(s): H04L41/5019
Abstract: various approaches to efficiently allocating and utilizing hardware resources in data centers while maintaining compliance with a service level agreement are described. in various embodiments, an application-level service level objective (slo) specified for a computational workload is translated into a hardware-level slo to facilitate direct enforcement by the hardware processor, e.g., using a feedback control loop or model-based mapping of the hardware-level slo to allocations of microarchitecture resources of the processor. in some embodiments, a computational model of the hardware behavior under resource contention is used to predict the application performance (e.g., as measured in terms of the hardware-level slo) to be expected under certain contention scenarios. scheduling of workloads among the compute nodes within the data center may be based on such predictions. in further embodiments, configurations of microservices are optimized to minimize hardware resources while meeting a specified performance goal.
Inventor(s): Eyal Ruhm of Tel Aviv IL for intel corporation, Jill Boyce of Portland OR US for intel corporation, Asaf J. Shenberg of Tel Aviv IL for intel corporation
IPC Code(s): H04N13/161
CPC Code(s): H04N13/161
Abstract: embodiments are generally directed to selective packing of patches for immersive video. an embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. the system is to select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. the system is to encode the patches into one or more coded pictures according to the selection of the patches.
Inventor(s): Laurent CARIOU of Milizac FR for intel corporation, Thomas J. KENNEY of Portland OR US for intel corporation
IPC Code(s): H04W52/02
CPC Code(s): H04W52/0216
Abstract: this disclosure describes systems, methods, and devices related to control frames status. a device may receive a control frame from a station (sta) at a beginning of a transmission opportunity (txop) that includes availability and unavailability information. the device may acknowledge the availability and unavailability information of the sta based on fields within the control frame, including unavailability target start time field and unavailability duration field. the device may adjust a transmission schedule to avoid transmitting to the sta during its indicated unavailability period. the device may initiate a txop with an initial control frame that includes updated availability and unavailability information based on the control frame from the sta.
Inventor(s): Yonathan Segev of Sunnyvale CA US for intel corporation, Qinghua Li of San Ramon CA US for intel corporation, Xiaogang Chen of Portland OR US for intel corporation, Ofer Hareuveni of Haifa IL for intel corporation, David Birnbaum of Modiin IL for intel corporation
IPC Code(s): H04W72/02, H04L5/00, H04L25/02, H04W72/0446
CPC Code(s): H04W72/02
Abstract: a station (sta) may operate as a first peer-to-peer (p2p) client (p2p1) for p2p operations with dual-stage triggering. the sta may decode a primary frame trigger frame (tf) from an access point (ap) operating as a coordinator. the primary tf may allocate resources in an initial portion of a time-duration allocation to the p2p1 for the p2p operations with one or more other peer stations, including a second p2p client (p2p2) and a third p2p client (p2p3). the primary tf may further allocate resources in a subsequent portion of the time-duration allocation to the p2p2 for the p2p operations. the sta may also encode a first secondary tf for transmission within the initial portion of the time-duration allocation. the first secondary tf may allocate specific resource units (rus) to the one or more other peer stations. the sta may also decode a tb physical layer protocol data unit (tb ppdu) encoded in accordance with a multi-user orthogonal frequency division multiple access (mu ofdma) frame format. the tb ppdu may be received concurrently within the initial portion of the time-duration allocation from the one or more other peer stations in accordance with an uplink ofdma technique.
Inventor(s): Salvatore Talarico of Santa Clara CA US for intel corporation, Kilian Roth of Munich DE for intel corporation, Alexey Khoryaev of Santa Clara CA US for intel corporation, Sergey Panteleev of Kildare IE for intel corporation, Mikhail Shilov of Santa Clara CA US for intel corporation
IPC Code(s): H04W72/25, H04L5/00, H04W72/0453
CPC Code(s): H04W72/25
Abstract: various embodiments herein provide techniques for sidelink communication, e.g., in an unlicensed frequency band. for example, embodiments may relate to channel access sensing procedures, e.g., in association with a listen-before-talk (lbt) procedure for unlicensed spectrum. embodiments may further relate to a frequency interlaced physical structure for sidelink communication. other embodiments may be described and claimed.
Inventor(s): Ritesh K. DAS of Hillsboro OR US for intel corporation, Kiran CHIKKADI of Hillsboro OR US for intel corporation, Ryan PEARCE of Beaverton OR US for intel corporation
IPC Code(s): H10D30/62, H01L21/02, H10D30/69, H10D64/66
CPC Code(s): H10D30/6215
Abstract: self-aligned gate endcap (sage) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (sage) architectures with vertical sidewalls, are described. in an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. a gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. the gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.
Inventor(s): Biswajeet GUHA of Hillsboro OR US for intel corporation, Mauro J. KOBRINSKY of Portland OR US for intel corporation, Tahir GHANI of Portland OR US for intel corporation
IPC Code(s): H10D30/67, H10D62/10, H10D84/01, H10D84/03, H10D84/83
CPC Code(s): H10D30/6757
Abstract: gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. for example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. a gate stack is over the vertical arrangement of nanowires. a first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. a second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. a first conductive contact structure is coupled to the first epitaxial source or drain structure. a second conductive contact structure is coupled to the second epitaxial source or drain structure. the second conductive contact structure is deeper along the fin than the first conductive contact structure.
Inventor(s): Leonard P. GULER of Hillsboro OR US for intel corporation, Charles H. WALLACE of Portland OR US for intel corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: integrated circuit structures having varied epitaxial source or drain structures are described. in an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. a first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width. a second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a lateral width greater than the lateral width of the first epitaxial source or drain structure.
Inventor(s): Leonard P. GULER of Hillsboro OR US for intel corporation, Charles H. WALLACE of Portland OR US for intel corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: integrated circuit structures having varied internal spacers and epitaxial source or drain structures are described. in an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. a first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure between first internal spacers having a maximum lateral width. a second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure between second internal spacers having a maximum lateral width greater than the maximum lateral width of the first internal spacers.
20250151355. QUANTUM DOT ARRAY DEVICES WITH SHARED GATES_simplified_abstract_(intel corporation)
Inventor(s): Hubert C. George of Portland OR US for intel corporation, Ravi Pillarisetty of Portland OR US for intel corporation, Jeanette M. Roberts of North Plains OR US for intel corporation, Nicole K. Thomas of Leuven BE for intel corporation, James S. Clarke of Portland OR US for intel corporation
IPC Code(s): H10D64/01, B82Y10/00, B82Y40/00, H01L23/532, H10D30/40, H10D48/00, H10D62/81, H10D64/27
CPC Code(s): H10D64/01
Abstract: disclosed herein are quantum dot devices, as well as related computing devices and methods. for example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.
Inventor(s): Rishabh MEHANDRU of Portland OR US for intel corporation, Pratik A. PATEL of Portland OR US for intel corporation, Ralph T. TROEGER of Portland OR US for intel corporation, Szuya S. LIAO of Portland OR US for intel corporation
IPC Code(s): H10D64/23, H01L21/02, H01L21/265, H01L21/306, H01L21/321, H10D30/01, H10D62/13, H10D64/01, H10D64/62, H10D64/66
CPC Code(s): H10D64/254
Abstract: solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. the composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. the composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. the composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. the trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.
Inventor(s): Leonard P. GULER of Hillsboro OR US for intel corporation, Charles H. WALLACE of Portland OR US for intel corporation
IPC Code(s): H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D84/83
Abstract: integrated circuit structures having varied etch-stop for epitaxial source or drain structures are described. in an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. a first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width, and the first epitaxial source or drain structure beneath a first etch-stop layer. a second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a lateral width greater than the lateral width of the first epitaxial source or drain structure, and the second epitaxial source or drain structure beneath a combination of the first etch stop layer and a second etch-stop layer.
- Intel Corporation
- B29C45/14
- B29C45/26
- CPC B29C45/14655
- Intel corporation
- G02B6/12
- H04J14/02
- CPC G02B6/12011
- G06F9/30
- G06T15/00
- CPC G06F9/30134
- G06F9/54
- G06F9/50
- CPC G06F9/541
- G06F12/0811
- G06F12/0831
- G06F12/0846
- CPC G06F12/0811
- G06F21/60
- CPC G06F21/602
- G06V10/771
- G06T5/20
- G06V10/40
- G06V20/64
- CPC G06V10/771
- G16H20/30
- CPC G16H20/30
- H01L23/498
- H01L23/00
- CPC H01L23/49811
- H01L25/065
- CPC H01L23/49822
- H01L21/48
- H01L23/13
- H01L23/538
- CPC H01L23/49838
- H01L23/15
- H01L23/31
- H01L23/48
- CPC H01L23/5383
- G06F30/392
- H01L23/522
- CPC H01L23/5386
- H01L21/56
- H01L25/07
- CPC H01L23/5389
- H01L25/00
- CPC H01L24/81
- H04B1/04
- CPC H04B1/0458
- H04B1/3827
- H04W52/36
- CPC H04B1/3838
- H04L1/1812
- H04L1/1867
- H04W72/0446
- H04W72/25
- H04W72/30
- H04W92/18
- CPC H04L1/1812
- H04L12/18
- G06F3/16
- CPC H04L12/1895
- H04L27/26
- H04L5/00
- H04W74/0833
- CPC H04L27/26025
- H04L41/5006
- H04L41/12
- H04L41/5019
- H04L67/1004
- H04L67/1021
- H04L67/1023
- CPC H04L41/5006
- CPC H04L41/5019
- H04N13/161
- CPC H04N13/161
- H04W52/02
- CPC H04W52/0216
- H04W72/02
- H04L25/02
- CPC H04W72/02
- H04W72/0453
- CPC H04W72/25
- H10D30/62
- H01L21/02
- H10D30/69
- H10D64/66
- CPC H10D30/6215
- H10D30/67
- H10D62/10
- H10D84/01
- H10D84/03
- H10D84/83
- CPC H10D30/6757
- H01L29/06
- H01L21/8238
- H01L27/092
- H01L29/08
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H10D62/121
- H01L21/8234
- H01L27/088
- H10D64/01
- B82Y10/00
- B82Y40/00
- H01L23/532
- H10D30/40
- H10D48/00
- H10D62/81
- H10D64/27
- CPC H10D64/01
- H10D64/23
- H01L21/265
- H01L21/306
- H01L21/321
- H10D30/01
- H10D62/13
- H10D64/62
- CPC H10D64/254
- CPC H10D84/83
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