Intel Corporation patent applications on May 1st, 2025
Patent Applications by Intel Corporation on May 1st, 2025
Intel Corporation: 25 patent applications
Intel Corporation has applied for patents in the areas of H01L21/768 (2), H01L21/28 (2), H01L23/48 (2), H01L21/308 (2), H01L21/285 (2) B25J13/025 (1), H01R12/721 (1), H10D84/017 (1), H10D64/671 (1), H10D30/6212 (1)
With keywords such as: semiconductor, structure, portion, source, plate, third, device, layer, via, and metal in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): David Gonzalez Aguirre of Hillsboro OR US for intel corporation, Javier Felip Leon of Hillsboro OR US for intel corporation, Javier Felix Rendon of Zapopan MX for intel corporation, Roderico Garcia Leal of Zapopan MX for intel corporation, Julio Zamora Esquivel of West Sacramento CA US for intel corporation
IPC Code(s): B25J13/02, B25J9/16
CPC Code(s): B25J13/025
Abstract: a bidirectional haptic feedback system, including: a flexible membrane configured to be mounted on a handheld controller; sensor-actuator units arranged on the flexible membrane, the sensor-actuator units respectively including a damping mechanism configured to mechanically isolate vibrations between adjacent sensor-actuator units; a control system configured to: generate vibration signals within selected frequency bands within a proximity to a natural resonant frequency range of the sensor-actuator units to drive the actuators of the sensor-actuator units to deliver haptic feedback to a user based on a state of the robot; simultaneously detect user grasp contact and pressure through analysis of back electromotive force (emf) signals generated by the sensor-actuator units; and adjust robot control parameters dynamically in response to the detected grasp contact and pressure.
Inventor(s): David Gonzalez Aguirre of Hillsboro OR US for intel corporation, Sebastian Arevalo of Centennial CO US for intel corporation, Javier Felip Leon of Hillsboro OR US for intel corporation, Javier Felix Rendon of Zapopan MX for intel corporation, Roderico Garcia Leal of Zapopan MX for intel corporation, Vasana Maneeratana of Tempe AZ US for intel corporation, Michael Tan of Gilbert AZ US for intel corporation, Julio Zamora Esquivel of West Sacramento CA US for intel corporation
IPC Code(s): B25J15/10, B25J9/16, B25J13/08, B25J19/00
CPC Code(s): B25J15/10
Abstract: a component of a system, including: processor circuitry; and a non-transitory computer-readable storage medium including instructions that, when executed by the processing circuitry, cause the processor circuitry to: receive image data of an object captured by a camera; analyze a visual feature of the object based on the received image data; generate illumination patterns based on the analyzed visual feature; and control arrays of light sources integrated into a plurality of fingers of a robotic gripper to project the illumination patterns within a grasp volume defined by the plurality of fingers during object manipulation to enhance detection of the visual feature of the object, wherein each light source in the arrays of light sources is individually controllable.
Inventor(s): Shouwei Sun of Shanghai CN for intel corporation, Hemin Han of Shanghai CN for intel corporation, Lili Ma of Shanghai CN for intel corporation, Ke Han of Minhang District CN for intel corporation, Rahul C. Shah of San Francisco CA US for intel corporation, Lu Wang of Shanghai CN for intel corporation
IPC Code(s): G05B13/02, G01J1/42, G01P15/00, G01R33/00
CPC Code(s): G05B13/027
Abstract: techniques for low power indoor/outdoor detection are disclosed. in the illustrative embodiment, an integrated sensor hub receives data from an accelerometer. the sensor hub processes the accelerometer data to determine an activity of the user. depending on the activity of the user, the sensor hub may determine whether the compute device is indoors or outdoors or may receive data from additional sensors, such as a magnetometer, a gyroscope, or an ambient light sensor. the additional sensor data may be used to determine whether the compute device is inside or outside.
Inventor(s): Edward T. GROCHOWSKI of San Jose CA US for intel corporation, Asit K. MISHRA of Hillsboro OR US for intel corporation, Robert VALENTINE of Kiryat Tivon IL for intel corporation, Mark J. CHARNEY of Lexington MA US for intel corporation, Simon C. STEELY, JR. of Hudson NH US for intel corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/3001
Abstract: a processor of an aspect includes a decode unit to decode a matrix multiplication instruction. the matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. the processor also includes an execution unit coupled with the decode unit. the execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. the completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.
Inventor(s): Santosh Ghosh of Hillsboro OR US for intel corporation, Christoph Dobraunig of St. Veit an der Glan AT for intel corporation, Manoj Sastry of Portland OR US for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3885
Abstract: a method comprises fetching, by fetch circuitry, an encoded xor3p instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded xor3pp instruction to generate a decoded xor3pp instruction; and executing, by execution circuitry, the decoded xor3pp instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an xor operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an xor result, perform a rotate operation on the xor result based on the second rotational value to generate a rotated xor; and store the rotated xor result.
Inventor(s): Aaron MCGAVOCK of Orangevale CA US for intel corporation, Venkatesh RAMANI of Milpitas CA US for intel corporation
IPC Code(s): G06F9/48, G06F9/50, G06F11/30
CPC Code(s): G06F9/4881
Abstract: an apparatus, computer-implemented method, and system for prioritizing a plurality of applications based on memory bandwidth utilization. the apparatus includes memory circuitry, machine-readable instructions, and processor circuitry to determine a bandwidth threshold based on the plurality of applications, wherein the bandwidth threshold is a percentage of total memory bandwidth utilization. the apparatus further receives a hint from the processor circuitry when the bandwidth threshold is exceeded. the apparatus then applies a prioritization policy to the plurality of applications while the bandwidth threshold is exceeded.
Inventor(s): Anjali Singhai Jain of Portland OR US for intel corporation, Naren Mididaddi of San Ramon CA US for intel corporation, Arunkumar Balakrishnan of Santa Clara CA US for intel corporation, Tamar Bar-Kanarik of Ramat Hasharon IL for intel corporation, Ji Li of Shanghai CN for intel corporation, Cristian Florin Dumitrescu of Shannon IE for intel corporation, Shweta Shrivastava of Bee Cave TX US for intel corporation, Patrick Connor of Beaverton OR US for intel corporation
IPC Code(s): G06F13/40, G06F13/16
CPC Code(s): G06F13/4004
Abstract: an apparatus includes a host interface; a network interface; hardware storage to store a flow table; and programmable circuitry comprising processors to implement network interface functionality and to: implement a hash table and an age context table, wherein the hash table and the age context table are to reference flow rules maintained in the flow table; process a synchronization packet for a flow by adding a flow rule for the flow to the flow table, adding a hash entry corresponding to the flow rule to the hash table, and adding an age context entry for the flow to the age context table; and process subsequent packets for the flow by performing a first lookup at the hash table to access the flow rule at the flow table and by performing a second lookup at the age context table to apply aging rules to the flow rule in the flow table.
Inventor(s): Ravi SAHITA of Portland OR US for intel corporation, Jiewen YAO of Shanghai CN for intel corporation
IPC Code(s): G06F21/85, G06F21/44, G06F21/60
CPC Code(s): G06F21/85
Abstract: examples include techniques to implement mutual authentication for confidential computing. examples are described of implementing mutual authentication for confidential computing that includes use of local attestation.
Inventor(s): Victoria KOLESOV of Pacific Grove CA US for intel corporation, Andrey DASHKOV of Beaverton OR US for intel corporation
IPC Code(s): G06F30/392
CPC Code(s): G06F30/392
Abstract: disclosed herein is a method for automatically routing a circuit layout of a metal layer of an interposer is provided. the method may include identifying anchor points of the metal layer; sorting the anchor points by location; determining neighbouring anchor points of a same supply net from the location of the anchor points; and creating vertical straps on the circuit layout plan through the neighbouring anchor points of the same supply net.
Inventor(s): Ilya KARPOV of Portland OR US for intel corporation, Tristan TRONIC of Aloha OR US for intel corporation, Arnab SEN GUPTA of Hillsboro OR US for intel corporation, I-Cheng TUNG of Hillsboro OR US for intel corporation, Jin WANG of Castro Valley CA US for intel corporation, Matthew METZ of Portland OR US for intel corporation, Eric MATTSON of Portland OR US for intel corporation
IPC Code(s): H01J37/34, C23C14/34, C23C14/35, H01L21/285, H01L21/308
CPC Code(s): H01J37/3405
Abstract: the present disclosure is directed to a high-voltage magnetron sputtering tool with an enhanced power source including a vacuum chamber containing a magnetron cathode with a magnet array, a target, and an anode, as well as the enhanced power source that includes high-power dc power source and controller that produces a pulsed output. in an aspect, the enhanced power source may include a standard power source that is retrofitted a supplemental high-power dc power source and controller, and alternatively, a high-power dc power source and controller that replaces the standard power source. in addition, the present disclosure is directed to methods for depositing a hydrogen-free diamond-like carbon film on a semiconductor substrate using the high-voltage magnetron sputtering tool. in an aspect, the hydrogen-free diamond-like carbon film may be an etch mask having a sp3 carbon bonding that is greater than 60 percent.
Inventor(s): Feng Zhang of Hillsboro OR US for intel corporation, Tao Chu of Portland OR US for intel corporation, Minwoo Jang of Portland OR US for intel corporation, Yanbin Luo of Portland OR US for intel corporation, Guowei Xu of Portland OR US for intel corporation, Ting-Hsiang Hung of Beaverton OR US for intel corporation, Chiao-Ti Huang of Portland OR US for intel corporation, Robin Chao of Portland OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Yang Zhang of Rio Rancho NM US for intel corporation, Kan Zhang of HILLSBORO OR US for intel corporation
IPC Code(s): H01L23/48, H01L27/092, H01L29/06, H01L29/778, H01L29/786
CPC Code(s): H01L23/481
Abstract: an ic device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. the semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. the backside semiconductor structure may be closer to the backside of a substrate of the ic device than the semiconductor structure. the backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. the backside semiconductor structure may have one or more different materials from the semiconductor structure. for instance, a semiconductor material in the backside semiconductor structure may have a different crystal direction from a semiconductor material in the semiconductor structure. as another example, the backside semiconductor structure may have one or more different chemical compounds from the semiconductor structure. the backside semiconductor structure may be over a backside via that can couple the backside semiconductor structure to a backside metal layer.
Inventor(s): Rajiv Mongia of Portland OR US for intel corporation, Sagar Suthram of Portland OR US for intel corporation, Wilfred Gomes of Portland OR US for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ US for intel corporation, Nicolas Butzen of Portland OR US for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/467, H01L23/473, H01L23/522, H10B80/00
CPC Code(s): H01L25/0652
Abstract: embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (ic) dies; a second set comprising another one or more of the first ic dies; a plate between, and in direct contact with, the first set and the second set; and a second ic die coupled to the first set, the second set, and the plate. each ic die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ild), the substrate and the interconnect region share a planar interface, and the first ic dies and the second ic die are arranged with the planar interfaces of the first ic dies parallel to each other and orthogonal to the planar interface of the second ic die.
20250140748. DOUBLE-SIDED CONDUCTIVE VIA_simplified_abstract_(intel corporation)
Inventor(s): Payam Amin of Portland OR US for intel corporation, Mandip Sibakoti of Hillsboro OR US for intel corporation, Bozidar Marinkovic of Portland OR US for intel corporation, Tofizur RAHMAN of Portland OR US for intel corporation, Conor P. Puls of Portland OR US for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/48, H01L23/498
CPC Code(s): H01L25/0657
Abstract: a fabrication method and associated integrated circuit (ic) structures and devices that include one or more conductive vias is described herein. in one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the ic structure opposite the first side. in one example, a resulting ic structure includes a first portion having a first width, a second portion having a second width, and a third portion having a third width, wherein the third portion is between the first portion and the second portion, and the third width is smaller than the first width and the second width. in one such example, the conductive via tapers from both ends towards the third portion between the ends.
20250141134. MULTIPLE SLOT CARD EDGE CONNECTOR_simplified_abstract_(intel corporation)
Inventor(s): Xiang LI of Portland OR US for intel corporation, George VERGIS of Portland OR US for intel corporation, James A. McCALL of Portland OR US for intel corporation, Yanjie ZHU of Folsom CA US for intel corporation
IPC Code(s): H01R12/72, H01R13/02, H05K1/18
CPC Code(s): H01R12/721
Abstract: a multi-slot connector having reduced dimm-to-dimm pitch distances can support up to 64 memory channels for next generation ddr (double data rate) technology, including ddr6. to support the increase in memory channels, while compensating for limited form factor motherboards, the multi-slot connector includes two or more slots for devices, such as dimms, to connect to a motherboard or other platform. reduced pitch distances between the dimms, shortened connector pins, thinner contacts, and complementary reduced pitch distances in a ball grid array (bga) used to connect to the motherboard or other platform, provides a compact multi-slot connector that can support up to 64 memory channels with improved performance characteristics. an optional cooling device can be employed between the slots as needed to maintain optimal performance.
Inventor(s): Santosh GHOSH of Hillsboro OR US for intel corporation, Xiaoyu RUAN of Folsom CA US for intel corporation, Daniel LEIDERMAN of Kfar Saba IL for intel corporation, Ruben Daniel VARELA VELASCO of Portland OR US for intel corporation
IPC Code(s): H04L9/14
CPC Code(s): H04L9/14
Abstract: a method and device for generating a shared session secret with forward secrecy between a first device and a second device. the first and second devices perform mutual authentication. the first and second devices establish a first shared secret using a key encapsulation mechanism with a long-term cryptographic key pair of the devices. the first and second devices generate an ephemeral cryptographic key pair comprising an ephemeral public key and an ephemeral private key, respectively, and transfer the ephemeral public key of the device to the other device using the first shared secret. the first and second devices then establish a second shared secret using the key encapsulation mechanism with the ephemeral public keys of the first device and the second device. the second shared secret is used as a temporary shared session secret.
20250141794. PROGRAMMING A PACKET PROCESSING DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Xiao WANG of Shanghai CN for intel corporation, Sridhar SAMUDRALA of Portland OR US for intel corporation, Zhirun YAN of Shanghai CN for intel corporation, Ji LI of Shanghai CN for intel corporation, Mohammad Abdul AWAL of Celbridge IE for intel corporation, Qi ZHANG of Shanghai CN for intel corporation, Ping YU of Shanghai CN for intel corporation, Yadong LI of Portland OR US for intel corporation, Hieu TRAN of Portland OR US for intel corporation, Jayaprakash SHANMUGAM of Portland OR US for intel corporation
IPC Code(s): H04L45/00, H04L45/42, H04L45/741
CPC Code(s): H04L45/566
Abstract: examples described herein relate to a network interface device. in some examples, the network interface device includes a host interface; a direct memory access (dma) circuitry; a network interface; and circuitry. the circuitry can be configured to: apply, for a tunnel packet, a single match-action rule that comprises a value of the encapsulation header of the tunnel packet and a value of the encapsulated header, wherein the single match-action rule is based on two or more match-action rules.
Inventor(s): Rui Huang of Santa Clara CA US for intel corporation, Meng Zhang of Beijing CN for intel corporation, Hua Li of Santa Clara CA US for intel corporation, In-Seok Hwang of Santa Clara CA US for intel corporation
IPC Code(s): H04W24/08
CPC Code(s): H04W24/08
Abstract: various embodiments herein provide techniques related to measurements in a testing scenario by a user equipment (ue) that is configured to use a pre-configured measurement gap (pre-mg). in embodiments, the ue may be configured to perform one or more measurements with the pre-mg disabled. the pre-mg may then be enabled and the ue may perform additional measurements. in this way, a plurality of parameters related to the ue and/or the pre-mg may be identified based on the testing scenario. other embodiments may be described and/or claimed.
Inventor(s): Ofer Hareuveni of Hifa IL for intel corporation, Ehud Reshef of Qiryat Tivon IL for intel corporation
IPC Code(s): H04W52/34, H04W52/36, H04W88/10
CPC Code(s): H04W52/346
Abstract: embodiments of the present disclosure are directed to applying the higher effective isotropic radiated power (eirp) limits that are set to subordinate devices to client devices that meet indoor constrains to form their own networks concurrently to operate as a client under the control of indoor access point (ap). other embodiments may be described and claimed.
Inventor(s): Yingyang Li of Beijing CN for intel corporation, Yi Wang Wang of Beijing CN for intel corporation, Gang Xiong of Beaverton OR US for intel corporation, Debdeep Chatterjee of San Jose CA US for intel corporation
IPC Code(s): H04W72/1273, H04W72/0446, H04W72/51, H04W72/566
CPC Code(s): H04W72/1273
Abstract: a ue configured for operating in a 5g nr network may decode signalling that schedules two physical downlink shared channels (pdschs) in a same time slot. when the ue is a reduced-bandwidth (rbw) reduced-capacity (redcap) ue (rbw-redcap ue), the ue may determine if a total number of allocated prbs in an ofdm symbol for the two scheduled pdschs exceed a predetermined value when the two scheduled pdschs either partially or fully overlap in time in non-overlapping prbs. the ue may also prioritize decoding of one of the two scheduled pdschs when the total number of allocated prbs exceed the predetermined value and when the two scheduled pdschs either partially or fully overlap in time in non-overlapping prbs. if a first of the two scheduled pdschs is a unicast pdsch and a second of the two scheduled pdschs is a broadcast pdsch, the ue may prioritize decoding of the unicast pdsch.
Inventor(s): Juha Paavola of Hillsboro OR US for intel corporation, Columbia Mishra of Mountain View CA US for intel corporation, Justin Huttula of Portland OR US for intel corporation, Mark Carbone of Cupertino CA US for intel corporation
IPC Code(s): H05K7/20, B23P15/26, G06F1/20
CPC Code(s): H05K7/20336
Abstract: disclosed embodiments are relate to heat transfer devices or heat exchangers for computing systems, and in particular, to heat pipes for improved thermal performance at a cold plate interface. a thermal exchange assembly includes a heat pipe (hp) directly coupled to a cold plate. the hp includes a window, which is a recessed or depressed portion of the hp. the window is attached to the cold plate at a window section of the cold plate. the cold plate is configured to be placed on a semiconductor device that generates heat during operation. the cold plate transfers the heat to the hp with less thermal resistance than existing hp solutions. other embodiments may be described and/or claimed.
20250142846. LOW RESISTANCE PLANAR CAPACITORS_simplified_abstract_(intel corporation)
Inventor(s): Basavaraj KANTHI of Bengaluru IN for intel corporation, Andrew P. COLLINS of Chandler AZ US for intel corporation, Jian Yong XIE of Chandler AZ US for intel corporation
IPC Code(s): H01L27/10
CPC Code(s): H10D1/696
Abstract: embodiments disclosed herein include a capacitor apparatus. in an embodiment, the apparatus comprises a first metal layer and a first plate above the first metal layer, where the first plate is electrically conductive. in an embodiment, a second plate is above the first plate, where the second plate is electrically conductive, and a third plate is above the second plate, where the third plate is electrically conductive. in an embodiment, a second metal layer is above the third plate, and a first via is between the first metal layer and the second metal layer, where the first via contacts the first plate and the third plate. in an embodiment, a second via is between the first metal layer and the second metal layer, where the second via contacts the second plate, and a third via is between the first metal layer and the first plate.
Inventor(s): Cory BOMBERGER of Portland OR US for intel corporation, Anand S. MURTHY of Portland OR US for intel corporation, Tahir GHANI of Portland OR US for intel corporation, Anupama BOWONDER of Portland OR US for intel corporation
IPC Code(s): H10D30/62, H10D30/01, H10D62/822
CPC Code(s): H10D30/6212
Abstract: fin smoothing, and integrated circuit structures resulting therefrom, are described. for example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. the semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. the sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. a gate stack is over and conformal with the protruding fin portion of the semiconductor fin. a first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.
Inventor(s): Seung Hoon SUNG of Portland OR US for intel corporation, Tristan TRONIC of Aloha OR US for intel corporation, Szuya S. LIAO of Portland OR US for intel corporation, Jack T. KAVALIEROS of Portland OR US for intel corporation
IPC Code(s): H10D64/66, H01L21/28, H01L21/768, H01L23/535, H10D64/01, H10D84/01, H10D84/03, H10D84/83, H10D84/85
CPC Code(s): H10D64/671
Abstract: self-aligned gate endcap (sage) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (sage) architectures with reduced or removed caps, are described. in an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. a second gate electrode is over a second semiconductor fin. a gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. a local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.
Inventor(s): Jeffrey S. LEIB of Beaverton OR US for intel corporation, Srijit MUKHERJEE of Portland OR US for intel corporation, Vinay BHAGWAT of Hillsboro OR US for intel corporation, Michael L. HATTENDORF of Portland OR US for intel corporation, Christopher P. AUTH of Portland OR US for intel corporation
IPC Code(s): H10D84/01, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L23/522, H01L23/528, H01L23/532, H10B10/00, H10D1/47, H10D30/62, H10D30/69, H10D62/13, H10D64/01, H10D64/68, H10D84/03, H10D84/85
CPC Code(s): H10D84/017
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a p-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. a first metal silicide layer is directly on the first and second semiconductor source or drain regions. an n-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. a second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. the first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.
Inventor(s): Robin Chao of Portland OR US for intel corporation, Chiao-Ti Huang of Portland OR US for intel corporation, Guowei Xu of Portland OR US for intel corporation, Yang Zhang of Rio Rancho NM US for intel corporation, Ting-Hsiang Hung of Beaverton OR US for intel corporation, Tao Chu of Portland OR US for intel corporation, Feng Zhang of Hillsboro OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Anand S. Murthy of Portland OR US for intel corporation, Conor P. Puls of Portland OR US for intel corporation, Kan Zhang of Hillsboro OR US for intel corporation
IPC Code(s): H01L27/088, H01L23/498, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H10D84/834
Abstract: an ic device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. for instance, a via may be coupled to a power plane. a jumper may be connected to the via and an electrode of a transistor. with the via and jumper, an electrical connection is built between the power plane and the electrode. the via may be self-aligned. the ic device may include a dielectric structure at a first side of the via. a portion of the jumper may be at a second side of the via. the second side opposes the first side. the dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. the via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.
- Intel Corporation
- B25J13/02
- B25J9/16
- CPC B25J13/025
- Intel corporation
- B25J15/10
- B25J13/08
- B25J19/00
- CPC B25J15/10
- G05B13/02
- G01J1/42
- G01P15/00
- G01R33/00
- CPC G05B13/027
- G06F9/30
- G06F9/38
- CPC G06F9/3001
- CPC G06F9/3885
- G06F9/48
- G06F9/50
- G06F11/30
- CPC G06F9/4881
- G06F13/40
- G06F13/16
- CPC G06F13/4004
- G06F21/85
- G06F21/44
- G06F21/60
- CPC G06F21/85
- G06F30/392
- CPC G06F30/392
- H01J37/34
- C23C14/34
- C23C14/35
- H01L21/285
- H01L21/308
- CPC H01J37/3405
- H01L23/48
- H01L27/092
- H01L29/06
- H01L29/778
- H01L29/786
- CPC H01L23/481
- H01L25/065
- H01L23/00
- H01L23/467
- H01L23/473
- H01L23/522
- H10B80/00
- CPC H01L25/0652
- H01L23/498
- CPC H01L25/0657
- H01R12/72
- H01R13/02
- H05K1/18
- CPC H01R12/721
- H04L9/14
- CPC H04L9/14
- H04L45/00
- H04L45/42
- H04L45/741
- CPC H04L45/566
- H04W24/08
- CPC H04W24/08
- H04W52/34
- H04W52/36
- H04W88/10
- CPC H04W52/346
- H04W72/1273
- H04W72/0446
- H04W72/51
- H04W72/566
- CPC H04W72/1273
- H05K7/20
- B23P15/26
- G06F1/20
- CPC H05K7/20336
- H01L27/10
- CPC H10D1/696
- H10D30/62
- H10D30/01
- H10D62/822
- CPC H10D30/6212
- H10D64/66
- H01L21/28
- H01L21/768
- H01L23/535
- H10D64/01
- H10D84/01
- H10D84/03
- H10D84/83
- H10D84/85
- CPC H10D64/671
- H01L21/033
- H01L21/311
- H01L21/762
- H01L23/528
- H01L23/532
- H10B10/00
- H10D1/47
- H10D30/69
- H10D62/13
- H10D64/68
- CPC H10D84/017
- H01L27/088
- H01L29/08
- H01L29/66
- H01L29/78
- CPC H10D84/834