Intel Corporation patent applications on March 6th, 2025
Patent Applications by Intel Corporation on March 6th, 2025
Intel Corporation: 30 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (6), H01L25/065 (5), H01L23/498 (4), G06T1/20 (2), H04W24/10 (2) G06F9/505 (2), H01L25/0652 (2), B60W60/0013 (1), H01L23/5227 (1), H05K7/20272 (1)
With keywords such as: surface, data, die, device, conductive, circuitry, coupled, memory, including, and metal in patent application abstracts.
Patent Applications by Intel Corporation
20250074464. ASSISTANCE SYSTEM FOR USE ON THE ROAD SURFACE_simplified_abstract_(intel corporation)
Inventor(s): Fabian OBORIL of Karlsruhe (DE) for intel corporation, Cornelius BUERKLE of Karlsruhe (DE) for intel corporation, Frederik PASCH of Karlsruhe (DE) for intel corporation
IPC Code(s): B60W60/00, B60K35/22, B60K35/28
CPC Code(s): B60W60/0013
Abstract: a driving assistance device comprises a processor which is configured to generate a risk map using road surface data and vehicle data; and to generate a driving instruction based on the risk map; wherein the risk map represents areas of risk related to a road surface within a vicinity of a vehicle; and wherein the road surface data represent irregularities of a road surface within the vicinity of the vehicle.
20250076496. AUDIO-BASED DEVICE CONTEXT DETECTION_simplified_abstract_(intel corporation)
Inventor(s): Mariusz Pietrolaj of Gdansk (PL) for intel corporation, Lukasz Kurylo of Gdansk (PL) for intel corporation, Kuba Lopatka of Gdansk (PL) for intel corporation, Marek Zabkiewicz of Gdynia (PL) for intel corporation
IPC Code(s): G01S15/04, G06F1/3206
CPC Code(s): G01S15/04
Abstract: systems and methods are provided for an acoustic-based determination that a device is inside a bag, enabling a device to react early to a potential hot bag scenario before the device begins to overheat. acoustic cues associated with the device being put in a bag can be detected, and an ultrasonic echo can be analyzed to identify characteristics of reflections from a bag material. ambient acoustics are used as a cue for hot bag detection, and acoustic analysis can be implemented in an audio digital signal processor, consuming a minimum amount of energy and allowing the acoustic-based device context detection method to function when the device is in standby, sleep, and/or hibernate mode. when the acoustic-based device context detection method determines that the device is inside a bag, the method prevents the device from entering a high power state, providing users with worry-free battery life.
Inventor(s): Vivek GARG of Folsom CA (US) for intel corporation, Ankush VARMA of Portland OR (US) for intel corporation, Krishnakanth SISTLA of Portland OR (US) for intel corporation, Nikhil GUPTA of Portland OR (US) for intel corporation, Nikethan Shivanand BALIGAR of Hillsboro OR (US) for intel corporation, Stephen WANG of Hillsboro OR (US) for intel corporation, Nilanjan PALIT of Northborough MA (US) for intel corporation, Timothy Yee-Kwong KAM of Portland OR (US) for intel corporation, Adwait PURANDARE of Hillsboro OR (US) for intel corporation, Ujjwal GUPTA of Hillsboro OR (US) for intel corporation, Stanley CHEN of Portland OR (US) for intel corporation, Dorit SHAPIRA of Portland OR (US) for intel corporation, Shruthi VENUGOPAL of Hillsboro OR (US) for intel corporation, Suresh CHEMUDUPATI of Austin TX (US) for intel corporation, Rupal PARIKH of Hillsboro OR (US) for intel corporation, Eric DEHAEMER of Shrewsbury MA (US) for intel corporation, Pavithra SAMPATH of Hudson MA (US) for intel corporation, Phani Kumar KANDULA of Hillsboro OR (US) for intel corporation, Yogesh BANSAL of Beaverton OR (US) for intel corporation, Dean MULLA of Saratoga CA (US) for intel corporation, Michael TULANOWSKI of Fort Collins CO (US) for intel corporation, Stephen Paul HAAKE of Sunnyvale CA (US) for intel corporation, Andrew HERDRICH of Hillsboro OR (US) for intel corporation, Ripan DAS of Beaverton OR (US) for intel corporation, Nazar Syed HAIDER of Fremont CA (US) for intel corporation, Aman SEWANI of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06F1/28, G06F1/30, G06F13/20
CPC Code(s): G06F1/28
Abstract: hierarchical power management (hpm) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. at a simplest level, hpm architecture has a supervisor and one or more supervisee power management units (pmus) that communicate via at least two different communication fabrics. each pmu can behave as a supervisor for a number of supervisee pmus in a particular domain. hpm addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. hpm serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (soc). hpm provides a basis for managing power and thermals across a diverse set of dice.
Inventor(s): JAMES VALERIO of NORTH PLAINS OR (US) for intel corporation, VASANTH RANGANATHAN of EL DORADO HILLS CA (US) for intel corporation, JOYDEEP RAY of FOLSOM CA (US) for intel corporation, PRADEEP RAMANI of MILPITAS CA (US) for intel corporation
IPC Code(s): G06F9/38, G06F13/28, G06T1/20
CPC Code(s): G06F9/3802
Abstract: a graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units. the circuitry is configured to, in response to a cache miss for the read from a first cache, broadcast an event within the graphics processor device to identify data associated with the cache miss, receive the event at a second compute unit in the set of compute units, and prefetch the data identified by the event into a second cache that is local to the second compute unit before an attempt to read the instruction or data by the second thread.
Inventor(s): Jeroen Leijten of Hulsel (NL) for intel corporation, Javier Martin-Langerwerf of Scheessel (DE) for intel corporation
IPC Code(s): G06F9/448, G06F9/30
CPC Code(s): G06F9/4494
Abstract: techniques and mechanisms for identifying a next task to be executed for an application which is modeled with a synchronous data flow (sdf) graph. in an embodiment, the sdf graph comprises nodes which each represent a different respective task, wherein the nodes variously exchange, via channels, tokens which represent data for operations of the application. a manager circuit manages and provides access to schedule registers which provide state information at a node-specific level of granularity. for a given node, a corresponding schedule register provides a status parameter which identifies whether the given node is currently qualified to be executed. the status parameter is based on one or more channel registers which each provide state information at a channel-specific level of granularity. in another embodiment, a processor comprises circuitry to send to the manager circuit a request to identify, based on the schedule registers, a next task to be executed.
Inventor(s): Marcin Pawel Lisowski of Gdynia (PL) for intel corporation, Yair Nahum of Atlit (IL) for intel corporation, Anna Elzbieta Drewek-Ossowicka of Gdansk (PL) for intel corporation
IPC Code(s): G06F9/50, G06F11/34
CPC Code(s): G06F9/505
Abstract: an example apparatus includes at least one programmable circuit to analyze workload runs for a plurality of combinations of enabled setting to determine a subset of the plurality of combinations that satisfy a target performance metric; run a workload for a second combination of enabled settings to generate a result, the second combination combining enabled settings from two or more of the subset of the plurality of combinations; analyze the result to determine the second combination satisfies the target performance metric; and deploy the second combination and the subset of the plurality of combinations to a device to process a second workload using at least one of the second combination of the subset of the plurality of combinations.
20250077299. INFRASTRUCTURE AS CODE DEPLOYMENT MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Alpa Choksi of Portland OR (US) for intel corporation, Patrick Koeberl of Alsbach-Hähnlein (DE) for intel corporation, Steffen Schulz of Darmstadt (DE) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/4401
CPC Code(s): G06F9/505
Abstract: a computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (ipu), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of microservices cluster.
Inventor(s): Bill NALE of Livermore CA (US) for intel corporation, Kuljit S. BAINS of Olympia WA (US) for intel corporation, Lawrence D. BLANKENBECKLER of Cary NC (US) for intel corporation, Ronald ANDERSON of Columbia SC (US) for intel corporation, Jongwon LEE of Portland OR (US) for intel corporation
IPC Code(s): G06F11/10, G11C11/406, G11C11/4096
CPC Code(s): G06F11/1068
Abstract: a memory chip is described. the memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ecc) information to protect the count value. the memory chip includes ecc read logic circuitry to correct an error in the count value. the memory chip includes a comparator to compare the count value against a threshold. the memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ecc write logic circuitry to determine new ecc information for the incremented count value, and write driver circuitry to write the incremented count value and the new ecc information into the storage cells. the memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.
20250077527. VARIABLE PRECISION IN VECTORIZATION_simplified_abstract_(intel corporation)
Inventor(s): Robert Vaughn of Portland OR (US) for intel corporation
IPC Code(s): G06F16/2457, G06F16/22
CPC Code(s): G06F16/24573
Abstract: systems, apparatuses and methods may provide for technology that identifies a first keyword and a second keyword in a plurality of keywords, determines that a first relevance associated with the first keyword is greater than a second relevance associated with the second keyword, vectorizes the first keyword to a first level of precision, vectorizes the second keyword to a second level of precision, wherein the first level of precision is greater than the second level of precision, and stores the vectorized first keyword and the vectorized second keyword to a retrieval-augmented generation (rag) vector database.
Inventor(s): Michael LeMay of Hillsboro OR (US) for intel corporation, Sebastian Osterlund of Amsterdam (NL) for intel corporation, Floris Cornelis Gorter of Amstelveen (NL) for intel corporation, Hans Goran Liljestrand of Helsinki (FI) for intel corporation, Luis Kida of Beaverton OR (US) for intel corporation, Gabriel Ferreira Teles Gomes of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F21/54, G06F21/55
CPC Code(s): G06F21/54
Abstract: techniques for using integrity check value tripwires for memory safety are described. in an embodiment, an apparatus includes an instruction decoder to decode one or more instructions to copy a memory region; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the one or more instructions, including detecting an integrity check value (icv) mismatch; determining whether a granule in the memory region represents a tripwire; determining a suppression mode associated with the one or more instructions; and in response to determining that the suppression mode allows copying the tripwire, copying the tripwire.
Inventor(s): Haihao SHEN of Shanghai (CN) for intel corporation, Feng TIAN of Shanghai (CN) for intel corporation, Xi CHEN of Shanghai (CN) for intel corporation, Huma ABIDI of Danville CA (US) for intel corporation, Yuwen ZHOU of Shanghai (CN) for intel corporation
IPC Code(s): G06N3/08, G06N3/0495, G06V10/774
CPC Code(s): G06N3/08
Abstract: the disclosure provides an apparatus, method, device and medium for label-balanced calibration in post-training quantization of dnns. an apparatus includes interface circuitry configured to receive a training dataset and processor circuitry coupled to the interface circuitry. the processor circuitry is configured to generate a small ground truth dataset by selecting images with a ground truth number of 1 from the training dataset; generate a calibration dataset randomly from the training dataset; if any image in the calibration dataset has the ground truth number of 1, remove the image from the small ground truth dataset; generate a label balanced calibration dataset by replacing an image with a ground truth number greater than a preset threshold in the calibration dataset with a replacing image selected randomly from the small ground truth dataset; and perform calibration using the label balanced calibration dataset in post-training quantization. other embodiments are disclosed and claimed.
Inventor(s): Amandeep Singh of Bangalore (IN) for intel corporation, Arthur Hunter, JR. of Cameron Park CA (US) for intel corporation, Abhinav Srivastava of Bangalore (IN) for intel corporation, Rashmi Agarwal of Bangalore (IN) for intel corporation, Mohit Choradia of Bangalore (IN) for intel corporation
IPC Code(s): G06T1/20, G06T1/60, G06T17/20
CPC Code(s): G06T1/20
Abstract: an apparatus to facilitate tessellation redistribution for reducing latencies in processors is disclosed. the apparatus includes a processor to provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front end and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using a redistribution bus; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.
Inventor(s): Sami Mohammed Alelyani of Phoenix AZ (US) for intel corporation, Paul Jonathan Diglio of Gaston OR (US) for intel corporation, Gregorio Roberto Murtagian of Phoenix AZ (US) for intel corporation, Shengquan Ou of Chandler AZ (US) for intel corporation, Joseph Blane Petrini of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/433, H01L23/427
CPC Code(s): H01L23/4336
Abstract: systems, apparatus, articles of manufacture, and methods for temperature control of jet impingement cooling of integrated circuit packages are disclosed. an example system includes: a first nozzle to direct a first portion of impingement fluid towards an integrated circuit package; a second nozzle to direct a second portion of the impingement fluid towards the integrated circuit package; a first flow restrictor to control a first pressure of the first portion of the impingement fluid provided to the first nozzle; and a second flow restrictor to control a second pressure of the second portion of the impingement fluid provided to the second nozzle.
Inventor(s): Sagar Suthram of Portland OR (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Abhishek A. Sharma of Portland OR (US) for intel corporation
IPC Code(s): H01L23/473, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/473
Abstract: embodiments of a microelectronic assembly may include a first integrated circuit (ic) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first ic die including a substrate with a microchannel, and a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface; and a second ic die having a fourth surface, wherein the conductive trace exposed at the third surface of the first ic die is electrically coupled to the fourth surface of the second ic die by an interconnect.
Inventor(s): Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/482, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/4821
Abstract: embodiments of a microelectronic assembly comprise: a package substrate having a blind cavity between a first surface and a second opposing surface; a bridge die in the blind cavity, the blind cavity being open towards the first surface; and a plurality of integrated circuit (ic) dies coupled to the first surface and to the bridge die. the blind cavity has a floor and a plurality of sidewalls, at least one sidewall is at an obtuse angle to the floor, and the at least one sidewall is patterned with conductive traces.
Inventor(s): Karumbu Nathan Meyyappan of Portland OR (US) for intel corporation, Pooya Tadayon of Portland OR (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Gregory A. Stone of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/538
CPC Code(s): H01L23/49816
Abstract: in one embodiment, an apparatus comprises a substrate with conductive contacts on a first side of the substrate and a housing coupled to the first side of the substrate. the housing defines a set of holes around the conductive contacts. the apparatus further includes gallium-based liquid metal in each hole, with the liquid metal being in contact with the conductive contact of the hole. the apparatus further includes a passivation layer on a surface of the liquid metal in each hole, the passivation layer being on an opposite end of the hole from the conductive contact in the hole.
20250079300. MAGNETIC INDUCTORS FOR SEMICONDUCTOR PACKAGING_simplified_abstract_(intel corporation)
Inventor(s): Aleksandar ALEKSOV of Chandler AZ (US) for intel corporation, Neelam PRABHU GAUNKAR of Chandler AZ (US) for intel corporation, Henning BRAUNISCH of Phoenix AZ (US) for intel corporation, Wenhao LI of Chandler AZ (US) for intel corporation, Feras EID of Chandler AZ (US) for intel corporation, Georgios C. DOGIAMIS of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/522, H01F1/03, H01F41/16
CPC Code(s): H01L23/5227
Abstract: magnetic inductors for microelectronics packages are provided. magnetic inductive structures include a magnetic region, a magnetic region base region, and a conductive region that forms a channel within the magnetic region. the magnetic region has a different chemical composition than the base region. additional structures are provided in which the magnetic region is recessed into a package substrate core. further inductor structures are provided in which the conductive region includes through-core vias and the conductive region at least partially encircles a portion of a package substrate core. additionally, methods of manufacture are provided for semiconductor packages that include magnetic inductors.
Inventor(s): Shairfe Salahuddin of Portland OR (US) for intel corporation, Mudit Bhargava of Austin TX (US) for intel corporation, Sakthi Prashanth of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/522, H10B10/00, H10B12/00
CPC Code(s): H01L23/528
Abstract: a memory device may include one or more semiconductor structures having a frontside and a backside, one or more gate electrodes, and metal layers at both the frontside and backside. a frontside metal layer may include metal lines that are used as bit lines of the memory device. a backside metal layer may include metal lines that are used as write bit lines of the memory device. a write bit line at the backside may be parallel to a bit line at the frontside. another backside metal layer may include metal lines that are used as word lines of the memory device. a word line at the backside may be parallel to a gate electrode. a switch may be between a bit line and a write bit line. the bit line is electrically coupled to the write bit line when the switch is closed.
Inventor(s): Omkar G. Karhade of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Mohammad Enamul Kabir of Portland OR (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L25/065
CPC Code(s): H01L24/80
Abstract: hybrid bonding interconnect (hbi) architectures for scalability. embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. the conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. some embodiments implement a non-bonding moisture seal ring (msr) structure.
Inventor(s): Sagar Suthram of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Abhishek A. Sharma of Portland OR (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/528, H10B80/00
CPC Code(s): H01L25/0652
Abstract: embodiments of a microelectronic assembly may include a first integrated circuit (ic) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first ic die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second ic die having a fourth surface and including voltage regulator circuitry; and a third ic die having a fifth surface, wherein the third surface of the first ic die is electrically coupled to the fifth surface of the third ic die by first interconnects, the fourth surface of the second ic die is electrically coupled to the fifth surface of the third ic die by second interconnects, and the first ic die is electrically coupled to the second ic die by conductive pathways in the third ic die.
Inventor(s): Sagar Suthram of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Abhishek A. Sharma of Portland OR (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/498
CPC Code(s): H01L25/0652
Abstract: embodiments of a microelectronic assembly may include a first integrated circuit (ic) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first ic die including an active region including a capacitor; and a metallization stack including a first conductive trace electrically coupled to a first conductor of the capacitor and a second conductive trace electrically coupled to a second conductor of the capacitor, wherein the first conductive trace and the second conductive trace are parallel to the first and second surfaces and exposed at the third surface; and a second ic die including a fourth surface, where the first conductive trace and the second conductive trace at the third surface of the first ic die are electrically coupled to the fourth surface of the second ic die by interconnects.
Inventor(s): Manoj Sastry of Portland OR (US) for intel corporation, Christopher Gutierrez of Hillsboro IN (US) for intel corporation, Marcio Rogerio Juliato of Portland OR (US) for intel corporation, Shabbir Ahmed of Portland OR (US) for intel corporation, Vuk Lesi of Cornelius OR (US) for intel corporation
IPC Code(s): H04L9/40, G06F1/04
CPC Code(s): H04L63/1416
Abstract: techniques for an attack-aware digital twin in a time sensitive network are described. a method includes receiving time information for a network by an attack-aware digital twin (aadt), the aadt to simulate operations of a clock manager for a node in the network based on models of the clock manager, generating model clock control information to adjust a clock to a network time for the network, the model clock control information to contain a malicious time sample introduced by a time desynchronization attack in the network, and removing the malicious time sample from the model clock control information to adjust the clock to the network time for the network. other embodiments are described and claimed.
20250080941. AUDIO SPATIALIZATION_simplified_abstract_(intel corporation)
Inventor(s): Nikos Kaburlasos of Lincoln CA (US) for intel corporation, Scott W. Cheng of Folsom CA (US) for intel corporation, Devon Worrell of Folsom CA (US) for intel corporation
IPC Code(s): H04S7/00
CPC Code(s): H04S7/304
Abstract: an apparatus includes at least one memory, instructions, and processor circuitry to execute the instructions to track movement of a head of a user wearing earphones, the earphones to move with the movement of the head of the user, the earphones to be communicatively coupled to a computing device. the processor circuitry is to obtain media content, the media content including first audio data for a first channel and second audio data for a second channel. the processor circuitry is to adjust, based on the movement of the head of the user, the first audio data for the first channel and the second audio data for the second channel. the processor circuitry is to cause the adjusted first audio data and the adjusted second audio data to be played by the earphones.
Inventor(s): Valerie J. Parker of Portland OR (US) for intel corporation, Stephen T. Palermo of Chandler AZ (US) for intel corporation, Vishal Gupta of San Diego CA (US) for intel corporation, Patrick L. Connor of Beaverton OR (US) for intel corporation
IPC Code(s): H04W24/04, H04W24/10, H04W84/04
CPC Code(s): H04W24/04
Abstract: various approaches for the deployment and coordination of network operation processing, communications, and mobile device positioning, in connection with backhaul of a radio access network (ran), are disclosed. an example method of operation of backhaul communications used with a radio access network (ran) includes: obtaining measurements corresponding to wireless communications of a radio access network (ran) operating with a backhaul, the measurements based on in-phase and quadrature (iq) data of the wireless communications; performing a comparison of the measurements to an expected operational state of the ran, with the expected operational state being established from a baseline of the iq data collected in the ran; and modifying the wireless communications of the backhaul based on the comparison of the measurements to the expected operational state.
20250081056. DATA COLLECTION TECHNIQUES FOR WIRELESS SYSTEMS_simplified_abstract_(intel corporation)
Inventor(s): Ziyi Li of Beijing (CN) for intel corporation, Yi Guo of Shanghai (CN) for intel corporation, Sudeep Palat of Cheltenham GLS (GB) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation
IPC Code(s): H04W36/00, H04W24/10
CPC Code(s): H04W36/0085
Abstract: embodiments are related to a fifth generation (5g) or sixth generation (6g) wireless communications system. a method for an access node of a wireless system comprises encoding a session start request message to start a data collection session (dcs) to collect data for a machine learning (ml) model from a user equipment (ue) by a base station of a wireless system, the session start request message including ue context information, decoding a session start response message to indicate the start of the dcs by the base station, the session start response message including dcs configuration information for the ml model, and encoding a data collection request message for the ue to collect measurements for the ml model based on the dcs configuration information for the ml model by the base station. other embodiments are described and claimed.
20250081081. MULTIPLE PATH OVER UE-TO-NETWORK AND NG-UU_simplified_abstract_(intel corporation)
Inventor(s): Chang Hong Shan of Shanghai (CN) for intel corporation
IPC Code(s): H04W40/22, H04W88/04
CPC Code(s): H04W40/22
Abstract: an apparatus and system of providing multi-path transmissions are described. a user equipment (ue) sends a multi-path policy provisioning request in a ue policy container to a policy control function (pcf). the pcf provisions a ue route selection policy (ursp) to the ue including a multi-path preference in an access type preference or multi-path parameter of a route selection descriptor of a ursp rule. the multi-path preference indicates a preferred path over a uu interface and layer-2 or layer-3 ue-to-network relay. the ue determines packet data unit (pdu) establishment additionally based on path availability, as well as prose layer-3 ue-to-network relay offload indication and prose policy. the multi-path policy provisioning request is earned in a registration request message or ue policy provisioning request message.
20250081266. MULTI-LINK DEVICE DATA CONTINUITY_simplified_abstract_(intel corporation)
Inventor(s): Po-Kai HUANG of San Ramon CA (US) for intel corporation, Daniel BRAVO of Portland OR (US) for intel corporation, Ofer SCHREIBER of Kiryat Ono (IL) for intel corporation, Arik KLEIN of Givaat Shmuel (IL) for intel corporation, Laurent CARIOU of Milizac (FR) for intel corporation, Robert STACEY of Portland OR (US) for intel corporation
IPC Code(s): H04W76/15, H04L1/1607, H04W84/12, H04W88/10
CPC Code(s): H04W76/15
Abstract: this disclosure describes systems, methods, and devices related to multi-link device (mld) data continuity. an mld device may set up one or more links with a station multi-link device (sta mld), wherein the sta mld comprises one or more logical entities defining separate station devices. the mld device may transmit a data packet associated with a traffic identifier (tid) to the sta mld. the mld device may determine that the data packet was not received by the sta mld. the mld device may retransmit the data packet to the sta mld. the mld device may increment a retransmit counter every time the data packet is retransmitted. the mld device may refrain from transmitting a second data packet until the data packet is dropped or successfully received by the sta mld.
Inventor(s): Arumanayagam RAJASEKAR of Nagercoil (IN) for intel corporation, Kesavan T of Hosur - Taluk (IN) for intel corporation, Praveen YENUBARI of Hyderabad (IN) for intel corporation, Velmurugan B of Attur (IN) for intel corporation
IPC Code(s): H05K1/14, H05K1/02, H05K1/11, H05K3/46
CPC Code(s): H05K1/142
Abstract: embodiments herein relate to systems, apparatuses, techniques, or processes for forming a bridge pcb within one or more metal layers of a main pcb. the bridge pcb, which may be manufactured using msap techniques, may be formed between the first and the second metal layers of the main pcb and may be used for high speed signal routing between two dies, such as a system-on-chip die and a memory die, that are on the main pcb and coupled by the bridge pcb. other embodiments may be described and/or claimed.
20250081396. LIQUID IMMERSION COOLING SYSTEMS_simplified_abstract_(intel corporation)
Inventor(s): Guangying Zhang of Shanghai (CN) for intel corporation, Chuanlou Wang of Shanghai (CN) for intel corporation, Yuehong Fan of Shanghai (CN) for intel corporation, Shaorong Zhou of Shanghai (CN) for intel corporation, Yang Yao of Shanghai (CN) for intel corporation, Yingqiong Bu of Shanghai (CN) for intel corporation, Xiang Que of Suzhou (CN) for intel corporation, Guoliang Ying of Shanghai (CN) for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20272
Abstract: immersion cooling systems are disclosed. an example immersion cooling system includes an immersion tank including a cooling fluid and a reservoir to contain a recirculated portion of the cooling fluid. the reservoir is separated from the immersion tank by a height to generate a liquid surface height variance between the cooling fluid in the immersion tank and the cooling fluid in the reservoir. a supply conduit is to fluidly couple the immersion tank and the reservoir. the cooling fluid to be provided from the reservoir to the immersion tank via gravity.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Anindya DASGUPTA of Portland OR (US) for intel corporation, Ankit Kirit LAKHANI of Hillsboro OR (US) for intel corporation, Guanqun CHEN of Portland OR (US) for intel corporation, Ian TOLLE of Rio Rancho NM (US) for intel corporation, Saurabh ACHARYA of Hillsboro OR (US) for intel corporation, Shengsi LIU of Portland OR (US) for intel corporation, Baofu ZHU of Portland OR (US) for intel corporation, Nikhil MEHTA of Portland OR (US) for intel corporation, Krishna GANESAN of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10D84/83
Abstract: integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires. a gate electrode is over the vertical stack of horizontal nanowires. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. a first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. a second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.
- Intel Corporation
- B60W60/00
- B60K35/22
- B60K35/28
- CPC B60W60/0013
- Intel corporation
- G01S15/04
- G06F1/3206
- CPC G01S15/04
- G06F1/28
- G06F1/30
- G06F13/20
- CPC G06F1/28
- G06F9/38
- G06F13/28
- G06T1/20
- CPC G06F9/3802
- G06F9/448
- G06F9/30
- CPC G06F9/4494
- G06F9/50
- G06F11/34
- CPC G06F9/505
- G06F9/4401
- G06F11/10
- G11C11/406
- G11C11/4096
- CPC G06F11/1068
- G06F16/2457
- G06F16/22
- CPC G06F16/24573
- G06F21/54
- G06F21/55
- CPC G06F21/54
- G06N3/08
- G06N3/0495
- G06V10/774
- CPC G06N3/08
- G06T1/60
- G06T17/20
- CPC G06T1/20
- H01L23/433
- H01L23/427
- CPC H01L23/4336
- H01L23/473
- H01L23/00
- H01L23/498
- H01L25/065
- CPC H01L23/473
- H01L23/482
- CPC H01L23/4821
- H01L23/538
- CPC H01L23/49816
- H01L23/522
- H01F1/03
- H01F41/16
- CPC H01L23/5227
- H01L23/528
- H10B10/00
- H10B12/00
- CPC H01L23/528
- CPC H01L24/80
- H10B80/00
- CPC H01L25/0652
- H04L9/40
- G06F1/04
- CPC H04L63/1416
- H04S7/00
- CPC H04S7/304
- H04W24/04
- H04W24/10
- H04W84/04
- CPC H04W24/04
- H04W36/00
- CPC H04W36/0085
- H04W40/22
- H04W88/04
- CPC H04W40/22
- H04W76/15
- H04L1/1607
- H04W84/12
- H04W88/10
- CPC H04W76/15
- H05K1/14
- H05K1/02
- H05K1/11
- H05K3/46
- CPC H05K1/142
- H05K7/20
- CPC H05K7/20272
- H01L27/088
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/78
- H01L29/786
- CPC H10D84/83