Intel Corporation patent applications on March 20th, 2025
Patent Applications by Intel Corporation on March 20th, 2025
Intel Corporation: 38 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (7), H01L29/06 (6), H01L25/065 (5), H01L29/423 (4), H01L29/78 (4) G06F11/1004 (2), H01L23/15 (2), G01R31/3025 (1), H04R1/2834 (1), H04L5/0051 (1)
With keywords such as: structure, gate, include, region, layer, coupled, material, surface, face, and example in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Zhen ZHOU of Chandler AZ US for intel corporation, Renzhi LIU of Portland OR US for intel corporation, Jong-Ru GUO of Portland OR US for intel corporation, Kenneth P. FOUST of Beaverton OR US for intel corporation, Jason A. MIX of Portland OR US for intel corporation, Kai XIAO of Portland OR US for intel corporation, Zuoguo WU of San Jose CA US for intel corporation, Daqiao DU of Lake Oswego OR US for intel corporation
IPC Code(s): G01R31/302, G01R31/28, G01R31/303, H01P3/08, H01Q9/16, H04B5/48
CPC Code(s): G01R31/3025
Abstract: a high volume manufacturing (hvm) test system including a test device defining an opening configured to receive a package under test, the test device including an external access agent (eaa) including: a first leaky surface wave launcher for near field wireless communication, the first leaky surface wave launcher configured to wirelessly provide sideband signals to and wirelessly receive the sideband signals from a silicon package agent physically positioned in a separate package as the eaa; and a first transceiver electrically coupled to the first leaky surface wave launcher, the first transceiver configured to: process the sideband signals received by the first leaky surface wave launcher; and generate the sideband signals for wireless transmission by the first leaky surface wave launcher.
20250093498. RADAR APPARATUS, SYSTEM, AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Ophir Shabtay of Tsofit IL for intel corporation, Oren Shalita of Tel-Aviv IL for intel corporation
IPC Code(s): G01S13/931, G01S7/02, G01S7/35, G01S13/34, G01S13/42, G01S13/72, G01S13/87, G01S13/88, G01S13/89
CPC Code(s): G01S13/931
Abstract: some demonstrative aspects include radar apparatuses, devices, systems and methods. in one example, a radar system may include a plurality of radar devices. for example, a radar device may include one or more transmit (tx) antennas to transmit radar tx signals, one or more receive (rx) antennas to receive radar rx signals, and a processor to generate radar information based on the radar rx signals. in one example, the radar system may be implemented as part of a vehicle. in other aspects, the radar system may include any other additional or alternative elements and/or may be implemented as part of any other device or system.
Inventor(s): Himanshu Kaul of Portland OR US for intel corporation, Mark A. Anders of Hillsboro OR US for intel corporation, Sanu K. Mathew of Hillsboro OR US for intel corporation, Anbang Yao of Beijing CN for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Ping T. Tang of Edison NJ US for intel corporation, Michael S. Strickland of Sunnyvale CA US for intel corporation, Xiaoming Chen of Shanghai CN for intel corporation, Tatiana Shpeisman of Menlo Park CA US for intel corporation, Abhishek R. Appu of El Dorado Hills CA US for intel corporation, Altug Koker of El Dorado Hills CA US for intel corporation, Kamal Sinha of Rancho Cordova CA US for intel corporation, Balaji Vembu of Folsom CA US for intel corporation, Nicolas C. Galoppo Von Borries of Portland OR US for intel corporation, Eriko Nurvitadhi of Hillsboro OR US for intel corporation, Rajkishore Barik of Santa Clara CA US for intel corporation, Tsung-Han Lin of Campbell CA US for intel corporation, Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, Sanjeev Jahagirdar of Folsom CA US for intel corporation
IPC Code(s): G06F9/30, G06F1/16, G06F7/483, G06F7/544, G06F9/38, G06F17/16, G06N3/044, G06N3/045, G06N3/063, G06N3/08, G06N20/00, G06T15/00, G09G5/393
CPC Code(s): G06F9/3001
Abstract: one embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (simt) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
Inventor(s): Sergej Deutsch of Hillsboro OR US for intel corporation, David M. Durham of Beaverton OR US for intel corporation, Karanvir Grewal of Hillsboro OR US for intel corporation, Rajat Agarwal of Portland OR US for intel corporation
IPC Code(s): G06F11/10, G06F3/06
CPC Code(s): G06F11/1004
Abstract: the technology disclosed herein comprises a processor; a memory to store data and a plurality of error correcting code (ecc) bits associated with the data; and a memory controller coupled to the memory, the memory controller to receive a write request from the processor and, when an access control field is selected in the write request, perform an exclusive or (xor) operation on the plurality of ecc bits and a fixed encoding pattern to generate a plurality of encoded ecc bits and store the data and the plurality of encoded ecc bits in the memory.
Inventor(s): Kishore KASICHAINULA of Johns Creek GA US for intel corporation, Thierry BEAUMONT of Saint Germain en Laye FR for intel corporation, Dhanumjai PASUMARTHY of Hyderabad IN for intel corporation, Sudhakar KAMMA of El Dorado Hills CA US for intel corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: methods and apparatus for low latency fail-operational time sensitive networking. an apparatus includes an error detection and path switching (edps) circuit comprising circuitry to read data from volatile memory, detect whether read data is errant, the errant data including one or more uncorrectable errors, and send a message to access correct data corresponding to the errant data stored in a non-volatile memory device, the message identifying the correct data to be returned to the edps circuit. the apparatus receives the correct data and enables the correct data to be read by circuitry coupled to the epds circuit. the edps circuit includes error correction code (ecc) logic to detect uncorrectable errors, detect the data has no ecc errors, and detect and correct single-bit errors to obtain corrected data. data with no ecc errors and corrected data is immediately made available for reading by the circuitry coupled to the epds circuit.
Inventor(s): Gopi Krishna Jha of Mysore, Karnataka IN for intel corporation, Sameh Gobriel of Dublin CA US for intel corporation, Nilesh Jain of Portland OR US for intel corporation
IPC Code(s): G06F40/284, G06F16/28
CPC Code(s): G06F40/284
Abstract: key-value (kv) caching accelerates inference in large language models (llms) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. due to large context lengths in modern llms, kv cache size can exceed the model size, which can negatively impact throughput. to address this issue, a multi-granular clustering-based solution for kv cache compression can be implemented. key tensors and value tensors corresponding unimportant tokens can be approximated using clusters created at different clustering-levels with varying accuracy. accuracy loss can be mitigated by using proxies produced at finer granularity clustering-level for a subset of attention heads that are more significant. more significant attention heads can have a higher impact on model accuracy than less significant attention heads. latency is improved by retrieving proxies from a faster memory for a subset of attention heads that are less significant, when impact on accuracy is lower.
Inventor(s): Ofer RIVLIN of Tel-Aviv IL for intel corporation, Mor UZIEL of Caesarea IL for intel corporation, Dan HOROVITZ of Rishon Lezion IL for intel corporation, David BIRNBAUM of Modiin IL for intel corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: it is provided a non-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries of an apparatus, causing the one or more processing circuitries to perform locally on the apparatus a method. the method includes obtaining a pretrained machine learning model by the apparatus. the method further includes generating training data based on user-related information. the user-related information relating to a user behavior during interaction of the user with the apparatus. the method further includes training the pretrained machine learning model based on the generated training data by the apparatus to obtain a personalized machine learning model. the method further includes executing the personalized machine learning model by the apparatus.
20250095099. PAGE FAULTING AND SELECTIVE PREEMPTION_simplified_abstract_(intel corporation)
Inventor(s): Altug Koker of El Dorado Hills CA US for intel corporation, Ingo Wald of Salt Lake City UT US for intel corporation, David Puffer of Tempe AZ US for intel corporation, Subramaniam M. Maiyuran of Gold River CA US for intel corporation, Prasoonkumar Surti of Folsom CA US for intel corporation, Balaji Vembu of Folsom CA US for intel corporation, Guei-Yuan Lueh of San Jose CA US for intel corporation, Murali Ramadoss of Folsom CA US for intel corporation, Abhishek R. Appu of El Dorado Hills CA US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation
IPC Code(s): G06T1/20, G06F9/30, G06F9/38, G06F9/46, G06F9/48
CPC Code(s): G06T1/20
Abstract: one embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. the circuitry includes an execution resource and a preemption status register. the execution resource is configured to execute an instruction. during execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.
20250095122. DISTORTION MESHES AGAINST CHROMATIC ABERRATIONS_simplified_abstract_(intel corporation)
Inventor(s): DANIEL POHL of Saarbrücken DE for intel corporation
IPC Code(s): G06T5/80, G02B27/01, G06T5/50
CPC Code(s): G06T5/80
Abstract: described herein is a technique in which a plurality of distortion meshes compensate for radial and chromatic aberrations created by optical lenses. the plurality of distortion meshes may include different lens specific parameters that allow the distortion meshes to compensate for chromatic aberrations created within received images. the plurality of distortion meshes may correspond to a red color channel, green color channel, or blue color channel to compensate for the chromatic aberrations. the distortion meshes may also include shaped distortions and grids to compensate for radial distortions, such as pin cushion distortions. in one example, the system uses a barrel-shaped distortion and a triangulation grid to compensate for the distortions created when the received image is displayed on a lens.
20250095217. LOW RANK MATRIX COMPRESSION_simplified_abstract_(intel corporation)
Inventor(s): Tomer Bar-On of Petah Tikva IL for intel corporation, Jacob Subag of Kiryat Haim IL for intel corporation, Yaniv Fais of Tel Aviv IL for intel corporation, Jeremie Dreyfuss of Tel-Aviv IL for intel corporation, Gal Novik of Haifa IL for intel corporation, Gal Leibovich of Kiryat Yam IL for intel corporation, Tomer Schwartz of Even Yehuda IL for intel corporation, Ehud Cohen of Kiryat Motskin IL for intel corporation, Lev Faivishevsky of Kfar Saba IL for intel corporation, Uzi Sarel of Zichron-Yaakov IL for intel corporation, Amitai Armon of Tel-Aviv IL for intel corporation, Yahav Shadmiy of Ramat Gan IL for intel corporation
IPC Code(s): G06T9/00, G06N3/044, G06N3/045, G06N3/047, G06N3/048, G06N3/084, G06N3/088, H04N19/42, H04N19/436
CPC Code(s): G06T9/002
Abstract: in an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (cnn) layer. other embodiments are also disclosed and claimed.
20250095522. IMAGING FOR FOLDABLE DISPLAYS_simplified_abstract_(intel corporation)
Inventor(s): Srikanth Kambhatla of Portland OR US for intel corporation
IPC Code(s): G09G3/00, G06F1/16, G09G5/00, G09G5/14
CPC Code(s): G09G3/003
Abstract: a processing unit, comprising a display interface to control a foldable display with multiple segments created by fold lines in the foldable display. the processing unit also including a plurality of lanes to connect the display interface to the foldable display, where each segment of the foldable display is connected to a lane. the processing unit also including a multi-segment protocol component to instruct the display interface to drive data to each segment of the display through the plurality of lanes.
Inventor(s): Abhishek A. Sharma of Portland OR US for intel corporation, Juan G. Alzate-Vinasco of Tigard OR US for intel corporation, Fatih Hamzaoglu of Portland OR US for intel corporation, Wilfred Gomes of Portland OR US for intel corporation, Anand S. Murthy of Portland OR US for intel corporation, Tahir Ghani of Portland OR US for intel corporation, Van H. Le of Beaverton OR US for intel corporation
IPC Code(s): G11C5/06, G11C11/4091, G11C11/419
CPC Code(s): G11C5/063
Abstract: an ic device may include a cmos layer and memory layers at the frontside and backside of the cmos layer. the cmos layer may include one or more logic circuits, which may include mosfet transistors. a memory layer may include one or more memory arrays. a memory array may include memory cells (e.g., dram cells), bit lines, and word lines. the logic circuits may include word line drivers and sense amplifiers. word lines in different memory layers may share the same word line driver. bit lines in different memory layers may share the same sense amplifier. the ic device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. a memory layer may be bonded with the cmos layer through a bonding layer that provides a bonding interface between the memory layer and the cmos layer.
20250096009. LOW COST PACKAGE WARPAGE SOLUTION_simplified_abstract_(intel corporation)
Inventor(s): Omkar G. KARHADE of Chandler AZ US for intel corporation, Nitin A. DESHPANDE of Chandler AZ US for intel corporation, Debendra MALLIK of Chandler AZ US for intel corporation, Bassam M. ZIADEH of Gilbert AZ US for intel corporation, Yoshihiro TOMITA of Tsukuba-shi JP for intel corporation
IPC Code(s): H01L21/56, H01L23/00, H01L23/16, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L21/563
Abstract: embodiments of the invention include device packages and methods of forming such packages. in an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. one or more openings may be formed through the reinforcement layer. in an embodiment, a device die may be placed into one of the openings. the device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. embodiments of the invention may include a molded reinforcement layer. alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
Inventor(s): Mohamed R. Saber of College Station TX US for intel corporation, Hanyu Song of Chandler AZ US for intel corporation, Fanyi Zhu of Gilbert AZ US for intel corporation, Bai Nie of Chandler AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Deniz Turan of Chander AZ US for intel corporation, Yonggang Li of Chandler AZ US for intel corporation, Naiya Soetan-Dodd of Mesa AZ US for intel corporation, Shuren Qu of Gilbert AZ US for intel corporation
IPC Code(s): H01L23/15, H01L21/48, H01L23/00, H01L23/48, H01L25/065
CPC Code(s): H01L23/15
Abstract: microelectronic assemblies with glass cores that have undergone localized thermal healing and/or localized doping in regions adjacent to glass surface are disclosed. in one example, a microelectronic assembly includes a glass core having a first face, an opposing second face, a sidewall extending between the first face and the second face, a surface region, and a bulk region, where the surface region is a portion of the glass core that starts at a surface of the first face, the second face, or the sidewall and extends from the surface into the glass core by a total depth of up to about 50 micron, the bulk region is a portion of the glass core further away from the surface than the surface region, and a density of the surface region is higher than a density of the bulk region, e.g., at least about 5% higher or at least about 7.5% higher.
Inventor(s): Jeremy Ecton of Gilbert AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Tarek A. Ibrahim of Mesa AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Benjamin T. Duong of Phoenix AZ US for intel corporation, Suddhasattwa Nad of Chandler AZ US for intel corporation
IPC Code(s): H01L23/15, H01L23/498, H01L23/522, H01L23/538, H01L25/065
CPC Code(s): H01L23/15
Abstract: a microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. the bridge die and the glass structure are embedded in a substrate. the assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. the glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. the glass structure may include an embedded passive device, such as an embedded inductor or capacitor.
20250096114. VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING_simplified_abstract_(intel corporation)
Inventor(s): Robin Chao of Portland OR US for intel corporation, Chiao-Ti Huang of Portland OR US for intel corporation, Guowei Xu of Portland OR US for intel corporation, Ting-Hsiang Hung of Beaverton OR US for intel corporation, Tao Chu of Portland OR US for intel corporation, Feng Zhang of Hillboro OR US for intel corporation, Chia-Ching Lin of Portland OR US for intel corporation, Yang Zhang of Rio Rancho NM US for intel corporation, Anand Murthy of Portland OR US for intel corporation, Conor P. Puls of Portland OR US for intel corporation
IPC Code(s): H01L23/522, H01L23/528
CPC Code(s): H01L23/5226
Abstract: techniques to form semiconductor devices can include one or more via structures having substrate taps. a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). the gate structure may extend over the semiconductor regions of any number of devices along a given direction. the gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. the via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. the conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. the via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.
Inventor(s): Jeremy Ecton of Gilbert AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Tarek A. Ibrahim of Mesa AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L21/48
CPC Code(s): H01L23/5381
Abstract: a microelectronic assembly includes a bridge die embedded in a substrate. the substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. a cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. after cavity formation, a selective metallization of the lower and upper layers of the doped dielectric material is performed, providing well-aligned metal layers in the region of the bridge die and the region around the bridge die.
20250096154. Package Substrates with Stiffener Interposers_simplified_abstract_(intel corporation)
Inventor(s): Chin Mian CHOONG of Georgetown MY for intel corporation, Jiun Hann SIR of Gelugor MY for intel corporation, Poh Boon KHOO of Perai MY for intel corporation, Juha PAAVOLA of Hillsboro OR US for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L23/15, H01L23/498, H01L23/552
CPC Code(s): H01L23/562
Abstract: the present disclosure is directed to a stiffener having a first lateral member and a vertical member that form a frame structure that encloses around a package substrate of a semiconductor package, and the vertical member having an upper end connected to the first lateral member and a lower end extending downward from the first lateral member for connecting to a printed circuit board.
Inventor(s): Debendra Mallik of Chandler AZ US for intel corporation, Sergio Antonio Chan Arguedas of Chandler AZ US for intel corporation, Jimin Yao of Chandler AZ US for intel corporation, Chandra Mohan Jha of Tempe AZ US for intel corporation
IPC Code(s): H01L23/00, H01L23/16, H01L23/367
CPC Code(s): H01L24/17
Abstract: embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. a plurality of solder thermal interface material (stim) thermal interconnects may be coupled with the die and an integrated heat spreader (ihs) may be coupled with the plurality of stim thermal interconnects. a thermal underfill material may be positioned between the ihs and the die such that the thermal underfill material at least partially surrounds the plurality of stim thermal interconnects. other embodiments may be described or claimed.
20250096194. MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Shawna M. Liff of Scottsdale AZ US for intel corporation, Adel A. Elsherbini of Tempe AZ US for intel corporation, Johanna M. Swan of Scottsdale AZ US for intel corporation, Arun Chandrasekhar of Chandler AZ US for intel corporation
IPC Code(s): H01L23/00, H01L25/00, H01L25/18
CPC Code(s): H01L24/81
Abstract: microelectronic assemblies, and related devices and methods, are disclosed herein. for example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
Inventor(s): Adel A. ELSHERBINI of Chandler AZ US for intel corporation, Henning BRAUNISCH of Phoenix AZ US for intel corporation, Javier SOTO GONZALEZ of Chandler AZ US for intel corporation, Shawna M. LIFF of Scottsdale AZ US for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/538
CPC Code(s): H01L25/0655
Abstract: an embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. the tall via pillars may span a z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.
Inventor(s): Nicolas Butzen of Portland OR US for intel corporation, Harish K. Krishnamurthy of Beaverton OR US for intel corporation
IPC Code(s): H01L25/065, H01L25/18, H02M3/158
CPC Code(s): H01L25/0657
Abstract: embodiments herein relate to a voltage regular (vr) formed by components which are distributed over a stack of dice or wafers. separate vrs can be provided in separate dice or wafers, where their outputs are coupled at an output path. a common control circuit can be used to control each vr. passive components of a vr can be distributed on separate dice. for example, capacitors or inductors on the different dice or wafers can be coupled in parallel or in series, respectively. the stack can include dice or wafers of different types, such as silicon and gallium nitride. a first vr on a first type of die or wafer can be arranged in cascade with a second vr on a second type of die or wafer. the components in the different dice or wafers can be coupled by vias such as through-silicon vias.
Inventor(s): Sally Safwat Amin of Hillsboro OR US for intel corporation
IPC Code(s): H03K17/06, H03K17/687
CPC Code(s): H03K17/063
Abstract: embodiments herein relate to a driver for a voltage converter which efficiently generates a control gate voltage of a power switch. the driver applies a staircase increasing and decreasing voltage to the control gate with three or more voltage levels, including an initial level such as 0 v, one or more intermediate voltages, and a peak drive voltage. the one or more intermediate voltages can be generated by a charge-recycling circuit which can include push-pull capacitors or switched flying capacitors. the push-pull capacitors are provided in a number of push-pull regulation circuits which is equal to the number of intermediate voltages. the switched flying capacitors are provided in a circuit where the number of flying capacitors is equal to the number of intermediate voltages.
Inventor(s): Nicolas Wainstein of Haifa IL for intel corporation, Eugene Avner of Haifa IL for intel corporation
IPC Code(s): H03L7/10, H03L7/081, H03L7/089
CPC Code(s): H03L7/105
Abstract: a system includes memory and at least one processor coupled to the memory and configured to receive a phase detector (pd) error signal. the pd error signal indicates a leading clock signal of at least two clock signals. the at least two clock signals are generated based on an input clock signal and a voltage control signal. the at least one processor receives a toggling signal indicating whether one of the at least two clock signals is toggling between clock cycles of the input clock signal. a code value is generated based on the pd error signal and the toggling signal. the at least one processor causes generation of the voltage control signal based on the code value.
Inventor(s): Guotong Wang of Santa Clara CA US for intel corporation, Alexei Davydov of Santa Clara CA US for intel corporation, Bishwarup Mondal of San Ramon CA US for intel corporation, Avik Sengupta of Santa Clara CA US for intel corporation, Dong Han of Santa Clara CA US for intel corporation
IPC Code(s): H04L5/00, H04L27/26, H04W72/232
CPC Code(s): H04L5/0051
Abstract: systems, apparatuses, methods, and computer-readable media are provided for enhanced demodulation reference signal (dmrs) for uplink transmissions with up to eight layers (e.g., an uplink single user (su)-multiple input, multiple output (mimo) transmission). additionally, embodiments relate to antenna port indication for dmrs transmission. other embodiments may be described and claimed.
20250097081. COMPLEX-ZERO EQUALIZER CIRCUIT_simplified_abstract_(intel corporation)
Inventor(s): Sashank Krishnamurthy of Hillsboro OR US for intel corporation, Mozhgan Mansuri of Portland OR US for intel corporation
IPC Code(s): H04L25/03, H01S5/42
CPC Code(s): H04L25/03878
Abstract: embodiments herein relate to an equalizer in a communication system. in an example implementation, the communication system is an optical system including a vertical-cavity surface-emitting laser (vcsel). a transfer function of the equalizer has two complex-zeroes to compensate for a group delay variation due to an underdamped complex-pole pair of the vcsel optical response. the equalizer may include a first transistor having a control gate coupled to an input path, a drain coupled to an output path, and a source, and first, second and third paths coupled between the source and ground. the first path includes, in series, a resistor, a node and a capacitor, the second path includes a second transistor having a control gate coupled to the node, and the third path includes a capacitor. a tuning process can be used to achieve a desired frequency and quality factor.
Inventor(s): Francesc GUIM BERNAT of Barcelona ES for intel corporation, Suraj PRABHAKARAN of Aachen DE for intel corporation, Kshitij A. DOSHI of Tempe AZ US for intel corporation, Brinda GANESH of Hillsboro OR US for intel corporation, Timothy VERRALL of Pleasant Hill CA US for intel corporation
IPC Code(s): H04L41/16, G06N3/04, G06N5/04, H04L41/0816, H04L41/5009, H04L41/5019, H04L41/5051
CPC Code(s): H04L41/16
Abstract: examples include techniques for artificial intelligence (ai) capabilities at a network switch. these examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an ai service to be provided by users requesting the ai service.
Inventor(s): Omer Ben-Shalom of Rishon Le-Tzion IL for intel corporation, Yoni Kahana of Ein Sarid IL for intel corporation, Yaron Klein of Rosh HaAyin IL for intel corporation, Ilil Blum Shem-Tov of Kiryat Tivon IL for intel corporation, Dan Horovitz of Rishon Letzion IL for intel corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/1425
Abstract: an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to interface circuitry to obtain a pre-trained detection model, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to tune the pre-trained detection model based on first local behavior data and execute the tuned detection model to detect an anomaly in second local behavior data associated with the apparatus.
Inventor(s): Francesc Guim Bernat of Barcelona ES for intel corporation, Patrick Bohan of Portland OR US for intel corporation, Kshitij Arun Doshi of Tempe AZ US for intel corporation, Brinda Ganesh of Portland OR US for intel corporation, Andrew J. Herdrich of Hillsboro OR US for intel corporation, Monica Kenguva of Phoenix AZ US for intel corporation, Karthik Kumar of Chandler AZ US for intel corporation, Patrick G. Kutch of Tigard OR US for intel corporation, Felipe Pastor Beneyto of Holmdel NJ US for intel corporation, Rashmin Patel of Chandler AZ US for intel corporation, Suraj Prabhakaran of Aachen DE for intel corporation, Ned M. Smith of Beaverton OR US for intel corporation, Petar Torre of Feldkirchen DE for intel corporation, Alexander Vul of San Jose CA US for intel corporation
IPC Code(s): H04L67/148, G06F9/48, H04L41/5003, H04L41/5019, H04L43/0811, H04L47/70, H04L67/00, H04L67/10, H04W4/40, H04W4/70
CPC Code(s): H04L67/148
Abstract: an architecture to perform resource management among multiple network nodes and associated resources is disclosed. example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge qos pre-allocation; and automatic qos migration across edge computing nodes. in a specific example, a technique for service migration includes: identifying a service operated with computing resources in an edge computing system, involving computing capabilities for a connected edge device with an identified service level; identifying a mobility condition for the service, based on a change in network connectivity with the connected edge device; and performing a migration of the service to another edge computing system based on the identified mobility condition, to enable the service to be continued at the second edge computing apparatus to provide computing capabilities for the connected edge device with the identified service level.
Inventor(s): Avinash Manu Aravindan of Alappuzha IN for intel corporation, Sumod Cherukkate of Bangalore IN for intel corporation, Prakash Kurma Raju of Bangalore IN for intel corporation, Ezekiel Poulose of Ernakulam IN for intel corporation
IPC Code(s): H04R1/28, H04R1/02, H04R7/04, H04R7/18, H04R31/00
CPC Code(s): H04R1/2834
Abstract: methods and apparatus to improve bass response of speakers in portable devices are disclosed. an example speaker includes a speaker box having a front face and a back face, a distance between the front face and the back face being less than 1 inch. the speaker box has a first portion of a back volume and a second portion of the back volume, the first portion of the back volume defined between the back face and a first region of the front face, the second portion of the back volume defined between the back face a second region of the front face. the example speaker further includes an active speaker driver including a first diaphragm, the first diaphragm coupled to the first region of the front face. the example speaker also includes a second diaphragm coupled to the second region of the front face, the second diaphragm being passive.
Inventor(s): Alexey Khoryaev of Santa Clara CA US for intel corporation, Mikhail Shilov of Santa Clara CA US for intel corporation, Sergey Panteleev of Kildare IE for intel corporation
IPC Code(s): H04W72/25, H04W72/02, H04W92/18
CPC Code(s): H04W72/25
Abstract: various embodiments herein provide techniques related to resource selection for sidelink transmissions. in some embodiments, the resource selection procedure may related to identification of whether to use a first or second resource selection procedure. in some embodiments, the resource selection procedure may relate to removal of non-preferred resources from a list of candidate resources. other embodiments may be described and/or claimed.
Inventor(s): Dan S. LAVRIC of Beaverton OR US for intel corporation, Sean PURSEL of Hillsboro OR US for intel corporation, Dimitri KIOUSSIS of San Jose CA US for intel corporation, Lukas BAUMGARTEL of Portland OR US for intel corporation, Mahdi AHMADI of Portland OR US for intel corporation, Cortnie S. VOGELSBERG of Beaverton OR US for intel corporation, Mengcheng LU of Portland OR US for intel corporation, Omar Kyle HITE of Beaverton OR US for intel corporation, Justin E. MUELLER of Portland OR US for intel corporation, Lily Mao of Portland OR US for intel corporation
IPC Code(s): H01L29/78, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/794
Abstract: integrated circuit structures having dual stress gates are described. for example, an integrated circuit structure includes a first vertical stack of horizontal nanowires, and a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires. an nmos gate electrode is over the first vertical stack of horizontal nanowires, the nmos gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires. a pmos gate electrode is over the second vertical stack of horizontal nanowires, the pmos gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires. the tensile layer of the nmos gate electrode is not included in the pmos gate electrode.
20250098239. AIR GAP INSULATION IN PLACE OF GATE SPACERS_simplified_abstract_(intel corporation)
Inventor(s): Seda Cekli of Portland OR US for intel corporation, Makram Abd El Qader of Hillsboro OR US for intel corporation, Aaron D. Lilak of Beaverton OR US for intel corporation, Anh Phan of Beaverton OR US for intel corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/08, H01L29/423, H01L29/778, H01L29/786
CPC Code(s): H10D62/118
Abstract: ic structures with air gap insulation in place of gate spacers are disclosed. an example ic structure includes a transistor comprising a channel region and a s/d region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a s/d contact structure coupled to the s/d region and comprising a second electrically conductive material, a gap between the gate structure and the s/d contact structure, and a liner material over at least a portion of a sidewall of the region below the contact structure, the liner material comprising aluminum and oxygen.
20250098242. AIR GAP INSULATION IN PLACE OF GATE SPACERS_simplified_abstract_(intel corporation)
Inventor(s): Seda Cekli of Portland OR US for intel corporation, Makram Abd El Qader of Hillsboro OR US for intel corporation, Sudipto Naskar of Portland OR US for intel corporation, Anh Phan of Beaverton OR US for intel corporation, Rishabh Mehandru of Portland OR US for intel corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/78
CPC Code(s): H10D62/123
Abstract: ic structures with air gap insulation in place of gate spacers are disclosed. an example ic structure includes a transistor comprising a channel region and a source or drain (s/d) region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a s/d contact structure coupled to the s/d region and comprising a second electrically conductive material, a gap between the gate structure and the s/d contact structure, and a liner material on at least a portion of a sidewall of the gap, the liner material comprising aluminum and oxygen.
Inventor(s): Avijit Barik of Portland OR US for intel corporation, Tao Chu of Portland OR US for intel corporation, Minwoo Jang of Portland OR US for intel corporation, Tofizur RAHMAN of Portland OR US for intel corporation, Conor P. Puls of Portland OR US for intel corporation, Ariana E. Bondoc of Hillsboro OR US for intel corporation, Diane Lancaster of Hillsboro OR US for intel corporation, Chi-Hing Choi of Portland OR US for intel corporation, Derek Keefer of Hillsboro OR US for intel corporation
IPC Code(s): H01L29/45, H01L21/285, H01L23/522, H01L23/532, H01L29/06, H01L29/40, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D62/83
Abstract: disclosed herein are ic structures and devices that aim to mitigate proximity effects of deep trench vias. an example ic structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 10atoms per cubic centimeter.
Inventor(s): Andrew W. YEOH of Portland OR US for intel corporation, Ilsup JIN of Portland OR US for intel corporation, Angelo KANDAS of Portland OR US for intel corporation, Michael L. HATTENDORF of Portland OR US for intel corporation, Christopher P. AUTH of Portland OR US for intel corporation
IPC Code(s): H01L29/66, H01L21/02, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8234, H01L21/8238, H01L23/00, H01L23/522, H01L23/528, H01L23/532, H01L27/02, H01L27/088, H01L27/092, H01L29/06, H01L29/08, H01L29/165, H01L29/167, H01L29/417, H01L29/51, H01L29/78, H10B10/00
CPC Code(s): H10D64/017
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a fin. an isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. a gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. a gate electrode is over the gate dielectric layer.
Inventor(s): Guowei XU of Portland OR US for intel corporation, Feng ZHANG of Hillboro OR US for intel corporation, Chiao-Ti HUANG of Portland OR US for intel corporation, Robin CHAO of Portland OR US for intel corporation, Tao CHU of Portland OR US for intel corporation, Chung-Hsun LIN of Portland OR US for intel corporation, Oleg GOLONZKA of Beaverton OR US for intel corporation, Yang ZHANG of Rio Rancho NM US for intel corporation, Ting-Hsiang HUNG of Beaverton OR US for intel corporation, Chia-Ching LIN of Portland OR US for intel corporation, Anand S. MURTHY of Portland OR US for intel corporation
IPC Code(s): H01L29/66, H01L29/06, H01L29/08, H01L29/423, H01L29/49, H01L29/775
CPC Code(s): H10D64/021
Abstract: integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. for example, an integrated circuit structure includes a stack of horizontal nanowires. a gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. an internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. an external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.
Inventor(s): Roman W. OLAC-VAW of Hillsboro OR US for intel corporation, Walid M. HAFEZ of Portland OR US for intel corporation, Chia-Hong JAN of Portland OR US for intel corporation, Pei-Chi LIU of Portland OR US for intel corporation
IPC Code(s): H01L21/8234, H01L21/28, H01L21/8238, H01L21/84, H01L23/528, H01L27/088, H01L27/12, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H10D84/014
Abstract: non-planar i/o and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar i/o and logic semiconductor devices having different workfunctions on common substrates are described. for example, a semiconductor structure includes a first semiconductor device disposed above a substrate. the first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. the semiconductor structure also includes a second semiconductor device disposed above the substrate. the second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
- Intel Corporation
- G01R31/302
- G01R31/28
- G01R31/303
- H01P3/08
- H01Q9/16
- H04B5/48
- CPC G01R31/3025
- Intel corporation
- G01S13/931
- G01S7/02
- G01S7/35
- G01S13/34
- G01S13/42
- G01S13/72
- G01S13/87
- G01S13/88
- G01S13/89
- CPC G01S13/931
- G06F9/30
- G06F1/16
- G06F7/483
- G06F7/544
- G06F9/38
- G06F17/16
- G06N3/044
- G06N3/045
- G06N3/063
- G06N3/08
- G06N20/00
- G06T15/00
- G09G5/393
- CPC G06F9/3001
- G06F11/10
- G06F3/06
- CPC G06F11/1004
- G06F40/284
- G06F16/28
- CPC G06F40/284
- CPC G06N20/00
- G06T1/20
- G06F9/46
- G06F9/48
- CPC G06T1/20
- G06T5/80
- G02B27/01
- G06T5/50
- CPC G06T5/80
- G06T9/00
- G06N3/047
- G06N3/048
- G06N3/084
- G06N3/088
- H04N19/42
- H04N19/436
- CPC G06T9/002
- G09G3/00
- G09G5/00
- G09G5/14
- CPC G09G3/003
- G11C5/06
- G11C11/4091
- G11C11/419
- CPC G11C5/063
- H01L21/56
- H01L23/00
- H01L23/16
- H01L25/00
- H01L25/065
- H01L25/18
- CPC H01L21/563
- H01L23/15
- H01L21/48
- H01L23/48
- CPC H01L23/15
- H01L23/498
- H01L23/522
- H01L23/538
- H01L23/528
- CPC H01L23/5226
- CPC H01L23/5381
- H01L23/552
- CPC H01L23/562
- H01L23/367
- CPC H01L24/17
- CPC H01L24/81
- CPC H01L25/0655
- H02M3/158
- CPC H01L25/0657
- H03K17/06
- H03K17/687
- CPC H03K17/063
- H03L7/10
- H03L7/081
- H03L7/089
- CPC H03L7/105
- H04L5/00
- H04L27/26
- H04W72/232
- CPC H04L5/0051
- H04L25/03
- H01S5/42
- CPC H04L25/03878
- H04L41/16
- G06N3/04
- G06N5/04
- H04L41/0816
- H04L41/5009
- H04L41/5019
- H04L41/5051
- CPC H04L41/16
- H04L9/40
- CPC H04L63/1425
- H04L67/148
- H04L41/5003
- H04L43/0811
- H04L47/70
- H04L67/00
- H04L67/10
- H04W4/40
- H04W4/70
- CPC H04L67/148
- H04R1/28
- H04R1/02
- H04R7/04
- H04R7/18
- H04R31/00
- CPC H04R1/2834
- H04W72/25
- H04W72/02
- H04W92/18
- CPC H04W72/25
- H01L29/78
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H10D30/794
- H01L21/8234
- H01L27/088
- H01L29/08
- H01L29/778
- CPC H10D62/118
- H01L21/8238
- CPC H10D62/123
- H01L29/45
- H01L21/285
- H01L23/532
- H01L29/40
- CPC H10D62/83
- H01L21/02
- H01L21/033
- H01L21/28
- H01L21/308
- H01L21/311
- H01L21/762
- H01L21/768
- H01L27/02
- H01L29/165
- H01L29/167
- H01L29/417
- H01L29/51
- H10B10/00
- CPC H10D64/017
- H01L29/49
- CPC H10D64/021
- H01L21/84
- H01L27/12
- CPC H10D84/014