Intel Corporation patent applications on March 13th, 2025
Patent Applications by Intel Corporation on March 13th, 2025
Intel Corporation: 26 patent applications
Intel Corporation has applied for patents in the areas of H01L27/092 (3), H01L23/498 (3), H01L29/423 (3), H01L29/06 (3), G06V10/44 (2) G06F1/26 (1), H04L7/0091 (1), H10D62/115 (1), H10B10/12 (1), H05K5/0247 (1)
With keywords such as: gate, device, structure, data, material, memory, signal, circuitry, thickness, and math in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Brandon COURTNEY of Hillsboro OR (US) for intel corporation, Greg LA TOUR of Beaverton OR (US) for intel corporation, Wei-Yi SUNG of New Taipei City (TW) for intel corporation
IPC Code(s): G06F1/26
CPC Code(s): G06F1/26
Abstract: disclosed are techniques for implementing power monitoring in computing systems using current sense devices.
Inventor(s): Shuai Mu of San Diego CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, Pradeep Golconda of El Dorado Hills CA (US) for intel corporation, Srilakshmi Jammula of Rancho Cordova CA (US) for intel corporation, Jiasheng Chen of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/3001
Abstract: an apparatus to facilitate unblocking the integer pipeline during math pipeline phases in a graphics environment is disclosed. the apparatus includes an execution resource comprising: a thread arbiter; a plurality of execution pipeline hardware circuitry comprising a math execution pipeline and an integer execution pipeline to share resources of the thread arbiter; arbitration hardware circuitry to determine whether the math execution pipeline is available for loading math operand data of a math instruction; and a math instruction staging buffer to store the math operand data responsive to the math execution pipeline not being available; wherein the integer execution pipeline is to receive integer operand data for an integer instruction while bypassing the math operand data in the math instruction staging buffer; and wherein the math execution pipeline is to receive, responsive to the math execution pipeline becoming available, the math operand data from the math instruction staging buffer.
20250085977. BOOT FIRMWARE ACCESS_simplified_abstract_(intel corporation)
Inventor(s): Ramamurthy KRITHIVAS of Gilbert AZ (US) for intel corporation, Mahesh S. NATU of Folsom CA (US) for intel corporation, Eswaramoorthi NALLUSAMY of Cedar Park TX (US) for intel corporation, Tiffany J. KASANICKY of Longmont CO (US) for intel corporation
IPC Code(s): G06F9/4401, G06F9/50
CPC Code(s): G06F9/4408
Abstract: examples described herein relate to allocating different lanes of an interface to different processor socket partitions and causing a processor socket partition to boot by accessing firmware by routing a request for the firmware to a device via one or more lanes of the interface and receiving the firmware from the one or more lanes. in some examples, the first host interface circuitry is to route an access to system address space for the first boot firmware to a particular lane of the first host interface circuitry.
Inventor(s): Karthik KUMAR of Chandler AZ (US) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation
IPC Code(s): G06F12/14, G06F12/06, G06F12/0813, G06F12/0891
CPC Code(s): G06F12/1441
Abstract: in an embodiment, network device apparatus is provided that includes packet processing circuitry to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request, and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, may cause transmission of the memory access request to the different device. the memory access request may comprise an identifier of a requester of the memory access request and the identifier may comprise a process address space identifier (pasid).
Inventor(s): Robert Cezary Zaglewski of Folsom CA (US) for intel corporation, Deepak Abraham Mathaikutty of Chandler AZ (US) for intel corporation
IPC Code(s): G06F13/16
CPC Code(s): G06F13/1673
Abstract: an accelerator may include one or more data processing units that perform deep learning operations in neural networks. a data processing unit includes a memory and a compute engine. the memory may include memory banks and clock domain crossing (cdc) buffers. each memory bank may have its own cdc buffer(s). the memory banks may be grouped into bank groups. the memory may also include a group selection module and bank selection modules, each of which is associated with a different bank group. the group selection module may select a bank group for a data transfer request from the compute engine. the bank selection module of the selected bank group may select a memory bank from the selected bank group and store the data transfer request in a cdc buffer of the selected memory bank. the data transfer request may be transmitted to the selected memory bank from the cdc buffer.
Inventor(s): Marcos Carranza of Portland OR (US) for intel corporation, Dario Oliver of Hillsboro OR (US) for intel corporation, Mateo Guzman of Beaverton OR (US) for intel corporation, Mariano Ortega De Mues of Hillsboro OR (US) for intel corporation, Cesar Martinez-Spessot of Hillsboro OR (US) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Carolyn Wyborny of Forest Grove OR (US) for intel corporation, Yashaswini Raghuram Prathivadi Bhayankaram of Portland OR (US) for intel corporation
IPC Code(s): G06F21/57
CPC Code(s): G06F21/575
Abstract: an apparatus includes a host interface, a network interface, and a programmable circuitry communicably coupled to the host interface and the network interface. the programmable circuitry can include one or more processors to implement network interface functionality, and a discrete trusted platform module (dtpm) to enable the one or more processors to establish a secure boot mechanism for the apparatus, wherein the one or more processors are to instantiate a virtual tpm (vtpm) manager that is associated with the dtpm, the vtpm manager to host vtpm instances corresponding to one or more virtualized environments hosted on at least one of the programmable circuitry or a host device communicable coupled to the apparatus.
Inventor(s): Kuan-Yu Chen of Portland OR (US) for intel corporation, Michael Wilmer Leddige of Middleton ID (US) for intel corporation, Diego Mauricio Cortes Hernandez of Hillsboro OR (US) for intel corporation, John Sharpe of Happy Valley OR (US) for intel corporation
IPC Code(s): G06F30/392, G06F30/27, G06F30/3947, G06F115/12, G06F119/10
CPC Code(s): G06F30/392
Abstract: an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify crosstalk between a first signal via and a second signal via on a printed circuit board (pcb) layout, determine an area for placement of a ground via between the first signal via and the second signal via, and classify one or more regions of the pcb layout into at least one of a protective area or a non-protective area based on the area for placement of the ground via.
Inventor(s): Karthik Kumar of Chandler AZ (US) for intel corporation, Marcos Carranza of Portland OR (US) for intel corporation, Patrick Connor of Beaverton OR (US) for intel corporation
IPC Code(s): G06N3/042, G06N3/063
CPC Code(s): G06N3/042
Abstract: deployment of resources utilizing improved mixture of experts processing is described. an example of an apparatus includes one or more network ports; one or more direct memory access (dma) engines; and circuitry for mixture of experts (moe) processing in the network, wherein the circuitry includes at least circuitry to track routing of tokens in moe processing, prediction circuitry to generate predictions regarding moe processing, including predicting future token loads for moe processing, and routing management circuitry to manage the routing of the tokens in moe processing based at least in part on the predictions regarding the moe processing.
Inventor(s): Ehud Cohen of Kiryat Motskin (IL) for intel corporation, Moshe Maor of Kiryat Mozking Z (IL) for intel corporation, Ashutosh Parkhi of Bangalore (IN) for intel corporation, Michael Behar of Zichron Yaakov (IL) for intel corporation, Yaniv Fais of Tel Aviv TA (IL) for intel corporation
IPC Code(s): G06N3/063, G06F16/17, G06F18/21, G06N3/045, G06N3/08, G06V10/44, G06V10/82, G06V10/94
CPC Code(s): G06N3/063
Abstract: a convolutional neural network (cnn) accelerator, including: a cnn circuit for performing a multiple-layer cnn computation, wherein the multiple layers are to receive an input feature according to an input feature map (ifm) and a weight matrix per output feature, wherein an output of a first layer provides an input for a next layer; and a mapping circuit to access a three-dimensional input matrix stored as a z-major matrix; wherein the cnn circuit is to perform an inner-product direct convolution on the z-major matrix, wherein the direct convolution lacks a lowering operation.
Inventor(s): David Moloney of Dublin (IE) for intel corporation
IPC Code(s): G06N3/084, G06F18/214, G06N3/045, G06N3/08, G06V10/44, G06V10/764, G06V10/82, G06V10/94, G06V10/96, H04L67/10
CPC Code(s): G06N3/084
Abstract: systems and methods for distributed training of deep learning models are disclosed. an example local device to train deep learning models includes a reference generator to label input data received at the local device to generate training data, a trainer to train a local deep learning model and to transmit the local deep learning model to a server that is to receive a plurality of local deep learning models from a plurality of local devices, the server to determine a set of weights for a global deep learning model, and an updater to update the local deep learning model based on the set of weights received from the server.
Inventor(s): Chiao-Ti Huang of Portland OR (US) for intel corporation, Tao Chu of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Yang Zhang of Rio Rancho NM (US) for intel corporation, Ting-Hsiang Hung of Beaverton OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation
IPC Code(s): H01L21/762, H01L21/768, H01L23/48, H01L27/088, H01L27/12
CPC Code(s): H01L21/76232
Abstract: techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. a semiconductor device includes a gate structure around or otherwise on a semiconductor region. the gate structure includes a gate dielectric and a gate electrode. the gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. the gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. the lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.
Inventor(s): Man Chun OOH of Menglembu (MY) for intel corporation, Wei Chung LEE of Nibong Tebal (MY) for intel corporation, Yean Ling SOON of Butterworth (MY) for intel corporation, Kor Oon LEE of Simpang Ampat (MY) for intel corporation, Jackson Chung Peng KONG of Tanjung Tokong (MY) for intel corporation, Azniza ABD AZIZ of Perai (MY) for intel corporation, Piyush BHATT of Bengaluru (IN) for intel corporation
IPC Code(s): H01L23/24, H01L23/498
CPC Code(s): H01L23/24
Abstract: the present disclosure is directed to an improved stiffener that has a body that has extension members positioned proximally to the corners of a semiconductor package substrate, and the extension members have bottom extension surfaces that extend beyond a periphery of a bottom surface of the semiconductor package substrate, and the bottom extension surfaces and the bottom surface of the semiconductor package substrate are co-planar. the present disclosure is also directed to a method for forming the improved stiffener with the extension members for a semiconductor package.
Inventor(s): Debendra MALLIK of Chandler AZ (US) for intel corporation, Ravindranath MAHAJAN of Chandler AZ (US) for intel corporation, Digvijay RAORANE of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/367, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/495, H01L23/538
CPC Code(s): H01L23/367
Abstract: a multi-chip unit suitable for chip-level packaging may include multiple ic chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. bonding of the integrated heat spreader to the multiple ic chips may be direct so that no thermal interface material (tim) is needed, resulting in a reduced bond line thickness (blt) and lower thermal resistance. the integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. the redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing ic chips of differing thickness prior to bonding the heat spreader. the sacrificial interposer may be removed to expose the rdl for further interconnection to a substrate without the use of through-substrate vias.
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/498, H01L23/522, H01L23/528
CPC Code(s): H01L23/5381
Abstract: architectures and process flows for an embedded organic bridge component for semiconductor packages. the bulk of the substrate package fabrication can be done using conventional processing steps to meet core geometries (e.g., 9/12) with associated equipment and clean room protocols. separately the organic bridge component is fabricated to embed into the substrate package at a location where the high-speed input/output (i/o) performance and high-density (hd) geometry are required. the organic bridge component is fabricated as required to meet the hd geometry (e.g., 3/3, or less). during assembly, the embedded organic bridge component can be attached into a cavity in the substrate package.
20250088342. TIMESTAMP ALIGNMENT FOR MULTIPLE NODES_simplified_abstract_(intel corporation)
Inventor(s): Mark BORDOGNA of Andover MA (US) for intel corporation, Jonathan A. ROBINSON of Portland OR (US) for intel corporation, Srinivasan S. IYENGAR of Fremont CA (US) for intel corporation
IPC Code(s): H04L7/00
CPC Code(s): H04L7/0091
Abstract: examples described herein relate to a first central processing unit (cpu) node to generate time stamp counter (tsc) values based on a first clock signal and a second cpu node to generate tsc values based on a second clock signal. in some examples, the first cpu node is to determine at least one network timer time stamp based on the tsc values based on the first clock signal and the second cpu node is to determine at least one network timer time stamp based on the tsc values based on the second clock signal. in some examples, determine at least one network timer time stamp based on the tsc values based on the first clock signal is based on (i) a relationship between the first clock signal and a device main timer and (ii) a relationship between a network timer source and the network interface device main timer.
Inventor(s): Shay GUERON of Haifa (IL) for intel corporation, Vlad KRASNOV of Nesher (IL) for intel corporation
IPC Code(s): H04L9/06, G06F9/30, G06F9/38, G06F21/72, G09C1/00
CPC Code(s): H04L9/0643
Abstract: a processor includes a decode unit to decode an sm3 two round state word update instruction. the instruction is to indicate one or more source packed data operands. the source packed data operand(s) are to have eight 32-bit state words a, b, c, d, e, f, g, and hthat are to correspond to a round (j) of an sm3 hash algorithm. the source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the sm3 hash algorithm. an execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. the result packed data operand(s) are to have at least four two-round updated 32-bit state words a, b, e, and f, which are to correspond to a round (j+2) of the sm3 hash algorithm.
Inventor(s): Samuel HUI of Hillsboro OR (US) for intel corporation, Jayant MANGALAMPALLI of Corcoran MN (US) for intel corporation, Fulton LI of Camas WA (US) for intel corporation, Ching Yu LO of Portland OR (US) for intel corporation
IPC Code(s): H04L9/32, H04L9/08
CPC Code(s): H04L9/3234
Abstract: examples described herein relate to an apparatus comprising: multiple processors and circuitry coupled to the multiple processors, wherein at least one of the multiple processors comprises multiple cores and wherein the circuitry is to provide the multiple processors with access to at least two firmware trusted platform module (tpm) instances. at least two firmware tpm instances of the firmware tpm instances is to apply cryptography to store information for platform authentication and wherein the information for platform authentication comprises one or more of: user credentials, passwords, certificates, encryption keys, shared secrets, state information, or hash data.
Inventor(s): Zhijun Lei of Portland OR (US) for intel corporation, Ximin Zhang of San Jose CA (US) for intel corporation, Sang-hee Lee of San Jose CA (US) for intel corporation
IPC Code(s): H04N19/124, H04N19/176, H04N19/18, H04N19/61
CPC Code(s): H04N19/124
Abstract: techniques related to video coding include content adaptive quantization that provides a selection between objective quality and subjective quality delta qp offsets. an adaptive method generates an objective quality delta qp offset that achieves a best peak signal-to-noise ratio (psnr) and/or structural similarity (ssim) score, which refers to a similarity between images. also, the adaptive method generates a subjective quality delta qp offset that achieves the best video multi-method assessment fusion (vmaf) score and/or multi-scale structural similarity (mssim) score.
Inventor(s): Yizhi YAO of Chandler AZ (US) for intel corporation
IPC Code(s): H04W24/10, H04W24/08, H04W48/18
CPC Code(s): H04W24/10
Abstract: this disclosure describes systems, methods, and devices related to optimized delay measurement. a device may receive a request from a consumer to create a trace job for collecting delay-related measurements from a user plane function (upf). the device may request a unified data management (udm) system to create the trace job. the device may receive a response about a result of the trace job creation from the udm. the device may send a response indicating the result of the trace job creation to the consumer.
20250088980. POWER SPECTRAL DENSITY LIMIT FOR 6 GHZ_simplified_abstract_(intel corporation)
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation, Ido OUZIELI of Tel Aviv (IL) for intel corporation, Carlos CORDEIRO of Portland OR (US) for intel corporation, Hassan YAGHOOBI of San Jose CA (US) for intel corporation, Thomas J. KENNEY of Portland OR (US) for intel corporation
IPC Code(s): H04W52/34, H04W52/32, H04W52/36, H04W52/52
CPC Code(s): H04W52/346
Abstract: this disclosure describes systems, methods, and devices related to power spectral density (psd) limit. a device may generate a frame comprising one or more elements to be sent to a first station device, wherein the frame is to be sent using a 6 ghz band. the device may include in the frame, information associated with a psd limit on a per bandwidth size basis of the 6 ghz band. the device may cause to send the frame to the first station device.
20250089092. DEFER SIGNAL DESIGN_simplified_abstract_(intel corporation)
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation, Thomas J. KENNEY of Portland OR (US) for intel corporation
IPC Code(s): H04W74/0816, H04W84/12
CPC Code(s): H04W74/0816
Abstract: this disclosure describes systems, methods, and devices related to defer signal that may be for prioritized access as part of a communication protocol. a device may generate a defer signal to be used with a prioritized access for one or more station devices (stas). the device may include a rate field and a length field in the defer signal. the device may cause to send the defer signal to the one or more stas. the benefit of the disclosed defer signal is that that legacy devices may understand it and defer for a certain duration because of the defer signal, all while keeping the defer signal as small as possible to save time.
20250089156. LOW STRESS THROUGH GLASS VIAS (TGVS)_simplified_abstract_(intel corporation)
Inventor(s): Mohamed R. SABER of College Station TX (US) for intel corporation, Manohar KONCHADY of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja PIETAMBARAM of Chandler AZ (US) for intel corporation, Hiroki TANAKA of Gilbert AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H05K1/02, H01L23/15, H01L23/498, H05K1/03, H05K1/11
CPC Code(s): H05K1/0271
Abstract: embodiments disclosed herein include an apparatus with a glass core and a via. in an embodiment, the apparatus comprises a layer, where the layer is a solid layer of glass. an opening is provided through the layer, and a via is in the opening. the via comprises a first material, where the first material comprises at least one metallic element, and a second material, where the second material comprises carbon.
Inventor(s): Phil Geng of Washougal WA (US) for intel corporation, Dongwang Chen of Shanghai (CN) for intel corporation, Fernando Gonzalez Lenero of Zapopan (MX) for intel corporation, Chuansheng Liu of Shanghai (CN) for intel corporation, Lejie Liu of Portland OR (US) for intel corporation, Ralph V. Miele of Hillsboro OR (US) for intel corporation, Mohanraj Prabhugoud of Hillsboro OR (US) for intel corporation, Sanjoy Saha of Portland OR (US) for intel corporation, David Shia of Portland OR (US) for intel corporation, Jeffory L. Smalley of East Olympia WA (US) for intel corporation, Ke Song of Shanghai (CN) for intel corporation, Meng Wang of Shanghai (CN) for intel corporation, Xiaoning Ye of Portland OR (US) for intel corporation, Juan Zermeno Carriedo of Guadalajara (MX) for intel corporation, Yipeng Zhong of Shanghai (CN) for intel corporation
IPC Code(s): H05K5/02, H05K5/04
CPC Code(s): H05K5/0247
Abstract: composite backplate architectures for backside power delivery and associated methods are disclosed. an example backplate includes a first layer including a first material, and a second layer attached to the first layer. the second layer includes a second material different from the first material. the example backplate further includes a bus bar attached to the first layer.
Inventor(s): Meenakshisundaram Ramanathan of Hillsboro OR (US) for intel corporation, Krishna Ganesan of Portland OR (US) for intel corporation, John Crocker of Hillsboro OR (US) for intel corporation, Akitomo Matsubayashi of Beaverton OR (US) for intel corporation, Jianhua Yin of Portland OR (US) for intel corporation, Reken Patel of Portland OR (US) for intel corporation
IPC Code(s): H10B10/00, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/778
CPC Code(s): H10B10/12
Abstract: integrated circuit (ic) structures that include static random-access memory (sram) and that are fabricated using gate contact patterning after source/drain (s/d) metallization are disclosed. an example ic structure includes a transistor comprising an s/d region and a gate electrode material, an s/d contact in electrical contact with the s/d region, and a gate contact in electrical contact with the gate electrode material. the s/d contact includes a first electrically conductive material, the gate contact includes a second electrically conductive material, and a portion of the second electrically conductive material is in electrical contact with a portion of the first electrically conductive material, wherein an average grain size or orientation in the portion of the first electrically conductive material is different from an average grain size or orientation in the portion of the second electrically conductive material.
Inventor(s): Ting-Hsiang Hung of Beaverton OR (US) for intel corporation, Yang Zhang of Rio Rancho NM (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Tao Chu of Portland OR (US) for intel corporation, Chiao-Ti Huang of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L27/092, H01L29/423, H01L29/778, H01L29/786
CPC Code(s): H10D62/115
Abstract: techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. in an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. a through-gate structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. the through-gate structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). in either case, an airgap spacer exists between the through-gate structure and the gate structure.
Inventor(s): Rahul RAMASWAMY of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation, Walid M. HAFEZ of Portland OR (US) for intel corporation, Hsu-Yu CHANG of Hillsboro OR (US) for intel corporation, Jeong Dong KIM of Scappoose OR (US) for intel corporation, Scott MOKLER of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. for example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. the nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. a dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.
- Intel Corporation
- G06F1/26
- CPC G06F1/26
- Intel corporation
- G06F9/30
- G06F9/38
- CPC G06F9/3001
- G06F9/4401
- G06F9/50
- CPC G06F9/4408
- G06F12/14
- G06F12/06
- G06F12/0813
- G06F12/0891
- CPC G06F12/1441
- G06F13/16
- CPC G06F13/1673
- G06F21/57
- CPC G06F21/575
- G06F30/392
- G06F30/27
- G06F30/3947
- G06F115/12
- G06F119/10
- CPC G06F30/392
- G06N3/042
- G06N3/063
- CPC G06N3/042
- G06F16/17
- G06F18/21
- G06N3/045
- G06N3/08
- G06V10/44
- G06V10/82
- G06V10/94
- CPC G06N3/063
- G06N3/084
- G06F18/214
- G06V10/764
- G06V10/96
- H04L67/10
- CPC G06N3/084
- H01L21/762
- H01L21/768
- H01L23/48
- H01L27/088
- H01L27/12
- CPC H01L21/76232
- H01L23/24
- H01L23/498
- CPC H01L23/24
- H01L23/367
- H01L21/48
- H01L21/56
- H01L23/00
- H01L23/31
- H01L23/495
- H01L23/538
- CPC H01L23/367
- H01L23/522
- H01L23/528
- CPC H01L23/5381
- H04L7/00
- CPC H04L7/0091
- H04L9/06
- G06F21/72
- G09C1/00
- CPC H04L9/0643
- H04L9/32
- H04L9/08
- CPC H04L9/3234
- H04N19/124
- H04N19/176
- H04N19/18
- H04N19/61
- CPC H04N19/124
- H04W24/10
- H04W24/08
- H04W48/18
- CPC H04W24/10
- H04W52/34
- H04W52/32
- H04W52/36
- H04W52/52
- CPC H04W52/346
- H04W74/0816
- H04W84/12
- CPC H04W74/0816
- H05K1/02
- H01L23/15
- H05K1/03
- H05K1/11
- CPC H05K1/0271
- H05K5/02
- H05K5/04
- CPC H05K5/0247
- H10B10/00
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/08
- H01L29/423
- H01L29/66
- H01L29/778
- CPC H10B10/12
- H01L29/786
- CPC H10D62/115
- H01L29/775
- CPC H10D62/121