Intel Corporation patent applications on January 9th, 2025
Patent Applications by Intel Corporation on January 9th, 2025
Intel Corporation: 24 patent applications
Intel Corporation has applied for patents in the areas of H01L25/065 (3), H01L23/538 (3), H01L23/00 (3), H05K1/18 (2), H01L25/00 (2) H01L23/5381 (2), A61B5/4884 (1), H01L21/67288 (1), H04W76/10 (1), H04W12/12 (1)
With keywords such as: device, circuit, link, wlan, apparatus, data, based, integrated, example, and interface in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Jonathan Lee of San Carlos CA (US) for intel corporation, Marco Della Torre of San Francisco CA (US) for intel corporation
IPC Code(s): A61B5/00, A61B5/0205, A61B5/024, A61B5/11
CPC Code(s): A61B5/4884
Abstract: a wearable device measures heart rate recovery of a user in a non-clinical setting. the wearable device comprises a heart rate detector configured to detect heart rate data of the user, an activity sensor configured to detect motion of the user, and a processor. the processor is configured to identify a start of an activity by the user using the motion detected by the activity sensor. responsive to detecting the start of the activity, the processor monitors the motion detected by the activity sensor to identify an end of the activity. a regression analysis is performed on heart rate data detected by the heart rate detector during a period of time after the end of the activity, and the heart rate recovery of the user is determined using the regression analysis.
Inventor(s): David Daniel Wieneke of San Tan Valley AZ (US) for intel corporation, Izhak Givoni of Chandler AZ (US) for intel corporation, Sriram Chandra Kumar of Gilbert AZ (US) for intel corporation
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2863
Abstract: methods and apparatus to disengage a test head from an integrated circuit (ic) device are disclosed. an example apparatus comprises a test head to thermally interface with an ic device, a mounting piece to be coupled to the test head, and a push off tab to be mounted to the mounting piece, the push off tab including an arm to extend underneath the test head, the arm to contact the ic device before the test head is to contact the ic device.
20250012874. D2D SPATIAL UNDERSTANDING WITH ELECTRIC MAGNETS_simplified_abstract_(intel corporation)
Inventor(s): Ke HAN of Shanghai (CN) for intel corporation, Xiaodong Cai of Shanghai (CN) for intel corporation, Shouwei Sun of Shanghai (CN) for intel corporation, Hemin Han of Shanghai (CN) for intel corporation, Lu Wang of Shanghai (CN) for intel corporation
IPC Code(s): G01R33/02
CPC Code(s): G01R33/02
Abstract: the present application provides a system including a plurality of components to be mounted to a first device in a preset layout and generate a magnetic field; a magnetometer integrated with a second device to detect the magnetic field to generate reading data associated with the magnetic field at the second device; and a processor configured to determine a position of the second device relative to the first device based on the reading data and the preset layout of the plurality of components.
Inventor(s): Igor Tatourian of Fountain Hills AZ (US) for intel corporation, Hassnaa Moustafa of San Jose CA (US) for intel corporation, David John Zage of Fremont CA (US) for intel corporation
IPC Code(s): G05D1/00, B25J9/16, B60W30/09
CPC Code(s): G05D1/0214
Abstract: apparatuses, storage media and methods associated with cognitive robot systems, such as adas for cad vehicles, are disclosed herein. in some embodiments, an apparatus includes emotional circuitry to receive stimuli for a robot integrally having the robotic system, process the received stimuli to identify potential adversities, and output information describing the identified potential adversities; and thinking circuitry to receive the information describing the identified potential adversities, process the received information describing the identified potential adversities to determine respective fear levels for the identified potential adversities in view of a current context of the robot, and generate commands to the robot to respond to the identified potential adversities, based at least in part on the determined fear levels for the identified potential adversities. other embodiments are also described and claimed.
Inventor(s): Sean J. W. Lawrence of Bangalore (IN) for intel corporation
IPC Code(s): G06F3/147, G06F3/01
CPC Code(s): G06F3/147
Abstract: systems and methods for controlling flexible displays are disclosed herein. an example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to determine a distance of a user relative to a display screen based on outputs of a sensor, the sensor in communication with one or more of the at least one processor circuit; determine a curvature radius of the display screen based on the user distance; and cause an actuator to adjust a curvature of the display screen based on the curvature radius.
20250013493. FREQUENCY SCALING IN MULTI-TENANT ENVIRONMENTS_simplified_abstract_(intel corporation)
Inventor(s): Chris MACNAMARA of Limerick (IE) for intel corporation, John J. BROWNE of Limerick (IE) for intel corporation, Nilanjan PALIT of Northborough MA (US) for intel corporation, Chetan HIREMATH of Portland OR (US) for intel corporation, Rory SEXTON of Fermoy (IE) for intel corporation, Conor WALSH of Tullamore (IE) for intel corporation, Kevin LAATZ of Caherconlish (IE) for intel corporation, Andriy GLUSTSOV of San Diego CA (US) for intel corporation, Peter McCARTHY of Ennis (IE) for intel corporation, Katelyn DONNELLAN of Kilkishen (IE) for intel corporation, Vishal DEEP AJMERA of Bangalore (IN) for intel corporation, David HUNT of Meelick (IE) for intel corporation, Gordon NOONAN of Limerick (IE) for intel corporation
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4881
Abstract: examples described herein relate to circuitry to: monitor utilization data for a plurality of processes; determine one or more priority levels associated with at least one of the plurality of processes based on policy parameters; and adjust a frequency of operation of the interface circuitry based on the monitored utilization data and the determined priority levels of the processes. in some examples, adjust the frequency of operation of the interface circuitry is to prioritize frequency of operation requested by a higher priority workload over a frequency of operations requested by a lower priority workload.
20250013507. TECHNOLOGIES FOR COMPUTER POWER MANAGEMENT_simplified_abstract_(intel corporation)
Inventor(s): Chris M. MacNamara of Ballyclough (IE) for intel corporation, John J. Browne of Limerick (IE) for intel corporation, Przemyslaw J. Perycz of Sopot (PL) for intel corporation, Pawel S. Zak of Gdansk (PL) for intel corporation, Reshma Pattan of Tuam (IE) for intel corporation
IPC Code(s): G06F9/50, G06F1/26, G06F9/48
CPC Code(s): G06F9/5094
Abstract: techniques for computer power management are disclosed. in one embodiment, a data center includes several compute nodes and a power management node. power telemetry data is gathered at each of the compute nodes and sent to the power management node. the power management node analyzes the telemetry data, such as by applying filtering to identify certain metrics. the power management node may use rules to analyze the telemetry data and determine whether power management actions should be performed. the power management node may instruct the compute node to, e.g., change a power state of a processor or processor core. in some embodiments, cores may be managed by an orchestrator, and the orchestrator may identify cores to be placed in high-power and low-power states, as appropriate.
Inventor(s): Debendra Das Sharma of Saratoga CA (US) for intel corporation
IPC Code(s): G06F11/263, G06F11/10, G06F11/22, G06F11/30, G06F13/40
CPC Code(s): G06F11/263
Abstract: systems and devices can include an error injection register comprising error injection parameter information. the systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (flit); and protocol stack circuitry to transmit the flit comprising the error on a multilane link. the injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.
Inventor(s): Emiliano Morini of Folsom CA (US) for intel corporation, Samuel Coward of London (GB) for intel corporation, Theo Drane of El Dorado Hills CA (US) for intel corporation, George A. Constantinides of Santa Clara CA (US) for intel corporation, Jordan Schmerge of Folsom CA (US) for intel corporation
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3624
Abstract: described herein are techniques for automatic bug fixing of implementation rtl code to transform the code into rtl code that is closer to a reference specification. two designs, such as a known-good reference specification and an updated implementation, can be compared in functionality via an e-graph. rewrites are applied from the direction of the specification code to find a design that is equivalent to the specification, but syntactically close to the current implementation.
20250013600. LINK LAYER-PHY INTERFACE ADAPTER_simplified_abstract_(intel corporation)
Inventor(s): Narasimha Lanka of Dublin CA (US) for intel corporation, Swadesh Choudhary of Mountain View CA (US) for intel corporation, Mahesh Wagh of Portland OR (US) for intel corporation, Lakshmipriya Seshan of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06F13/42, G06F13/28
CPC Code(s): G06F13/4286
Abstract: an adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (phy) device. the phy device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the phy device. the second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. the adapter is to implement a logical phy for the link.
Inventor(s): Pradeep M. Pappachan of Tualatin OR (US) for intel corporation, Luis S. Kida of Beaverton OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F21/60, G06F12/1009, G06F12/14, G06F21/78, G06T1/20, H04L9/14
CPC Code(s): G06F21/602
Abstract: embodiments are directed to trusted local memory management in a virtualized gpu. an embodiment of an apparatus includes one or more processors including a trusted execution environment (tee); a gpu including a trusted agent; and a memory, the memory including gpu local memory, the trusted agent to ensure proper allocation/deallocation of the local memory and verify translations between graphics physical addresses (pas) and pas for the apparatus, wherein the local memory is partitioned into protection regions including a protected region and an unprotected region, and wherein the protected region to store a memory permission table maintained by the trusted agent, the memory permission table to include any virtual function assigned to a trusted domain, a per process graphics translation table to translate between graphics virtual address (va) to graphics guest pa (gpa), and a local memory translation table to translate between graphics gpas and pas for the local memory.
Inventor(s): Kuba Lopatka of Gdansk (PL) for intel corporation
IPC Code(s): G10L25/30, G10L25/51
CPC Code(s): G10L25/30
Abstract: systems and methods to trigger llm inference based on the presences of relevant audio, such as a keyword or sound event of interest. a detection head receives acoustic embeddings from an audio encoder and determines whether the audio stream includes relevant sounds (e.g., a selected audio trigger). when the audio stream does not include relevant sounds, multimodal llm inference is bypassed, thereby saving power and protecting privacy. when relevant sounds are detected in the audio stream by the detector, the acoustic embeddings from the audio encoder are transmitted to the multimodal llm, which proceeds to perform inference on the acoustic embeddings. the audio encoder and/or detection head can be offloaded in the hardware and implemented before the multimodal llm in the hardware pipeline, while the multimodal llm can be implemented in a neural processing unit.
Inventor(s): Chrystian Mauricio Posada Arbelaez of Portland OR (US) for intel corporation, Grace Mei Ee Khoo of Portland OR (US) for intel corporation, Bathiya Prashan Bandara Senevirathna of Hillsboro OR (US) for intel corporation, Binh Nguyen of Cupertino CA (US) for intel corporation
IPC Code(s): H01L21/67, G06T7/00, G06T7/70
CPC Code(s): H01L21/67288
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to improve inspection techniques for integrated circuits with backside power delivery. an example disclosed apparatus includes at least one programmable circuit to at least one of instantiate or execute the machine readable instructions to modulate first and second bitlines for a bitcell in a memory array of an integrated circuit between first and second voltages at a frequency for a period of time, the modulating of the first and second bitlines to produce a periodic heat signal in the integrated circuit, cause a thermal imaging sensor to capture a series of images of the integrated circuit during the period of time, and determine a location of a defect in the integrated circuit based on the series of images.
Inventor(s): Kyle Jordan Arrington of Gilbert AZ (US) for intel corporation, Prabhakar Subrahmanyam of San Jose CA (US) for intel corporation, Steven Adam Klein of Chandler AZ (US) for intel corporation, Kelly Porter Lofgreen of Phoenix AZ (US) for intel corporation, Joseph Blane Petrini of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/473, H01L23/40, H01L23/42, H01R12/85, H01R13/52
CPC Code(s): H01L23/4735
Abstract: systems, apparatus, articles of manufacture, and methods to improve thermal dissipation and mechanical loading of integrated circuit packages are disclosed. an example apparatus includes: a socket to receive an integrated circuit package; and a plate to apply a load on the integrated circuit package towards the socket. the plate includes an internal channel to carry a coolant through the plate. the liquid coolant is to facilitate cooling of the integrated circuit package.
Inventor(s): Eric ERIKE of Mesa AZ (US) for intel corporation, Anikki GIESSLER of Tempe AZ (US) for intel corporation, Zhichao ZHANG of Chandler AZ (US) for intel corporation, Srikant NEKKANTY of Chandler AZ (US) for intel corporation, Saikat MONDAL of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01R12/52
CPC Code(s): H01L23/49838
Abstract: embodiments disclosed herein include a liquid metal interposer. in an embodiment, the liquid metal interposer comprises a substrate with a first opening in the substrate and a second opening in the substrate. in an embodiment, a channel is between the first opening and the second opening. in an embodiment, the channel fluidically couples the first opening to the second opening.
Inventor(s): Srinivas PIETAMBARAM of Gilbert AZ (US) for intel corporation, Rahul MANEPALLI of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L25/00, H01L25/065
CPC Code(s): H01L23/5381
Abstract: embodiments disclosed herein include electronic packages and methods of forming such packages. in an embodiment, a microelectronic device package may include a redistribution layer (rdl) and an interposer over the rdl. in an embodiment, a glass core may be formed over the rdl and surround the interposer. in an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. in an embodiment, the plurality of dies are communicatively coupled with the interposer.
Inventor(s): Yueli LIU of Gilbert AZ (US) for intel corporation, Qinglei ZHANG of Chandler AZ (US) for intel corporation, Amanda E. SCHUCKMAN of Scottsdale AZ (US) for intel corporation, Rui ZHANG of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/532, H01L25/065, H01L25/18, H05K1/18, H05K3/34
CPC Code(s): H01L23/5381
Abstract: embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. in one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. the bridge may be configured to route electrical signals between two dies. an interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. the first conductive material, the second conductive material, and the third conductive material may have different chemical composition. other embodiments may be described and/or claimed.
Inventor(s): Bhaskar Jyoti Krishnatreya of Beaverton OR (US) for intel corporation, Nagatoshi Tsunoda of Tsukuba (JP) for intel corporation, Shawna M. Liff of Scottsdale AZ (US) for intel corporation, Sairam Agraharam of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/31, H01L23/367, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L24/08
Abstract: disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. for example, in some embodiments, a microelectronic component may include a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface, the trench having a depth; and a burr in the trench having a height that is less than the depth of the trench.
Inventor(s): Landon HANKS of Milwaukie OR (US) for intel corporation
IPC Code(s): H01R13/24, G06F1/18, H01R12/71, H05K3/34, H05K7/10
CPC Code(s): H01R13/2442
Abstract: small form factor shunted socket pins and configurations for improved single ended signaling. the shunted socket pin includes a cantilevered spring member coupled to an upper portion of a body having a lower lever directed in a first direction coupled to an upper lever directed in a second direction to form a nose, the cantilevered spring member folding back on itself, and a shunting lever, coupled to the upper portion of the body. the body is coupled to a base, such as a solder ball. when the socket pin is compressed, a portion of the shunting lever is in contact with a portion of the cantilevered member, creating a shunted (and shorter) electrical path between contact pads on a socketed ic, soc, or sop and a contact pad or via on a pcb to which the solder ball is coupled.
20250015967. CONFIGURATION SCHEME FOR LINK ESTABLISHMENT_simplified_abstract_(intel corporation)
Inventor(s): Istvan KOVACS of Hillsboro OR (US) for intel corporation, Samuel A. JOHNSON of Portland OR (US) for intel corporation, Jonathan D. TURPEN of Hillsboro OR (US) for intel corporation, Israel BEN SHAHAR of Mevaseret Zion (IL) for intel corporation
IPC Code(s): H04L5/14, H04L1/00, H04L27/26, H04W28/18, H04W76/18
CPC Code(s): H04L5/1438
Abstract: examples described herein relate to a physical layer interface device with an interface to a medium and a link controller. the link controller can attempt to form a link with another device through the interface. based on failure to achieve link using a last successful configuration, an attempt to form a link with another device through the interface can include interleaving use of an ieee 802.3 compatible auto-negotiation process with at least one attempt to form a link using a non-auto-negotiated mode. based on failure to achieve link with the another device using any available link speed mode and forward error correction (fec) scheme, an attempt is made using ieee 802.3 compatible auto-negotiation without use of next pages.
Inventor(s): Robert VAUGHN of Portland OR (US) for intel corporation, John HANSEN of Forest Grove OR (US) for intel corporation
IPC Code(s): H04L9/08
CPC Code(s): H04L9/0819
Abstract: provided is a method for detecting an artificial intelligence (ai) agent of an application in a network. in this method, the varieties of a plurality of outputs of the application may be determined, where the outputs are respectively corresponding to a plurality of identical inputs provided to the application. furthermore, the method may detect, based on the varieties of the plurality of outputs, the ai agent of the application, wherein the ai agent comprises an ai model providing ai-based resource information to the application to generate the plurality of outputs.
Inventor(s): Markus Dominik Mueck of Unterhaching (DE) for intel corporation
IPC Code(s): H04W12/12, H04B17/24
CPC Code(s): H04W12/12
Abstract: the present disclosure is related to reconfigurable radio equipment and edge computing, and in particular, to technologies for cyber security and radio equipment supporting certain features ensuring protection from fraud, and testing interfaces related to reconfigurable radio equipment. other embodiments may be described and/or claimed.
Inventor(s): Laurent Cariou of Milizac (FR) for intel corporation, Thomas Kenney of Portland OR (US) for intel corporation
IPC Code(s): H04W76/10, H04W24/02, H04W84/12
CPC Code(s): H04W76/10
Abstract: for example, an apparatus may include logic and circuitry configured to cause a parameter-setting server to establish a connection with a wireless local area network (wlan) station (sta). for example, the parameter-setting server may be configured to send wlan parameter-setting information to the wlan sta via the connection with the wlan sta. for example, the wlan parameter-setting information may be configured to indicate a setting of one or more wlan parameters to be implemented by the wlan sta for communication in a wlan. for example, the wlan sta may be configured to process the wlan parameter-setting information from the parameter-setting server to identify the setting of the one or more wlan parameters to be implemented by the wlan sta. for example, the wlan sta may be configured to communicate one or more transmissions in the wlan, for example, according to the setting of the one or more wlan parameters.
Inventor(s): Min Suet Lim of Gelugor (MY) for intel corporation, Luis Alvarez Mata of Paraíso (CR) for intel corporation, Jia Yan Go of Kulim (MY) for intel corporation, Smit Kapila of Bangalore (IN) for intel corporation, Chaitra Kotehal of Bengaluru (IN) for intel corporation, Jeff Ku of Taipei (TW) for intel corporation, Shantanu Kulkarni of Hillsboro OR (US) for intel corporation, Kari Mansukoski of Hillsboro OR (US) for intel corporation, Surya Pratap Mishra of Portland OR (US) for intel corporation
IPC Code(s): H05K1/18
CPC Code(s): H05K1/183
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for inductors of voltage regulators that are built into and/or around mounting holes of a printed circuit board. an example apparatus includes a printed circuit board that includes a plurality of layers and a mounting hole extending through the plurality of layers, and an inductor at least partially in the mounting hole between two or more of the plurality of layers.
- Intel Corporation
- A61B5/00
- A61B5/0205
- A61B5/024
- A61B5/11
- CPC A61B5/4884
- Intel corporation
- G01R31/28
- CPC G01R31/2863
- G01R33/02
- CPC G01R33/02
- G05D1/00
- B25J9/16
- B60W30/09
- CPC G05D1/0214
- G06F3/147
- G06F3/01
- CPC G06F3/147
- G06F9/48
- CPC G06F9/4881
- G06F9/50
- G06F1/26
- CPC G06F9/5094
- G06F11/263
- G06F11/10
- G06F11/22
- G06F11/30
- G06F13/40
- CPC G06F11/263
- G06F11/36
- CPC G06F11/3624
- G06F13/42
- G06F13/28
- CPC G06F13/4286
- G06F21/60
- G06F12/1009
- G06F12/14
- G06F21/78
- G06T1/20
- H04L9/14
- CPC G06F21/602
- G10L25/30
- G10L25/51
- CPC G10L25/30
- H01L21/67
- G06T7/00
- G06T7/70
- CPC H01L21/67288
- H01L23/473
- H01L23/40
- H01L23/42
- H01R12/85
- H01R13/52
- CPC H01L23/4735
- H01L23/498
- H01R12/52
- CPC H01L23/49838
- H01L23/538
- H01L21/48
- H01L21/56
- H01L21/683
- H01L23/00
- H01L23/31
- H01L25/00
- H01L25/065
- CPC H01L23/5381
- H01L23/532
- H01L25/18
- H05K1/18
- H05K3/34
- H01L23/367
- CPC H01L24/08
- H01R13/24
- G06F1/18
- H01R12/71
- H05K7/10
- CPC H01R13/2442
- H04L5/14
- H04L1/00
- H04L27/26
- H04W28/18
- H04W76/18
- CPC H04L5/1438
- H04L9/08
- CPC H04L9/0819
- H04W12/12
- H04B17/24
- CPC H04W12/12
- H04W76/10
- H04W24/02
- H04W84/12
- CPC H04W76/10
- CPC H05K1/183