Intel Corporation patent applications on January 16th, 2025
Patent Applications by Intel Corporation on January 16th, 2025
Intel Corporation: 26 patent applications
Intel Corporation has applied for patents in the areas of H01L29/66 (4), H01L21/8238 (3), H01L21/768 (3), H01L27/092 (3), H01L29/78 (3) G02B6/42 (1), H01L27/0924 (1), H05K7/20327 (1), H05K7/10 (1), H04W76/10 (1)
With keywords such as: structure, die, layer, surface, gate, dielectric, example, circuit, apparatus, and substrate in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Abhishek A. Sharma of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Mauro J. Kobrinsky of Portland OR (US) for intel corporation
IPC Code(s): G02B6/42, G02B6/12, G02B6/13, H01L25/16, H10B41/00
CPC Code(s): G02B6/42
Abstract: microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. as used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two ic structures fabricated using different manufacturers, materials, or manufacturing techniques. before bonding, at least one ic structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. one or more additional electronic and/or photonic components may be provided in one or more of these ic structures after bonding. for example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded ic structures.
Inventor(s): Todd R. COONS of Gilbert AZ (US) for intel corporation, Michael RUTIGLIANO of Chandler AZ (US) for intel corporation, Joe F. WALCZYK of Tigard OR (US) for intel corporation, Abram M. DETOFSKY of Tigard OR (US) for intel corporation
IPC Code(s): G02B6/42, G02B6/12, G02B6/30, G02B6/34, H01L23/367, H01L25/075, H01L33/58, H01L33/62, H04B10/40
CPC Code(s): G02B6/4201
Abstract: embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. the top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. the base die may be referred to as the photonics die. a system-on-a-chip (soc) may be electrically coupled with and stacked onto the top of the photonics die. other embodiments may be described and/or claimed.
Inventor(s): Sangeeta Manepalli of Chandler AZ (US) for intel corporation, Chia-Hung S. Kuo of Folsom CA (US) for intel corporation, Venkateshan Udhayan of Portland OR (US) for intel corporation, Stanley Baran of Chandler AZ (US) for intel corporation, Jason Tanner of Folsom CA (US) for intel corporation, Michael Rosenzweig of Queen Creek AZ (US) for intel corporation
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4881
Abstract: methods, systems, articles of manufacture and apparatus are disclosed to generate dynamic computing resource schedules. an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to determine a first schedule policy based on (a) an interval parameter and (b) an energy budget parameter, the first schedule policy to include a first instantiation window. the example instructions further determine performance metrics of a target processor circuit based on instantiating a workload with the first schedule policy, and generate a second schedule policy based on the performance metrics of the target processor circuit, the second schedule policy to include a second instantiation window, the second instantiation window including a modification relative to the first instantiation window.
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation
IPC Code(s): G06F12/0815, G06F3/06
CPC Code(s): G06F12/0815
Abstract: disclosed examples include accessing a memory access command, the memory access command identifying a memory address; determining a remote node that provides access to the memory address in a pooled memory shared by multiple nodes; and causing tunneling of the memory access command to the remote node to service the memory access command.
20250021621. BIT MATRIX MULTIPLICATION_simplified_abstract_(intel corporation)
Inventor(s): Dmitry Y. Babokin of Santa Clara CA (US) for intel corporation, Kshitij A. Doshi of Tempe AZ (US) for intel corporation, Vadim Sukhomlinov of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F17/16, G06F7/544, G06F9/30
CPC Code(s): G06F17/16
Abstract: detailed are embodiments related to bit matrix multiplication in a processor. for example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of s-bit elements of the identified first source bit matrix with s-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein s indicates a plural bit size is described.
Inventor(s): Aviv Barkai of Haifa (IL) for intel corporation, Benjamin Zeltser of Haifa (IL) for intel corporation, Elad Peer of Yokneam Ilit (IL) for intel corporation
IPC Code(s): G06F21/12
CPC Code(s): G06F21/125
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to prevent attacks on software. an example non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least: insert a plurality of code blocks into an input code; insert replacement manager instructions into the input code, the replacement manager instructions to, when executed: determine a subset of the plurality of code blocks; and insert the subset of the plurality of code blocks into memory for execution during execution of the input code.
Inventor(s): Vinay Joshi of Nanded (IN) for intel corporation, Om Ji Omer of Bangalore (IN) for intel corporation, Prashant Laddha of Bangalore (IN) for intel corporation, Shambhavi Sinha of Bangalore (IN) for intel corporation
IPC Code(s): G06N3/086
CPC Code(s): G06N3/086
Abstract: systems, apparatus, articles of manufacture, and methods for quality and capacity-aware grouped query attention are disclosed. to accomplish such groupings, example instructions cause a machine to create a plurality of groups of query heads present in a key value cache using an evolutionary algorithm based on at least two objectives, quantify an amount of error introduced by a first group of query heads in the plurality of groups of query heads, and retain the query heads of the first group of query heads in a non-grouped arrangement when the error meets an error threshold.
Inventor(s): Sahar Daraeizadeh of Bellevue WA (US) for intel corporation, Todor Mladenov of Portland OR (US) for intel corporation, Xiang Zou of Portland OR (US) for intel corporation, Anne Matsuura of Portland OR (US) for intel corporation
IPC Code(s): G06N10/20
CPC Code(s): G06N10/20
Abstract: apparatus and method for a quantum control processor. for example, one embodiment of a qcp comprises: instruction fetch logic to fetch instructions from a memory, the instructions including quantum instructions; decode logic to decode the quantum instructions into a first plurality of quantum microoperations; translation logic translate the first plurality of quantum microoperations into a second plurality of quantum microoperations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor; and issue logic to synchronously issue the second plurality of quantum microoperations in parallel to the plurality of quantum controller cores.
Inventor(s): Binbin Wang of Portland OR (US) for intel corporation, Hyun Woo Shim of Beaverton OR (US) for intel corporation, Garrett Martin Mitchell of Pomona CA (US) for intel corporation
IPC Code(s): G06T7/00, G06T3/02, G06T7/33, G06T7/73
CPC Code(s): G06T7/001
Abstract: methods and apparatus for semiconductor die fault analysis are disclosed. an example apparatus comprises interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify a location of a reference feature on a semiconductor die within a first image of the semiconductor die, the first image containing a region of interest on the semiconductor die adjacent to the reference feature, transform a baseline pattern of the semiconductor die to align a location of a baseline feature in the baseline pattern with the location of the reference feature in the first image, and determine a location of the region of interest in the first image based on the transformed baseline pattern.
Inventor(s): Santhosh Kumar Chandrakanthan of Bangalore (IN) for intel corporation
IPC Code(s): G11C29/12, G11C29/36
CPC Code(s): G11C29/12015
Abstract: an example integrated circuit disclosed herein includes a first die including first microbumps associated with a source-synchronous data interface of a three-dimensional (3d) die stack, a first one of the first microbumps in circuit with a clock output of the first die, a second one of the first microbumps in circuit with a data output of the first die, the clock output and the data output associated with a transmitter side of the source-synchronous data interface. the example integrated circuit also includes a second die including second microbumps associated with the source-synchronous data interface of the 3d die stack, a first one of the second microbumps in circuit with a clock input of the second die, a second one of the second microbumps in circuit with a data input of the second die, the clock input and the data input associated with a receiver side of the source-synchronous data interface.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jason Gamba of Gilbert AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Robert May of Chandler AZ (US) for intel corporation, Benjamin Taylor Duong of Phoenix AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Whitney Bryks of Tempe AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/08
CPC Code(s): H01L23/49827
Abstract: methods and apparatus for edge protected glass cores are disclosed herein. an example package substrate includes a first glass layer including a first surface, a second surface opposite the first surface, and first lateral surfaces extending between the first and second surfaces, the first glass layer having a first via extending between the first surface and the second surface; and a dielectric material in contact with the first surface of the first glass layer and in contact with the first lateral surfaces of the first glass layer.
Inventor(s): William J. LAMBERT of Chandler AZ (US) for intel corporation, Sri Chaitra Jyotsna CHAVALI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/64, H01F27/28, H01F27/32, H01F41/04, H01F41/12, H01L21/48, H01L23/00, H01L23/498
CPC Code(s): H01L23/645
Abstract: embodiments include inductors and methods to form the inductors. an inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. the inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. the inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (pth) vias in the dielectric and substrate layers. the pth vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the pth vias. the magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.
20250022845. MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Adel A. Elsherbini of Tempe AZ (US) for intel corporation, Feras Eid of Chandler AZ (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation, Shawna M. Liff of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L25/00, H01L25/18
CPC Code(s): H01L25/0652
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.
Inventor(s): Andy Chih-Hung Wei of Yamhill OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Mauro J. Kobrinsky of Portland OR (US) for intel corporation, Guillaume Bouche of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L23/522, H01L29/06, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: methods for fabricating a transistor arrangement of an ic structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. an example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. a nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. the nanoribbons are processed to form s/d regions and gate stacks for future transistors. the dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.
Inventor(s): Sairam SUBRAMANIAN of Portland OR (US) for intel corporation, Walid M. HAFEZ of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/768, H01L21/8238, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: self-aligned gate endcap (sage) architectures having gate contacts, and methods of fabricating sage architectures having gate contacts, are described. in an example, an integrated circuit structure includes a gate structure over a semiconductor fin. a gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. a trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. a local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.
Inventor(s): Brandon Marin of Gilbert AZ (US) for intel corporation, Khaled Ahmed of San Jose CA (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L27/15
CPC Code(s): H01L27/156
Abstract: techniques and mechanisms for a micro-led (or “uled”) device to facilitate communication of an optical signal which is propagated via a transparent substrate structure. in an embodiment, one or more recess structures are formed in a side of a transparent substrate structure, such as a glass core of a package substrate. a uled structure extends partially through the transparent substrate structure in a first recess structure, and is oriented to transmit or receive an optical signal via the transparent substrate. in another embodiment, the uled structure is coupled to integrated circuitry which provides functionality to operate the uled structure, at different times, in either one of an optical signal receiver mode or an optical signal transmitter mode.
Inventor(s): Seung Hoon SUNG of Portland OR (US) for intel corporation, Tristan TRONIC of Aloha OR (US) for intel corporation, Szuya S. LIAO of Portland OR (US) for intel corporation, Jack T. KAVALIEROS of Portland OR (US) for intel corporation
IPC Code(s): H01L29/49, H01L21/28, H01L21/768, H01L21/8234, H01L21/8238, H01L23/535, H01L27/088, H01L27/092, H01L29/66
CPC Code(s): H01L29/4983
Abstract: self-aligned gate endcap (sage) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (sage) architectures with reduced or removed caps, are described. in an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. a second gate electrode is over a second semiconductor fin. a gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. a local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.
Inventor(s): Andrew W. YEOH of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Atul MADHAVAN of Portland OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation, Christopher P. AUTH of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/02, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8234, H01L21/8238, H01L23/00, H01L23/522, H01L23/528, H01L23/532, H01L27/02, H01L27/088, H01L27/092, H01L29/06, H01L29/08, H01L29/165, H01L29/167, H01L29/417, H01L29/51, H01L29/78, H10B10/00
CPC Code(s): H01L29/66545
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. first and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. first dielectric spacer are adjacent the first side of the first gate electrode. a trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.
Inventor(s): Ou Yang of Santa Clara CA (US) for intel corporation, Carlos Cordeiro of Portland OR (US) for intel corporation, Cheng Chen of Portland OR (US) for intel corporation, Oren Kedem of Modiin Maccabim-Reut (IL) for intel corporation
IPC Code(s): H04B7/0413, H04L5/00, H04W72/04, H04W74/04
CPC Code(s): H04B7/0413
Abstract: some demonstrative embodiments include apparatuses, systems and/or methods of communicating a single-user (su) multiple-input-multiple-output (mimo) transmission. for example, a first wireless communication station may be configured to transmit a request to send (rts) to a second wireless communication station via a plurality of su mimo transmit (tx) sectors of the first wireless communication station, the rts to establish a transmit opportunity (txop) to transmit an su-mimo transmission to the second wireless communication station, a control trailer of the rts including an indication of an intent to transmit the su-mimo transmission to the second wireless communication station; and to transmit the su-mimo transmission to the second wireless communication station, upon receipt of a clear to send (cts) from the second wireless communication station indicating that the second wireless communication station is ready to receive the su-mimo transmission.
Inventor(s): Carlos CORDEIRO of Portland OR (US) for intel corporation
IPC Code(s): H04B7/06, H04W74/04
CPC Code(s): H04B7/0623
Abstract: techniques for supporting variable channel bandwidths in a wireless communications network are described. in one embodiment, for example, an apparatus may comprise a processor circuit and a communications management module, and the communications management module may be operable by the processor circuit to determine a channel bandwidth for communication over a channel of a wireless network, transmit a beamforming initiation message comprising a channel bandwidth parameter indicating the determined channel bandwidth, receive a beamforming initiation confirmation message confirming the channel bandwidth parameter, perform a beamforming training sequence to determine one or more beamforming parameters, and transmit one or more messages over the channel according to the determined channel bandwidth and the one or more beamforming parameters. other embodiments are described and claimed.
Inventor(s): Dan Horovitz of Rishon Letzion (IL) for intel corporation, Mordechai Alon of Or Yehuda (IL) for intel corporation, Kobi Guetta of Netanya (IL) for intel corporation, Yoni Kahana of Kfar Hess (IL) for intel corporation
IPC Code(s): H04L47/2441, H04L47/2425
CPC Code(s): H04L47/2441
Abstract: an apparatus, including: a classifier configured to classify, in real time, an application type of an application traffic stream based on one or more indicators received from one or more components of an edge device and associated with the application traffic stream; and a quality-of-service (qos) engine configured to assign a priority to the application traffic stream by modifying its packet headers, enabling a network module to dynamically prioritize the application traffic stream based on the classification.
Inventor(s): Arvind Merwaday of Beaverton OR (US) for intel corporation, Rath Vannithamby of Portland OR (US) for intel corporation, Dibakar Das of Hillsboro OR (US) for intel corporation, Dave Cavalcanti of Portland OR (US) for intel corporation, Necati Canpolat of Beaverton OR (US) for intel corporation
IPC Code(s): H04W28/06
CPC Code(s): H04W28/06
Abstract: for example, an apparatus may include logic and circuitry configured to cause a non access point (ap) (non-ap) station (sta) to set one or more segment-association-information (sai) queue-size subfields in a control field. for example, the one or more sai queue-size subfields may indicate queue sizes of one or more sai queues at the non-ap sta. for example, an sai queue of the one or more sai queues may queue packet segments corresponding to a same application layer packet. for example, the non-ap sta may be configured to transmit a frame to an ap, wherein a media access control (mac) header of the frame includes the control field.
Inventor(s): Mohan Kumar HALAPPA of BANGALORE (IN) for intel corporation, Oren HAGGAI of Kefar Sava (IL) for intel corporation, Srinivas KROVVIDI of Hyderabad (IN) for intel corporation
IPC Code(s): H04W76/10
CPC Code(s): H04W76/10
Abstract: disclosed herein are devices, methods, and systems for automatically switching a mode of the isochronous adaption layer. the system establishes a connection group via a wireless transceiver, where the connection group includes a listening device and another device. the wireless transceiver may transmit data packets to the connection group using a communication connection in a data packet mode. the system may determine a reconfiguration of the communication connection based on an activity status of the other device within the connection group, wherein the reconfiguration comprises changing the data packet mode of the communication connection to a second data packet mode. the system may then cause the wireless transceiver to transmit the data packets over the communication connection in the second data packet mode.
20250024622. PROTRUSIONS OF SOCKET BODIES HAVING METAL_simplified_abstract_(intel corporation)
Inventor(s): Richard Canham of West Richland WA (US) for intel corporation, Eric W. Buddrius of Hillsboro OR (US) for intel corporation, Jeffory L. Smalley of East Olympia WA (US) for intel corporation, Garrett Frans Pauwels of Beaverton OR (US) for intel corporation, Emery Evon Frey of Portland OR (US) for intel corporation, Steven Adam Klein of Chandler AZ (US) for intel corporation, Daniel Neumann of Tualatin OR (US) for intel corporation
IPC Code(s): H05K7/10, H01R12/57, H01R13/11, H01R13/405
CPC Code(s): H05K7/10
Abstract: protrusions of socket bodies having metal are disclosed. an example apparatus comprises a socket body, the socket body including a plastic material, an array of contacts distributed across a surface of the socket body, and a protrusion extending away from the surface of the socket body, the protrusion to facilitate alignment of an ic package with the array of contacts, the protrusion including metal.
Inventor(s): Jeff Ku of Taipei (TW) for intel corporation, Smit Kapila of Bangalore (IN) for intel corporation, Shantanu Kulkarni of Hillsboro OR (US) for intel corporation, Min Suet Lim of Penang (MY) for intel corporation, Surya Pratap Mishra of Portland OR (US) for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20327
Abstract: a thermal ground plane (tgp), including: a vapor chamber containing an ionized fluid; a reservoir fluidly connected with the vapor chamber, configured to store excess ionized fluid; and an electromagnetic source configured to dynamically direct a variable amount of the excess ionized fluid from the reservoir to the vapor chamber based on a thermal resistance of the ionized fluid in the vapor chamber or a temperature of the tgp at a location proximate to a heat source.
Inventor(s): Hardeep SINGH of Folsom CA (US) for intel corporation, Rachit SHARMA of Vancouver (CA) for intel corporation, Timothy Glen HANNA of Tigard OR (US) for intel corporation, Devdatta P. KULKARNI of Portland OR (US) for intel corporation
IPC Code(s): H05K7/20, H05K7/14
CPC Code(s): H05K7/20772
Abstract: an apparatus is described. the apparatus includes a cooling mass. the apparatus includes a cooling block having an opening to receive a portion of the cooling mass. the apparatus having a spring element to be rotated about an axis of rotation. an obstruction between a hot pluggable electronic component and an electro-mechanical connector is to be removed by the spring element's rotation. the cooling mass is to be pressed toward the hot pluggable electronic component in response to a force induced by the spring element's rotation.
- Intel Corporation
- G02B6/42
- G02B6/12
- G02B6/13
- H01L25/16
- H10B41/00
- CPC G02B6/42
- Intel corporation
- G02B6/30
- G02B6/34
- H01L23/367
- H01L25/075
- H01L33/58
- H01L33/62
- H04B10/40
- CPC G02B6/4201
- G06F9/48
- CPC G06F9/4881
- G06F12/0815
- G06F3/06
- CPC G06F12/0815
- G06F17/16
- G06F7/544
- G06F9/30
- CPC G06F17/16
- G06F21/12
- CPC G06F21/125
- G06N3/086
- CPC G06N3/086
- G06N10/20
- CPC G06N10/20
- G06T7/00
- G06T3/02
- G06T7/33
- G06T7/73
- CPC G06T7/001
- G11C29/12
- G11C29/36
- CPC G11C29/12015
- H01L23/498
- H01L23/08
- CPC H01L23/49827
- H01L23/64
- H01F27/28
- H01F27/32
- H01F41/04
- H01F41/12
- H01L21/48
- H01L23/00
- CPC H01L23/645
- H01L25/065
- H01L25/00
- H01L25/18
- CPC H01L25/0652
- H01L27/088
- H01L23/522
- H01L29/06
- H01L29/417
- H01L29/66
- H01L29/78
- CPC H01L27/0886
- H01L27/092
- H01L21/768
- H01L21/8238
- CPC H01L27/0924
- H01L27/15
- CPC H01L27/156
- H01L29/49
- H01L21/28
- H01L21/8234
- H01L23/535
- CPC H01L29/4983
- H01L21/02
- H01L21/033
- H01L21/285
- H01L21/308
- H01L21/311
- H01L21/762
- H01L23/528
- H01L23/532
- H01L27/02
- H01L29/08
- H01L29/165
- H01L29/167
- H01L29/51
- H10B10/00
- CPC H01L29/66545
- H04B7/0413
- H04L5/00
- H04W72/04
- H04W74/04
- CPC H04B7/0413
- H04B7/06
- CPC H04B7/0623
- H04L47/2441
- H04L47/2425
- CPC H04L47/2441
- H04W28/06
- CPC H04W28/06
- H04W76/10
- CPC H04W76/10
- H05K7/10
- H01R12/57
- H01R13/11
- H01R13/405
- CPC H05K7/10
- H05K7/20
- CPC H05K7/20327
- H05K7/14
- CPC H05K7/20772