Patent Applications by Intel Corporation on February 27th, 2025

Intel Corporation: 35 patent applications

Intel Corporation has applied for patents in the areas of H01L23/00 (4), H01L23/498 (3), G06F9/30 (3), H01L25/065 (2), H10B10/00 (2) G02B6/12004 (1), H04W48/02 (1), H04B7/06968 (1), H04L5/0007 (1), H04L41/0896 (1)

With keywords such as: network, conductive, circuitry, apparatus, data, material, embodiments, example, memory, and layer in patent application abstracts.

Patent Applications by Intel Corporation

20250067925. PHOTONICS INTEGRATED CIRCUIT EMBEDDED IN A GLASS SUBSTRATE AND OPTICALLY COUPLED WITH A PHOTONIC WIRE BOND_simplified_abstract_(intel corporation)

Inventor(s): Chia-Pin CHIU of Tempe AZ (US) for intel corporation, Kaveh HOSSEINI of Livermore CA (US) for intel corporation

IPC Code(s): G02B6/12, G02B6/13

CPC Code(s): G02B6/12004

Abstract: embodiments herein relate to systems, apparatuses, techniques or processes for packages that include a glass substrate, with one or more photonic integrated circuits embedded into cavities within the glass substrate. dies may be on the glass substrate and electrically coupled with the embedded photonic integrated circuits. photonic wire bonds may optically couple the embedded photonic integrated circuits with one or more optical waveguides that are within the glass substrate. other embodiments may be described and/or claimed.

20250068337. METHODS AND APPARATUS TO PERSISTENT PLATFORM SERVICE RECORDS_simplified_abstract_(intel corporation)

Inventor(s): Matthew I. Royer of Portland OR (US) for intel corporation, Barak Einav of Jerusalem (IL) for intel corporation, Tsippy Mendelson of Jerusalem (IL) for intel corporation, Narendra K. Vanguput of Bangalore (IN) for intel corporation, Garritt C. Binder of Loomis CA (US) for intel corporation, Moorthy Rajesh of Folsom CA (US) for intel corporation, Lili Ma of Shanghai (CN) for intel corporation, Hemant Desai of Gilbert AZ (US) for intel corporation, Robert Vaughn of Portland OR (US) for intel corporation

IPC Code(s): G06F3/06

CPC Code(s): G06F3/0622

Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to manage and securely store platform service records. an apparatus for monitoring a compute device, the apparatus comprising interface circuitry, non-volatile flash memory, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to analyze telemetry data obtained via a sensor of the compute device, the analyzing of the telemetry data to detect an undesired event, and storing, in response to detection of the undesired event, the telemetry data in a ledger, wherein the ledger is digitally signed to prevent unauthorized modification and stored in the non-volatile flash memory.

20250068373. METHOD, APPARATUS, AND COMPUTER-READABLE MEDIUM FOR RECONFIGURING AN ACTIVE REGION OF A DISPLAY_simplified_abstract_(intel corporation)

Inventor(s): Aruni NELSON of Folsom CA (US) for intel corporation, Ashok MISHRA of Portland OR (US) for intel corporation, Rajesh POORNACHANDRAN of Portland OR (US) for intel corporation

IPC Code(s): G06F3/14, G06F21/10, G09G3/20

CPC Code(s): G06F3/1446

Abstract: a method, apparatus, and non-transitory computer-readable medium or reconfiguring an original active region of a first display is disclosed. the apparatus comprises interface circuitry for communication with both the first and second displays, memory circuitry, machine-readable instructions, and processor circuitry configured to execute the machine-readable instructions. the processor circuitry is operable to determine a subset active region within the original active region of the first display and to generate a hint for configuring the second display based on this subset active region.

20250068423. INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER THREAD_simplified_abstract_(intel corporation)

Inventor(s): Jorge Eduardo Parra Osorio of El Dorado Hills CA (US) for intel corporation, Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation, Pradeep Golconda of El Dorado Hills CA (US) for intel corporation, Brent Schwartz of Sacramento CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Sabareesh Ganapathy of Bangalore (IN) for intel corporation, Peter Caday of Beaverton OR (US) for intel corporation, Wei-Yu Chen of San Jose CA (US) for intel corporation, Po-Yu Chen of San Diego CA (US) for intel corporation, Timothy Bauer of Hillsboro OR (US) for intel corporation, Maxim Kazakov of San Diego CA (US) for intel corporation, Stanley Gambarin of Belmont CA (US) for intel corporation, Samir Pandya of Folsom CA (US) for intel corporation

IPC Code(s): G06F9/30, G06F9/38

CPC Code(s): G06F9/3016

Abstract: described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. the second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.

20250068438. AUTONOMOUS GENERATION OF NETWORK AND DEVICE CONFIGURATIONS_simplified_abstract_(intel corporation)

Inventor(s): Mateo Guzman of Beaverton OR (US) for intel corporation, Marcos Carranza of Portland OR (US) for intel corporation, Daniel Biederman of Saratoga CA (US) for intel corporation, Chihjen Chang of Union City CA (US) for intel corporation, Jeremy Petsinger of Fort Collins CO (US) for intel corporation, Yadong Li of Portland OR (US) for intel corporation, Mitu Aggarwal of Portland OR (US) for intel corporation, Suyog Kulkarni of Portland OR (US) for intel corporation, Mariano Ortega de Mues of Hillsboro OR (US) for intel corporation, Rajesh Poornachandran of Portland OR (US) for intel corporation, Cesar Martinez of Hillsboro OR (US) for intel corporation, Mats Agerstam of Portland OR (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Usharani Ayyalasomayajula of Bangalore (IN) for intel corporation

IPC Code(s): G06F9/445

CPC Code(s): G06F9/44505

Abstract: described herein are technique to enable the autonomous generation of configurations for a network environment, including but not limited to an edge network of a datacenter. additional embodiments include prompt-based generation of network and device configurations and neural network based systems for adaptive network management.

20250068457. COMPUTER VISION PIPELINE MANAGEMENT IN PROGRAMMABLE NETWORK INTERFACE DEVICE_simplified_abstract_(intel corporation)

Inventor(s): Marcos Carranza of Portland OR (US) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Mariano Ortega De Mues of Hillsboro OR (US) for intel corporation, Mateo Guzman of Beaverton OR (US) for intel corporation, Patrick Connor of Beaverton OR (US) for intel corporation, Cesar Martinez-Spessot of Hillsboro OR (US) for intel corporation

IPC Code(s): G06F9/455

CPC Code(s): G06F9/45558

Abstract: an apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (cv) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface device; access instructions to cause the portions of the set of the cv processes to be deployed on the host device and the programmable network interface device; and wherein a media processing portion of the set of the cv processes is to be deployed to the programmable circuitry, and wherein the programmable circuitry is to utilize media processing hardware circuitry hosted by the apparatus to perform the media processing portion.

20250068473. DISTRIBUTED REGISTER FILE CACHE TO REDUCE L1 BANDWIDTH REQUIREMENTS_simplified_abstract_(intel corporation)

Inventor(s): Jorge Eduardo Parra Osorio of El Dorado Hills CA (US) for intel corporation, Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation

IPC Code(s): G06F9/50, G06F9/30

CPC Code(s): G06F9/5033

Abstract: described herein is a graphics processor comprising a graphics processing cluster coupled with the memory interface, the graphics processing cluster including a plurality of processing resources, a processing resource of the plurality of processing resources including a register file including a first plurality of registers associated with a first hardware thread of a plurality of hardware threads of the processing resource and a second plurality of registers associated with a second hardware thread of the plurality of hardware threads of the processing resource and first circuitry configured to facilitate access to memory on behalf of the plurality of hardware threads and store metadata for memory access requests from the plurality of hardware threads.

20250068529. TEST AND REPAIR ARCHITECTURE FOR INTER AND INTRA CLUSTER DEFECTS_simplified_abstract_(intel corporation)

Inventor(s): Sreejit CHAKRAVARTY of San Jose CA (US) for intel corporation

IPC Code(s): G06F11/22

CPC Code(s): G06F11/2242

Abstract: embodiments disclosed herein include apparatuses for improved testing between chips. in an embodiment, an apparatus comprises a plurality of transmit clusters on a first chip, where individual ones of the plurality of transmit clusters comprise a set of transmit lanes on the first chip. in an embodiment, a plurality of finite state machines (fsms) are on the first chip, where individual ones of the plurality of transmit clusters comprise one of the plurality of fsms. in an embodiment, a global transmit test generator is communicatively coupled to each of the set of transmit lanes on the first chip, and a global transmit expected response generator is communicatively coupled to each of the plurality of fsms on the first chip.

20250068556. Secure Shared Memory Buffer For Communications Between Trusted Execution Environment Virtual Machines_simplified_abstract_(intel corporation)

Inventor(s): Arie AHARON of Haifa (IL) for intel corporation, Jiewen YAO of Shanghai (CN) for intel corporation

IPC Code(s): G06F12/02, G06F9/455, G06F21/53

CPC Code(s): G06F12/023

Abstract: a system includes memory circuitry to store a secure shared memory buffer (ssmb) and instructions; and a processor to create the ssmb in the memory circuitry and assign ownership of the ssmb to an ssmb owner, the ssmb owner being a trusted execution environment virtual machine running on the computing system; configure access permissions for the ssmb by the ssmb owner to allow one or more ssmb users to access the ssmb, the one or more ssmb users being trusted execution environment virtual machines running on the computing system; allocate memory by the ssmb owner from the ssmb owner's private memory space in the memory circuitry for the ssmb; and allowing secure access by the one or more ssmb users to the ssmb in response to successfully verifying authorization of the one or more ssmb users based at least in part on the access permissions.

20250068588. SCALAR CORE INTEGRATION_simplified_abstract_(intel corporation)

Inventor(s): Joydeep RAY of Folsom CA (US) for intel corporation, Aravindh ANANTARAMAN of Folsom CA (US) for intel corporation, Abhishek R. APPU of El Dorado Hills CA (US) for intel corporation, Altug KOKER of El Dorado Hills CA (US) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, Valentin ANDREI of San Jose CA (US) for intel corporation, Subramaniam MAIYURAN of Gold River CA (US) for intel corporation, Nicolas GALOPPO VON BORRIES of Portland OR (US) for intel corporation, Varghese GEORGE of Folsom CA (US) for intel corporation, Mike MACPHERSON of Portland OR (US) for intel corporation, Ben ASHBAUGH of Folsom CA (US) for intel corporation, Murali RAMADOSS of Folsom CA (US) for intel corporation, Vikranth VEMULAPALLI of Folsom CA (US) for intel corporation, William SADLER of Folsom CA (US) for intel corporation, Jonathan PEARCE of Portland OR (US) for intel corporation, Sungye KIM of Folsom CA (US) for intel corporation

IPC Code(s): G06F15/80, G06F9/30, G06F9/38, G06T15/00

CPC Code(s): G06F15/8069

Abstract: methods and apparatus relating to scalar core integration in a graphics processor. in an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. other embodiments are also disclosed and claimed.

20250068776. REGION-BASED DETERMINISTIC MEMORY SAFETY_simplified_abstract_(intel corporation)

Inventor(s): Michael LeMay of Hillsboro OR (US) for intel corporation, David M. Durham of Beaverton OR (US) for intel corporation

IPC Code(s): G06F21/79, G06F12/0871, G06F12/0882, G06F21/55, G06F21/60

CPC Code(s): G06F21/79

Abstract: methods and apparatus relating to techniques for region-based deterministic memory safety are described. in some embodiment, one or more instructions may be used to encrypt, decrypt, and/or check a pointer to a portion of the data stored in memory. the portion of the data is stored in a first region of the memory. the first region of the memory includes a plurality of identically sized allocation slots. other embodiments are also disclosed and claimed.

20250068891. DYNAMIC TRIPLET CONVOLUTION FOR CONVOLUTIONAL NEURAL NETWORKS_simplified_abstract_(intel corporation)

Inventor(s): Dongqi CAI of Beijing (CN) for intel corporation, Anbang YAO of Beijing (CN) for intel corporation, Chao LI of Beijing (CN) for intel corporation, Yurong CHEN of Beijing (CN) for intel corporation, Wenjian SHAO of Shanghai (CN) for intel corporation

IPC Code(s): G06N3/0464

CPC Code(s): G06N3/0464

Abstract: methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement dynamic triplet convolution for convolutional neural networks are disclosed. an example apparatus disclosed herein for a convolutional neural network is to calculate one or more scalar kernels based on an input feature map applied to a layer of the convolutional neural network, ones of the one or more scalar kernels corresponding to respective dimensions of a static multidimensional convolutional filter associated with the layer of the convolutional neural network. the disclosed example apparatus is also to scale elements of the static multidimensional convolutional filter along a first one of the dimensions based on a first one of the one or more scalar kernels corresponding to the first one of the dimensions to determine a dynamic multidimensional convolutional filter associated with the layer of the convolutional neural network.

20250068916. SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR TEACHER-FREE SELF-FEATURE DISTILLATION TRAINING OF MACHINE LEARNING MODELS_simplified_abstract_(intel corporation)

Inventor(s): Yurong Chen of Beijing (CN) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation, Yi Qian of Shanghai (CN) for intel corporation, Yu Zhang of Beijing (CN) for intel corporation, Shandong Wang of Beijing (CN) for intel corporation

IPC Code(s): G06N3/088

CPC Code(s): G06N3/088

Abstract: methods, apparatus, systems, and articles of manufacture are disclosed for teacher-free self-feature distillation training of machine-learning (ml) models. an example apparatus includes at least one memory, instructions, and processor circuitry to at least one of execute or instantiate the instructions to perform a first comparison of (i) a first group of a first set of feature channels (fcs) of an ml model and (ii) a second group of the first set, perform a second comparison of (iii) a first group of a second set of fcs of the ml model and one of (iv) a third group of the first set or a first group of a third set of fcs of the ml model, adjust parameter(s) of the ml model based on the first and/or second comparisons, and, in response to an error value satisfying a threshold, deploy the ml model to execute a workload based on the parameter(s).

20250069182. GRAPHICS ANTI-ALIASING RESOLVE WITH STENCIL MASK_simplified_abstract_(intel corporation)

Inventor(s): Hugues Labbe of Folsom CA (US) for intel corporation, Tomer Bar-on of Petah Tikva (IL) for intel corporation, Kai Xiao of Santa Clara CA (US) for intel corporation, Ankur N. Shah of Folsom CA (US) for intel corporation, John G. Gierach of Hillsboro OR (US) for intel corporation

IPC Code(s): G06T1/20, G06T15/80

CPC Code(s): G06T1/20

Abstract: an embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. the resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. other embodiments are disclosed and claimed.

20250069539. POWER OPTIMIZED MULTI-REGIONAL UPDATE DISPLAY_simplified_abstract_(intel corporation)

Inventor(s): Perazhi Sameer Kalathil of Folsom CA (US) for intel corporation, Vishal Ravindra Sinha of Portland OR (US) for intel corporation, Krishna Kishore Nidamanuri of Bangalore (IN) for intel corporation, Mallari C. Hanchate of Bangalore (IN) for intel corporation, Vivek Paranjape of Portland OR (US) for intel corporation, Kunjal S. Parikh of Fremont CA (US) for intel corporation, Roland P. Wooster of Folsom CA (US) for intel corporation

IPC Code(s): G09G3/20

CPC Code(s): G09G3/2092

Abstract: in one embodiment, a display panel may have multiple regions that are controlled by independent driver circuitries to allow for independent refreshing of different regions. circuitry, e.g., in a graphics source or in the display, can determine, based on a partial frame update, which panel regions to refresh and refresh those regions, e.g., while not refreshing other regions of the panel.

20250069902. INTEGRATED CIRCUIT PACKAGE SUPPORTS_simplified_abstract_(intel corporation)

Inventor(s): Kristof Kuwawi Darmawikarta of Chandler AZ (US) for intel corporation, Robert May of Chandler AZ (US) for intel corporation, Sri Ranga Sai Boyapati of Austin TX (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Chung Kwang Christopher Tan of Portland OR (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation

IPC Code(s): H01L21/48, H01L23/498

CPC Code(s): H01L21/4857

Abstract: disclosed herein are integrated circuit (ic) package supports and related apparatuses and methods. for example, in some embodiments, a method for forming an ic package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.

20250070030. MICROELECTRONIC COMPONENT HAVING MOLDED REGIONS WITH THROUGH-MOLD VIAS_simplified_abstract_(intel corporation)

Inventor(s): Sanka GANESAN of Chandler AZ (US) for intel corporation, Ram VISWANATH of Phoenix AZ (US) for intel corporation, Xavier Francois BRUN of Hillsboro OR (US) for intel corporation, Tarek A. IBRAHIM of Mesa AZ (US) for intel corporation, Jason M. GAMBA of Gilbert AZ (US) for intel corporation, Manish DUBEY of Chandler AZ (US) for intel corporation, Robert Alan MAY of Chandler AZ (US) for intel corporation

IPC Code(s): H01L23/538, H01L23/00, H01L23/31, H01L23/367

CPC Code(s): H01L23/5381

Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (tsv); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (tmv) conductively coupled to the tsv; and a second mold material region at the second face, wherein the second mold material region includes a second tmv conductively coupled to the tsv.

20250070056. METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES_simplified_abstract_(intel corporation)

Inventor(s): Dae-Woo KIM of Phoenix AZ (US) for intel corporation, Sujit SHARAN of Chandler AZ (US) for intel corporation, Sairam AGRAHARAM of Chandler AZ (US) for intel corporation

IPC Code(s): H01L23/58, G01R31/27, H01L21/66, H01L23/00, H01L23/14, H01L23/498, H01L23/522, H01L23/538, H01L23/544, H01L25/065, H01L25/18, H10B80/00

CPC Code(s): H01L23/585

Abstract: metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. in an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. a metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. a first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. a second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. a metal-free region of the dielectric material stack surrounds the second metal guard ring. the metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

20250070083. MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)

Inventor(s): Adel A. ELSHERBINI of Chandler AZ (US) for intel corporation, Henning BRAUNISCH of Phoenix AZ (US) for intel corporation, Aleksandar ALEKSOV of Chandler AZ (US) for intel corporation, Shawna M. LIFF of Scottsdale AZ (US) for intel corporation, Johanna M. SWAN of Scottsdale AZ (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation, Kimin JUN of Portland OR (US) for intel corporation, Brennen MUELLER of Portland OR (US) for intel corporation, Paul B. FISCHER of Portland OR (US) for intel corporation

IPC Code(s): H01L25/065, H01L23/498, H01L25/00

CPC Code(s): H01L25/0652

Abstract: microelectronic assemblies, and related devices and methods, are disclosed herein. for example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

20250070491. SOCKET CONTACT PIN DEPOPULATION AND HOUSING CUT-OUT IN LOW S-G REGION FOR POST-RESONANCE CROSSTALK SUPPRESSION IN HIGH FREQUENCY APPLICATIONS_simplified_abstract_(intel corporation)

Inventor(s): Saikat MONDAL of Chandler AZ (US) for intel corporation, Zhichao ZHANG of Chandler AZ (US) for intel corporation, Oluwafemi AKINWALE of Hayward CA (US) for intel corporation, Kemal AYGÜN of Tempe AZ (US) for intel corporation

IPC Code(s): H01R12/71, H01L23/00, H01R13/24, H01R13/405

CPC Code(s): H01R12/714

Abstract: embodiments disclosed herein include sockets and socket modules. in an embodiment, a socket module comprises a housing and a first pin through the housing in a first row of pins. in an embodiment, a second pin is through the housing in a second row of pins. in an embodiment, at least three intervening rows of pins are between the first row of pins and the second row of pins. in an embodiment, one or more pin locations in the at least three intervening rows of pins are depopulated.

20250070849. COMMON TCI SWITCH DELAY FOR CARRIER AGGREGATION_simplified_abstract_(intel corporation)

Inventor(s): Hua Li of Beijing 11 (CN) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation, Andrey Chervyakov of Maynooth (IE) for intel corporation, Rui Huang of Beijing (CN) for intel corporation, Ilya Bolotin of Nizhny-Novgorod (RU) for intel corporation

IPC Code(s): H04B7/06, H04B17/318, H04L5/00, H04W36/00

CPC Code(s): H04B7/06968

Abstract: an apparatus and system of establishing a transmission configuration indication (tci) state switch delay are described. the tci state switch delay for a reference signal (rs) on a component carrier (cc) in intra-band carrier aggregation (ca) is dependent on whether a tci state indicated in the dci is known based on a type of quasi co-location (qcl) and whether a common tci state id is known on the cc. the delay is known for a delay of qcl-typed rs on the cc or any other qcl-typed rs in the cc set that contains the cc. the delay may be based on that of a single cc delay, with the slot where the new tci state applies determined based on a carrier with a smallest subcarrier spacing (scs) in the cc or the cc set.

20250070926. APPARATUS, SYSTEM, AND METHOD OF CHANNEL SOUNDING OVER A WIDE CHANNEL BANDWIDTH_simplified_abstract_(intel corporation)

Inventor(s): Qinghua Li of San Ramon CA (US) for intel corporation, Xiaogang Chen of Portland OR (US) for intel corporation, Po-Kai Huang of San Jose CA (US) for intel corporation, Yonathan Segev of Sunnyvale CA (US) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation, Cheng Chen of Camas WA (US) for intel corporation

IPC Code(s): H04L5/00, H04L27/34

CPC Code(s): H04L5/0007

Abstract: for example, a wireless communication device may be configured to generate a wide bandwidth long training field (ltf) configured for channel sounding over a wide channel bandwidth of at least 320 megahertz (mhz). for example, the wide bandwidth ltf may include a plurality of orthogonal frequency division multiplexing (ofdm) symbols over the wide channel bandwidth. for example, the wireless communication device may be configured to transmit a null data packet (ndp) over the wide channel bandwidth. for example, the ndp may include a non-high-throughput (non-ht) short training field (l-stf), a non-hit ltf (l-ltf) after the l-stf, a non-ht signal (l-sig) field after the l-ltf, a repeated l-sig (rl-sig) field after the l-sig field, and the wide bandwidth ltf after the rl-sig field.

20250071023. METHODS, SYSTEM, ARTICLES OF MANUFACTURE, AND APPARATUS TO MANAGE TELEMETRY DATA IN AN EDGE ENVIRONMENT_simplified_abstract_(intel corporation)

Inventor(s): Kshitij Doshi of Tempe AZ (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Ned Smith of Beaverton OR (US) for intel corporation, Timothy Verrall of Pleasant Hill CA (US) for intel corporation, Rajesh Gadiyar of Chandler AZ (US) for intel corporation

IPC Code(s): H04L41/0896, H04L9/40, H04L41/0893

CPC Code(s): H04L41/0896

Abstract: methods, apparatus, systems and articles of manufacture are disclosed to manage telemetry data in an edge environment. an example apparatus includes a publisher included in a first edge platform to publish a wish list obtained from a consumer, the wish list including tasks to execute, a commitment determiner to determine whether a commitment is viable to execute at least one of the tasks in the wish list, the commitment to be processed to identify the telemetry data, and a communication interface to establish a communication channel to facilitate transmission of the telemetry data from the first edge platform to a second edge platform.

20250071037. MANAGEMENT OF DATA TRANSFER FOR NETWORK OPERATION_simplified_abstract_(intel corporation)

Inventor(s): Daniel Biederman of Saratoga CA (US) for intel corporation, Patrick Connor of Beaverton OR (US) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Marcos Carranza of Portland OR (US) for intel corporation, Anjali Singhai Jain of Portland OR (US) for intel corporation

IPC Code(s): H04L43/0823, G11C7/10

CPC Code(s): H04L43/0847

Abstract: management of data transfer for network operation is described. an example of an apparatus includes one or more network interfaces and a circuitry for management of data transfer for a network, wherein the circuitry for management of data transfer includes at least circuitry to analyze a plurality of data elements transferred on the network to identify data elements that are delayed or missing in transmission on the network, circuitry to determine one or more responses to delayed or missing data on the network, and circuitry to implement one or more data modifications for delayed or missing data on the network, including circuitry to provide replacement data for the delayed or missing data on the network.

20250071118. Non-transitory computer readable medium, apparatus_simplified_abstract_(intel corporation)

Inventor(s): Piotr ZMIJEWSKI of Gdansk (PL) for intel corporation, Arkadiusz BERENT of Tuchom (PL) for intel corporation, Mateusz BRONK of Gdansk (PL) for intel corporation, Krystian MATUSIEWICZ of Gdansk (PL) for intel corporation

IPC Code(s): H04L9/40

CPC Code(s): H04L63/101

Abstract: provided is a non-transitory machine-readable medium including machine-readable instructions. the machine-readable instructions cause, when executed on an apparatus, the apparatus to receive, by a trusted authority, a request for access to user data stored on a distributed network. the machine-readable instructions further cause the apparatus to search, by the trusted authority, an immutable ledger for an entry related to the user data. the machine-readable instructions further cause the apparatus to selectively decide, by the trusted authority and based on an access policy for the user data indicated by the entry, whether to grant access to the user data.

20250071190. MICROSERVICE COMMUNICATION AND COMPUTING OFFLOADING VIA SERVICE MESH_simplified_abstract_(intel corporation)

Inventor(s): Zongrui Ding of Portland OR (US) for intel corporation, Qian Li of Portland OR (US) for intel corporation, Xiaopeng Tong of Beijing (CN) for intel corporation, Alexandre Saso Stojanovski of Paris 75 (FR) for intel corporation, Thomas Luetzenkirchen of Taufkirchen BY (DE) for intel corporation, Sudeep Palat of Gloucestershire (GB) for intel corporation, Ching-Yu Liao of Santa Clara CA (US) for intel corporation, Abhijeet Kolekar of Portland OR (US) for intel corporation, Sangeetha L. Bangolae of Santa Clara CA (US) for intel corporation, Youn Hyoung Heo of Santa Clara CA (US) for intel corporation

IPC Code(s): H04L67/61, H04L67/56

CPC Code(s): H04L67/61

Abstract: various embodiments herein provide techniques to enable communication between a user equipment (ue) microservice and a microservice of a wireless cellular network via service mesh. a first solution is described, in which the service mesh is in the network, and the network includes a service mesh proxy to communicate with the ue. a second solution is also described, in which the ue is part of the cellular network service mesh and includes a service mesh proxy in the ue. other embodiments may be described and claimed.

20250071662. SATELLITE 5G TERRESTRIAL AND NON-TERRESTRIAL NETWORK INTERFERENCE EXCLUSION ZONES_simplified_abstract_(intel corporation)

Inventor(s): Stephen T. Palermo of Chandler AZ (US) for intel corporation, Chetan Hiremath of Portland OR (US) for intel corporation, Rajesh Gadiyar of Chandler AZ (US) for intel corporation, Jason K. Smith of Lake Oswego OR (US) for intel corporation, Valerie J. Parker of Portland OR (US) for intel corporation, Udayan Mukherjee of Portland OR (US) for intel corporation, Neelam Chandwani of Portland OR (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Ned M. Smith of Beaverton OR (US) for intel corporation

IPC Code(s): H04W48/02, H04B7/185, H04B7/195, H04W16/28, H04W84/06

CPC Code(s): H04W48/02

Abstract: various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. in an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

20250071724. TECHNIQUES FOR A POSITIONING REFERENCE SIGNAL MEASUREMENT WITH A MEASUREMENT GAP_simplified_abstract_(intel corporation)

Inventor(s): Rui Huang of Santa Clara CA (US) for intel corporation, Andrey Chervyakov of Kildare (IE) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation, Yi Guo of Shanghai (CN) for intel corporation, Hua Li of Santa Clara CA (US) for intel corporation, Ilya Bolotin of Santa Clara CA (US) for intel corporation

IPC Code(s): H04W64/00, H04W4/029

CPC Code(s): H04W64/003

Abstract: various embodiments herein provide techniques for configuring and/or using a measurement gap (mg) for a positioning reference signal (prs) measurement. for example. a user equipment (ue) may receive a configuration of a pre-configured measurement gap; identify that a measurement gap is needed for a positioning reference signal (prs) measurement and that the ce has not previously notified a network of the prs measurement prior to receipt of the configuration; and encode, based on the identification, a location measurement indication for transmission to a network entity to indicate that the prs measurement is to be performed. other embodiments may be described and claimed.

20250071820. DETERMINATION OF RAR WINDOW AND RA-RNTI FOR MULTIPLE PRACH TRANSMISSIONS_simplified_abstract_(intel corporation)

Inventor(s): Gang Xiong of Portland OR (US) for intel corporation, Prerana Rane of Santa Clara CA (US) for intel corporation

IPC Code(s): H04W74/0833, H04W72/23

CPC Code(s): H04W74/0833

Abstract: various embodiments herein provide techniques for multiple physical random access channel (prach) transmissions. for example, embodiments provide techniques to determine a random access response (rar) window and/or a random access (ra)—radio network temporary identifier (rnti) for multiple prach transmissions. furthermore, embodiments relate to multiple prach transmissions triggered by physical downlink control channel (pdcch) order. other embodiments may be described and claimed.

20250071885. RADIO FREQUENCY FRONT-END STRUCTURES_simplified_abstract_(intel corporation)

Inventor(s): Sidharth Dalmia of Portland OR (US) for intel corporation, Zhenguo Jiang of Chandler AZ (US) for intel corporation, William J. Lambert of Chandler AZ (US) for intel corporation, Kirthika Nahalingam of San Jose CA (US) for intel corporation, Swathi Vijayakumar of Folsom CA (US) for intel corporation

IPC Code(s): H05K1/02, G06F1/16, H01F5/04, H01L25/16, H04B1/40, H05K1/18

CPC Code(s): H05K1/0243

Abstract: disclosed herein are radio frequency (rf) front-end structures, as well as related methods and devices. in some embodiments, an rf front-end package may include an rf package substrate including an embedded passive circuit element. at least a portion of the embedded passive circuit element may be included in a metal layer of the rf package substrate. the rf package substrate may also include a ground plane in the metal layer.

20250071924. Tall DIMM Structural Retention_simplified_abstract_(intel corporation)

Inventor(s): Phil Geng of Washougal WA (US) for intel corporation, David Shia of Portland OR (US) for intel corporation, Xiang Li of Portland OR (US) for intel corporation, George Vergis of Portland OR (US) for intel corporation, Ralph Miele of Hillsboro OR (US) for intel corporation, Sanjoy Saha of Portland OR (US) for intel corporation, Jeffory Smalley of East Olympia WA (US) for intel corporation

IPC Code(s): H05K7/14

CPC Code(s): H05K7/1402

Abstract: methods and apparatus relating to tall dual inline memory module (dimm) structural retention are described. in one embodiment, a dual in-line memory module (dimm) retention frame is coupled to a top portion of a tall (e.g., “two unit” or taller) dimm. a plurality of fasteners physically attach the dimm retention frame to a printed circuit board (pcb). the dimm retention frame reduces movement of the tall dimm. other embodiments are also claimed and disclosed.

20250071938. COLD PLATE ARCHITECTURE FOR LIQUID COOLING OF DEVICES_simplified_abstract_(intel corporation)

Inventor(s): Jin YANG of Hillsboro OR (US) for intel corporation, David SHIA of Portland OR (US) for intel corporation, Mohanraj PRABHUGOUD of Hillsboro OR (US) for intel corporation, Olaotan ELENITOBA-JOHNSON of Tigard OR (US) for intel corporation, Craig JAHNE of Beaverton OR (US) for intel corporation, Phil GENG of Washougal WA (US) for intel corporation

IPC Code(s): H05K7/20

CPC Code(s): H05K7/20254

Abstract: examples described herein relate to a cold plate. an example apparatus includes a first layer with one or more channels to receive fluid. the example apparatus further includes a second layer that is more rigid than the first layer. the second layer is to be mounted to the first layer and separated from the first layer by a gasket to reduce corrosion of the second layer.

20250071963. UNIFORM LAYOUTS FOR SRAM AND REGISTER FILE BIT CELLS_simplified_abstract_(intel corporation)

Inventor(s): Zheng GUO of Portland OR (US) for intel corporation, Clifford L. ONG of Portland OR (US) for intel corporation, Eric A. KARL of Portland OR (US) for intel corporation, Mark T. BOHR of Aloha OR (US) for intel corporation

IPC Code(s): H10B10/00, H01L23/528, H01L27/02, H01L27/092

CPC Code(s): H10B10/12

Abstract: uniform layouts for sram and register file bit cells are described. in an example, an integrated circuit structure includes a six transistor (6t) static random access memory (sram) bit cell on a substrate. the 6t sram bit cell includes first and second active regions parallel along a first direction of the substrate. first, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

20250072069. RECESSED VIA WITH CONDUCTIVE LINK TO ADJACENT CONTACT_simplified_abstract_(intel corporation)

Inventor(s): Leonard P. Guler of Hillsboro OR (US) for intel corporation, Desalegne B. Teweldebrhan of Sherwood OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation, Saurabh Acharya of Hillsboro OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Richard Schenker of Portland OR (US) for intel corporation

IPC Code(s): H01L29/08, H01L21/8234, H01L27/088, H01L29/06

CPC Code(s): H01L29/0847

Abstract: techniques to form semiconductor device conductive interconnections. in an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. a transistor device includes a semiconductor material extending from a source or drain region, a gate structure over the semiconductor material, and a contact on the source or drain region. adjacent to the source or drain region, a deep via structure extends in a vertical direction through an entire thickness of the gate structure. the via structure includes a conductive via that is recessed below a top surface of the conductive contact. a conductive bridge extends between the contact and the conductive via such that the conductive bridge contacts a portion of the contact and at least a portion of a top surface of the conductive via.

20250072078. HETEROGENEOUS METAL LINE COMPOSITIONS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION_simplified_abstract_(intel corporation)

Inventor(s): Andrew W. YEOH of Portland OR (US) for intel corporation, Joseph STEIGERWALD of Forest Grove OR (US) for intel corporation, Jinhong SHIN of Portland OR (US) for intel corporation, Vinay CHIKARMANE of Portland OR (US) for intel corporation, Christopher P. AUTH of Portland OR (US) for intel corporation

IPC Code(s): H01L29/66, H01L21/02, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8234, H01L21/8238, H01L23/00, H01L23/522, H01L23/528, H01L23/532, H01L27/02, H01L27/088, H01L27/092, H01L29/06, H01L29/08, H01L29/165, H01L29/167, H01L29/417, H01L29/51, H01L29/78, H10B10/00

CPC Code(s): H01L29/66545

Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ild layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. a second plurality of conductive interconnect lines is in and spaced apart by a second ild layer above the first ild layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Intel Corporation patent applications on February 27th, 2025