Intel Corporation patent applications on February 13th, 2025
Patent Applications by Intel Corporation on February 13th, 2025
Intel Corporation: 29 patent applications
Intel Corporation has applied for patents in the areas of G06F9/50 (3), G06F9/30 (3), G06F9/38 (2), G06N3/063 (2), G06T1/20 (2) G06F9/5027 (2), A63F13/52 (1), G06T1/20 (1), H04W64/00 (1), H04W60/02 (1)
With keywords such as: layer, apparatus, data, processor, device, including, systems, interface, network, and methods in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Tanujay Saha of Folsom CA (US) for intel corporation
IPC Code(s): A63F13/52, G06T3/4046, G06T3/4053
CPC Code(s): A63F13/52
Abstract: systems and methods for providing a high-resolution gaming experience on typical computer systems, including computer systems without high-end d-gpus. in particular, systems and methods are provided for optimizing deep learning-based super-sampling methods. a hardware-aware optimization technique for super-sampling machine learning networks uses a subset of intermediate outputs of the machine learning model for the previous game frame for convolution operations on the current frame, thereby reducing compute usage and latency without sacrificing quality of the output. the inputs are concatenated and passed through a convolutional neural network (cnn), such as a u-net-based cnn. the output of the cnn is a high-resolution image frame that can be post-processed to generate a final output. the hardware optimization technique can be implemented in a neural network framework that divides the machine learning inference across available compute resources on the computer platform.
20250052512. MULTI-SECTIONAL VAPOR CHAMBERS_simplified_abstract_(intel corporation)
Inventor(s): Shantanu Kulkarni of Hillsboro OR (US) for intel corporation, Jeff Ku of Taipei (TW) for intel corporation, Baomin Liu of Hillsboro OR (US) for intel corporation, Tongyan Zhai of Portland OR (US) for intel corporation, Min Suet Lim of Gelugor (MY) for intel corporation, Chee Chun Yee of Bayan Lepas (MY) for intel corporation, Eng Huat Goh of Paya Terubong (MY) for intel corporation, Jun Liao of Portland OR (US) for intel corporation, Kavitha Nagarajan of Bangalore (IN) for intel corporation
IPC Code(s): F28D15/04
CPC Code(s): F28D15/04
Abstract: systems, apparatus, articles of manufacture, and methods related to multi-sectional vapor chambers for electronic devices are disclosed. an example vapor chamber includes a first panel, a second panel, and a wall extending between the first panel and the second panel to separate the vapor chamber into a first section and a second section between both the first panel and the second panel, the wall including insulation.
Inventor(s): Fei Su of Ann Arbor MI (US) for intel corporation, Rakesh Kandula of Bangalore (IN) for intel corporation
IPC Code(s): G01R31/28, G01R31/317
CPC Code(s): G01R31/2896
Abstract: techniques and mechanisms for an integrated circuit (ic) die to support in-field testing and/or repair of a lane in a three-dimensional (3d) ic which is formed with multiple ic dies. in an embodiment, the 3d ic comprises test units which each correspond to a different partition comprising respective circuit resources. during in-field operation of the 3d ic, a given test unit is operable to detect both a first condition wherein two partitions are each in an idle state, and a second condition wherein a first link between the two partitions fails to satisfy a performance criteria. the idle states are indicated by a power management controller (pmc) agent during runtime operation of the 3d ic. in another embodiment, one or more test units configure an operational mode, based on the detected conditions, to substitute communication via the first lane with communication via a repair lane.
Inventor(s): Tarakesava Reddy Koki of Hyderabad (IN) for intel corporation, Prabhakar Subrahmanyam of San Jose CA (US) for intel corporation, Zhongsheng Wang of Camas WA (US) for intel corporation, Feroze Khan of Bangalore (IN) for intel corporation, Phani Alaparthi of Bengaluru (IN) for intel corporation, Shreedhar Shahapur of Bangalore (IN) for intel corporation, Venkata Mahesh Gunnam of East Godavari (IN) for intel corporation, Krishnendu Saha of Bangalore (IN) for intel corporation
IPC Code(s): G06F1/3231
CPC Code(s): G06F1/3231
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to perform power-saving based on user presence, including a network interface to communicate with a cloud device, user presence detector circuitry to determine if a user is present or not present; workload distributor circuitry to distribute an ai workload to either first ai inference circuitry or second ai inference circuitry; and power circuitry to charge a battery at either a first charge level or a second charge level.
Inventor(s): Rajesh POORNACHANDRAN of Portland OR (US) for intel corporation, Vincent J. ZIMMER of Issaquah WA (US) for intel corporation, Nilesh K. JAIN of Portland OR (US) for intel corporation
IPC Code(s): G06F9/445
CPC Code(s): G06F9/445
Abstract: an apparatus, method, and computer-readable medium for reconfiguring a support package for initializing firmware. the apparatus comprises memory, machine-readable instructions, and processor circuitry configured to execute the machine-readable instructions to intercept a write operation to a register of the processor circuitry requesting a configuration profile for the support package. the apparatus further selects an applet for the support package corresponding to the requested configuration profile, reconfigures the support package with the selected applet, and initializes firmware based on the reconfigured support package.
Inventor(s): Rajaram Regupathy of Bangalore (IN) for intel corporation, Reuven Rozic of Binyamina (IL) for intel corporation, Xiong Zhang of Beijing (CN) for intel corporation, Gil Fine of Modiin (IL) for intel corporation, Dmitriy Berchanskiy of Roseville CA (US) for intel corporation, Nirmala Bailur of Bangalore (IN) for intel corporation, Paul Crutcher of Welches OR (US) for intel corporation
IPC Code(s): G06F9/455, G06F13/42
CPC Code(s): G06F9/45558
Abstract: in one embodiment, a system comprises: a processor to execute a native operating system (os); and an interface circuit coupled to the processor, the interface circuit configured to tunnel communications of a plurality of tunneled protocols, the interface circuit to couple to at least one device via a first tunneled protocol, where a connection manager for the interface circuit is to execute in a user space of the native os. other embodiments are described and claimed.
Inventor(s): Pawel MAJEWSKI of Rotmanka (PL) for intel corporation, Prasoonkumar SURTI of Folsom CA (US) for intel corporation, Karthik VAIDYANATHAN of San Francisco CA (US) for intel corporation, Joshua BARCZAK of Forest Hill MD (US) for intel corporation, Vasanth RANGANATHAN of El Dorado Hills CA (US) for intel corporation, Vikranth VEMULAPALLI of Folsom CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/48, G06F9/54
CPC Code(s): G06F9/5027
Abstract: apparatus and method for stack access throttling for synchronous ray tracing. for example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.
Inventor(s): Gerasimos Gerogiannis of Champaign IL (US) for intel corporation, Wim Marcel Ann Heirman of Aalter (BE) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Stijn Erik D. Eyerman of Evergem (BE) for intel corporation
IPC Code(s): G06F9/50, G06F17/16
CPC Code(s): G06F9/5027
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for a machine learning model decompression accelerator. an example apparatus includes a processor core including at least one matrix multiplication engine, a memory storing a plurality of tiles of compressed data of a machine learning model to be processed by the at least one matrix multiplication engine; and a decompression accelerator including one or more control registers in communication with the processor core, a processing engine in communication with the memory and configured by the one or more control registers to decompress the plurality of tiles of the compressed data, and an output register to store decompressed data, wherein the processor core is to read the decompressed data from the output register and cause the at least one matrix multiplication engine to perform matrix multiplication with the decompressed data for execution of the machine learning model.
Inventor(s): Diego Garcia Rodriguez of Guadalajara (MX) for intel corporation, Omar Avelar Suarez of Zapopan (MX) for intel corporation, Claudia Barajas Rivera of Zapopan (MX) for intel corporation, Gaurav Porwal of Portland OR (US) for intel corporation, Luis Gonzalez Perez of Zapopan (MX) for intel corporation
IPC Code(s): G06F11/07, G06F13/40
CPC Code(s): G06F11/0745
Abstract: an example of an apparatus may include a processor to process request transactions and completion transactions for one or more respective communication protocols, memory coupled to the processor to store error-related transaction information, and circuitry coupled to the memory to save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols. other examples are disclosed and claimed.
20250053530. HIGHLY SCALABLE ACCELERATOR_simplified_abstract_(intel corporation)
Inventor(s): Philip R. Lantz of Cornelius OR (US) for intel corporation, Sanjay Kumar of Hillsboro OR (US) for intel corporation, Rajesh M. Sankaran of Portland OR (US) for intel corporation, Saurabh Gayen of Portland OR (US) for intel corporation
IPC Code(s): G06F13/364, G06F9/50, G06F13/24
CPC Code(s): G06F13/364
Abstract: embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. in an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. the work requests are to be dispatched to the plurality of engines from a plurality of work queues. the work queues are to store a work descriptor per work request. each work descriptor is to include all information needed to perform a corresponding work request.
20250053613. RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY_simplified_abstract_(intel corporation)
Inventor(s): Chunhui Mei of San Diego CA (US) for intel corporation, Hong Jiang of El Dorado Hills CA (US) for intel corporation, Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Yongsheng Liu of San Diego CA (US) for intel corporation, Yan Li of San Diego CA (US) for intel corporation
IPC Code(s): G06F17/16, G06F7/544, G06F9/30, G06F15/80, G06F17/11
CPC Code(s): G06F17/16
Abstract: matrix multiply units can take advantage of input sparsity by zero gating alus, which saves power consumption, but compute throughput does not increase. to improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. if zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.
Inventor(s): Vedvyas Shanbhogue of Austin TX (US) for intel corporation, Jason W. Brandt of Austin TX (US) for intel corporation, Ravi L. Sahita of Portland OR (US) for intel corporation, Barry E. Huntley of Hillsboro OR (US) for intel corporation, Baiju V. Patel of Portland OR (US) for intel corporation, Deepak K. Gupta of Portland OR (US) for intel corporation
IPC Code(s): G06F21/52, G06F3/06, G06F9/30, G06F9/46, G06F12/14
CPC Code(s): G06F21/52
Abstract: a processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. in one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. the plurality of registers is used to store data used in privilege level transitions. each register of the plurality of registers is associated with a privilege level. an indicator to change a first privilege level of a currently active application to a second privilege level is received. in view of the second privilege level, a shadow stack pointer (ssp) stored in a register of the plurality of registers is selected. the register is associated with the second privilege level. by using the ssp, a shadow stack for use by the processor at the second privilege level is identified.
Inventor(s): Robert S. Chappell of Portland OR (US) for intel corporation, Jared W. Stark, IV of Portland OR (US) for intel corporation, Joseph Nuzman of Haifa (IL) for intel corporation, Stephen Robinson of Austin TX (US) for intel corporation, Jason W. Brandt of Austin TX (US) for intel corporation
IPC Code(s): G06F21/55, G06F9/30, G06F9/38, G06F9/48, G06F12/0802, G06F21/62
CPC Code(s): G06F21/556
Abstract: systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. in one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.
20250053668. SCALABLE MULTI-KEY MEMORY ENCRYPTION_simplified_abstract_(intel corporation)
Inventor(s): Barry E. Huntley of Hillsboro OR (US) for intel corporation, Hormuzd M. Khosravi of Portland OR (US) for intel corporation, Thomas Toll of Portland OR (US) for intel corporation, Ramya Jayaram Masti of Hillsboro OR (US) for intel corporation, Siddhartha Chhabra of Portland OR (US) for intel corporation, Vincent Von Bokern of Rescue CA (US) for intel corporation
IPC Code(s): G06F21/60, G06F12/06, H04L9/14
CPC Code(s): G06F21/602
Abstract: embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. in an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. the core is to write data to and read data from memory regions, each to be identified by a corresponding address. the encryption unit to encrypt data to be written and decrypt data to be read. the key identification hardware is to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure. the corresponding key identifier is one multiple key identifiers. the corresponding key identifier is to identify which one of multiple encryption keys is to be used to encrypt and decrypt the data.
Inventor(s): Amit Bleiweiss of Yad Binyamin (IL) for intel corporation, Abhishek Venkatesh of Hillsboro OR (US) for intel corporation, Gokce Keskin of Mountain View CA (US) for intel corporation, John Gierach of Portland OR (US) for intel corporation, Oguz Elibol of Sunnyvale CA (US) for intel corporation, Tomer Bar-On of Petah Tikva (IL) for intel corporation, Huma Abidi of Santa Clara CA (US) for intel corporation, Devan Burke of Portland OR (US) for intel corporation, Jaikrishnan Menon of Portland OR (US) for intel corporation, Eriko Nurvitadhi of Hillsboro OR (US) for intel corporation, Pruthvi Gowda Thorehosur Appajigowda of San Jose CA (US) for intel corporation, Travis T. Schluessler of Berthoud CO (US) for intel corporation, Dhawal Srivastava of Phoenix AZ (US) for intel corporation, Nishant Patel of Santa Clara CA (US) for intel corporation, Anil Thomas of Santa Clara CA (US) for intel corporation
IPC Code(s): G06N3/063, G06F9/38, G06N3/04, G06N3/08, G06N5/046, G06N20/00, G06T1/20
CPC Code(s): G06N3/063
Abstract: an apparatus to facilitate compute optimization is disclosed. the apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.
Inventor(s): Yurong Chen of Beijing (CN) for intel corporation, Jianguo Li of Beijing (CN) for intel corporation, Renkun Ni of Beijing (CN) for intel corporation
IPC Code(s): G06N3/082, G06N3/063, G06N7/04
CPC Code(s): G06N3/082
Abstract: a mechanism is described for facilitating slimming of neural networks in machine learning environments. a method of embodiments, as described herein, includes learning a first neural network associated with machine learning processes to be performed by a processor of a computing device, where learning includes analyzing a plurality of channels associated with one or more layers of the first neural network. the method may further include computing a plurality of scaling factors to be associated with the plurality of channels such that each channel is assigned a scaling factor, wherein each scaling factor to indicate relevance of a corresponding channel within the first neural network. the method may further include pruning the first neural network into a second neural network by removing one or more channels of the plurality of channels having low relevance as indicated by one or more scaling factors of the plurality of scaling factors assigned to the one or more channels.
Inventor(s): Balaji Vembu of Folsom CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation
IPC Code(s): G06T1/20, G06T15/00
CPC Code(s): G06T1/20
Abstract: one embodiment provides an apparatus comprising an interconnect fabric comprising a processing cluster including an array of multiprocessors coupled to an interconnect fabric, scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors, each thread group comprising a plurality of threads. a first multiprocessor of the array of multiprocessors can be assigned to process a first thread group comprising a first plurality of threads including a first thread sub-group and a second thread sub-group. the second thread sub-group has a data dependency on the first thread sub-group and the first multiprocessor includes circuitry to cause threads of the second thread sub-group to sleep until the threads of the first thread sub-group have satisfied the data dependency.
Inventor(s): Veronica Aleman Strong of Etterbeek (BE) for intel corporation, Neelam Prabhu Gaunkar of Chandler AZ (US) for intel corporation
IPC Code(s): H01F17/00, H01F27/28, H01F41/04, H01F41/26
CPC Code(s): H01F17/0013
Abstract: described herein are inductor devices formed using wafer processing techniques. the inductor devices are singulated and can be mounted into different packages or computing systems. the magnetic material included in the inductor devices have higher aspect ratios (e.g., relatively tall and thin magnetic regions), which may be achieved using electroplating. the electroplated magnetic material is highly concentrated, which enables a higher inductance density.
Inventor(s): Charles Cameron Mokhtarzadeh of Portland OR (US) for intel corporation, Scott Peter Semproni of Fair Lawn NJ (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation
IPC Code(s): H01L21/033, G03F7/004, G03F7/16
CPC Code(s): H01L21/0332
Abstract: metal oxide resist layers including bismuth and phosphorus, and related methods are disclosed herein. an example method of fabricating a semiconductor device, the method including depositing a metal oxide resist layer on a base material by applying a precursor including bismuth, the metal oxide resist layer including a bismuth phosphate compound and patterning the metal oxide resist layer.
Inventor(s): Seok Ling LIM of Kulim (MY) for intel corporation, Eng Huat GOH of Paya Terubong (MY) for intel corporation, Kavitha NAGARAJAN of Bangalore (IN) for intel corporation, Kang Eu ONG of Simpang Ampat (MY) for intel corporation, Min Suet LIM of Gelugor (MY) for intel corporation
IPC Code(s): H01L23/053, H01L21/48, H01L23/16, H01L23/544, H01L25/065
CPC Code(s): H01L23/053
Abstract: according to various aspects, there may be provided a stiffener assembly. the stiffener assembly may include a primary stiffener and an auxiliary stiffener. the primary stiffener may include a first engagement arrangement, and the auxiliary stiffener may include a second engagement arrangement. the first engagement arrangement of the primary stiffener and the second engagement arrangement of the auxiliary stiffener may be configured to form a detachable joint with each other, thereby enabling the auxiliary stiffener to be releasably connected to the primary stiffener for reinforcing the primary stiffener.
Inventor(s): Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Rahul Nagaraj Manepalli of Chandler AZ (US) for intel corporation, Sashi Shekhar Kandanur of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L21/683, H01L21/768, H01L23/00, H01L23/13, H01L23/498, H01L23/538, H01L25/18, H05K1/18, H10B80/00
CPC Code(s): H01L23/15
Abstract: methods and apparatus to mitigate cracking in glass cores are disclosed. an example apparatus comprises a glass core having an opening extending between opposing surfaces of the glass core, and a metal within the opening. a gap between an interface of the metal and a sidewall of the opening.
Inventor(s): Yao-Feng Chang of Bellemont AZ (US) for intel corporation
IPC Code(s): H01L23/522, H01L23/525
CPC Code(s): H01L23/5226
Abstract: techniques for forming a semiconductor device (such as a metal-semiconductor-metal device) within the interconnect region over a device layer (such as plurality of field effect transistor (fet) devices). an interconnect layer within a stack of interconnect layers includes a metal-semiconductor-metal (msm) structure having a first metal layer, a semiconductor layer on the first metal layer, and a second metal layer on the semiconductor layer. the first metal layer may be directly on a first conductive layer of a lower interconnect layer (such as on a via or line of the lower interconnect layer). one or more other conductive layers may also be disposed between the first metal layer and the underlying first conductive layer. a second conductive layer may contact the top surface of the second metal layer.
20250055217. PINS FOR USE IN LAND GRID ARRAY_simplified_abstract_(intel corporation)
Inventor(s): Min Pei of Camas WA (US) for intel corporation, Lejie Liu of Portland OR (US) for intel corporation, Ralph Miele of Hillsboro OR (US) for intel corporation, Phil Geng of Washougal WA (US) for intel corporation, Steven Klein of Chandler AZ (US) for intel corporation
IPC Code(s): H01R13/24, H01R12/71
CPC Code(s): H01R13/2442
Abstract: a land grid array (lga) interface assembly used to physically interface or connect a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) and a pcb, motherboard, etc. the lga interface assembly including an lga socket including a plurality of socket pins arranged and configured to contact a plurality of contact pads on the semiconductor package to enable data transfer. the socket pins including a multi-bend and/or zig-zag configuration arranged and configured to minimize lateral displacement of the socket pin relative to the contact pad during insertion of the semiconductor package into the lga socket. other embodiments are described and claimed.
Inventor(s): Xiaogang CHEN of Portland OR (US) for intel corporation, Qinghua LI of San Ramon CA (US) for intel corporation, Thomas J. KENNEY of Portland OR (US) for intel corporation
IPC Code(s): H04L5/00, H04L69/22, H04W72/0453, H04W72/23
CPC Code(s): H04L5/0053
Abstract: this disclosure describes systems, methods, and devices related to extremely high throughput (eht) trigger based (tb) preamble. a device may receive a trigger frame from an associated access point (ap), wherein the trigger frame comprises one or more resource unit (ru) bandwidths (bws) allocated to the device. the device may generate an eht physical layer protocol data unit (ppdu) based on receiving the trigger frame from the access point, wherein the ppdu comprises an eht preamble that includes a signaling (u-sig) field. the device may encode the u-sig field with an indication of one or more resource unit (ru) bandwidth (bw) allocations to be used for sending the ppdu to the ap, wherein the indication is a value associated with a first option of one or more options of selectable ru bws. the device may cause to send the ppdu to the ap and an uplink data transmission direction.
Inventor(s): Brinda Ganesh of Portland OR (US) for intel corporation, Nilesh Jain of Portland OR (US) for intel corporation, Sumit Mohan of San Jose CA (US) for intel corporation, Faouzi Kossentini of Vancouver (CA) for intel corporation, Jill Boyce of Portland OR (US) for intel corporation, James Holland of Folsom CA (US) for intel corporation, Zhijun Lei of Portland OR (US) for intel corporation, Chekib Nouira of Mission (CA) for intel corporation, Foued Ben Amara of Vancouver (CA) for intel corporation, Hassene Tmar of Richmond (CA) for intel corporation, Sebastian Possos of Sammamish WA (US) for intel corporation, Craig Hurst of Hillsboro OR (US) for intel corporation
IPC Code(s): H04N19/114, H04N19/154
CPC Code(s): H04N19/114
Abstract: techniques related to distributing the video encoding processing of an input video across hardware and software systems. such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.
Inventor(s): Ximin Zhang of San Jose CA (US) for intel corporation, Sang-Hee Lee of San Jose CA (US) for intel corporation, Keith W. Rowe of Shingle Springs CA (US) for intel corporation
IPC Code(s): H04N19/159, G06N3/084, H04N19/176, H04N19/179, H04N19/30, H04N19/70
CPC Code(s): H04N19/159
Abstract: techniques related to quantization parameter estimation for coding intra and scene change frames are discussed. such techniques include generating features based on an intra or scene change frame including a proportion of smooth blocks and one or both of a measure of block variance and a prediction distortion, and applying a machine learning model to generate an estimated quantization parameter for encoding the intra or scene change frame.
Inventor(s): Markus Dominik Mueck of Unterhaching (DE) for intel corporation
IPC Code(s): H04W60/02, H04W36/00, H04W76/23
CPC Code(s): H04W60/02
Abstract: a base station (bs) circuitry, configured to adapt operation of a user equipment (ue) between a stand-alone operation mode and a mobile network operator (mno) assisted operation mode, includes: a first interface connectable to an mno network; a second interface connectable to the ue; and a bs controller, configured to: transmit a first register message via the first interface to the mno network, wherein the first register message indicates a request to operate the ue in at least one licensed frequency band of the mno network, and signal a hand-over via the second interface to the ue, wherein the hand-over indicates a transition from operating the ue in at least one frequency band of the stand-alone operation mode to operating the ue in the at least one licensed frequency band of the mno assisted operation mode.
20250056486. ENHANCED PRECISION RANGING FOR WI-FI NETWORKS_simplified_abstract_(intel corporation)
Inventor(s): Qinghua LI of San Ramon CA (US) for intel corporation, Jonathan SEGEV of Sunnyvale CA (US) for intel corporation, Xintian LIN of Palo Alto CA (US) for intel corporation, Shlomi VITURI of Tel Aviv (IL) for intel corporation, Robert STACEY of Portland OR (US) for intel corporation, Carlos CORDEIRO of Camas WA (US) for intel corporation
IPC Code(s): H04W64/00, H04W24/10, H04W56/00
CPC Code(s): H04W64/00
Abstract: this disclosure describes systems, methods, and devices related to enhanced ranging. a device may initiate a ranging sequence by transmitting an ndpa frame followed by an i2r ndp frame. the device may receive a corresponding r2i ndp frame and an r2i lmr from a responding station. the device may repeat the ranging sequence for two or more iterations to collect multiple data sets. the device may process the r2i ndp frame and the r2i lmr to generate continuous toa and tod measurements for each iteration.
20250056598. MULTI-CARRIER/BEAM LBT PROCEDURE ABOVE 52.6GHZ_simplified_abstract_(intel corporation)
Inventor(s): Salvatore Talarico of Los Gatos CA (US) for intel corporation, Yi Wang of Beijing (CN) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation, Dae Won LEE of Portland OR (US) for intel corporation
IPC Code(s): H04W74/00, H04W74/0808
CPC Code(s): H04W74/006
Abstract: an apparatus and system of providing a listen before talk (lbt) procedure in multi-carrier or multi-beam mode above a 52.6 ghz band are described. the lbt procedure is performed independently for each carrier or beam to maintain and update a different back-off counter for each carrier or beam. to align a transmission starting time across the carriers or beams, for each carrier or beam: the counter continues to decrement if the counter has reached zero before the starting time and transmit at the starting time if the channel continues to be sensed idle for an additional observation period immediately prior to the starting time and otherwise considers the lbt procedure to have failed. the counter is reinitialized for carriers or beams for which a channel occupancy time (cot) is to be acquired and transmission ceases.
Intel Corporation patent applications on February 13th, 2025
- Intel Corporation
- A63F13/52
- G06T3/4046
- G06T3/4053
- CPC A63F13/52
- Intel corporation
- F28D15/04
- CPC F28D15/04
- G01R31/28
- G01R31/317
- CPC G01R31/2896
- G06F1/3231
- CPC G06F1/3231
- G06F9/445
- CPC G06F9/445
- G06F9/455
- G06F13/42
- CPC G06F9/45558
- G06F9/50
- G06F9/48
- G06F9/54
- CPC G06F9/5027
- G06F17/16
- G06F11/07
- G06F13/40
- CPC G06F11/0745
- G06F13/364
- G06F13/24
- CPC G06F13/364
- G06F7/544
- G06F9/30
- G06F15/80
- G06F17/11
- CPC G06F17/16
- G06F21/52
- G06F3/06
- G06F9/46
- G06F12/14
- CPC G06F21/52
- G06F21/55
- G06F9/38
- G06F12/0802
- G06F21/62
- CPC G06F21/556
- G06F21/60
- G06F12/06
- H04L9/14
- CPC G06F21/602
- G06N3/063
- G06N3/04
- G06N3/08
- G06N5/046
- G06N20/00
- G06T1/20
- CPC G06N3/063
- G06N3/082
- G06N7/04
- CPC G06N3/082
- G06T15/00
- CPC G06T1/20
- H01F17/00
- H01F27/28
- H01F41/04
- H01F41/26
- CPC H01F17/0013
- H01L21/033
- G03F7/004
- G03F7/16
- CPC H01L21/0332
- H01L23/053
- H01L21/48
- H01L23/16
- H01L23/544
- H01L25/065
- CPC H01L23/053
- H01L23/15
- H01L21/683
- H01L21/768
- H01L23/00
- H01L23/13
- H01L23/498
- H01L23/538
- H01L25/18
- H05K1/18
- H10B80/00
- CPC H01L23/15
- H01L23/522
- H01L23/525
- CPC H01L23/5226
- H01R13/24
- H01R12/71
- CPC H01R13/2442
- H04L5/00
- H04L69/22
- H04W72/0453
- H04W72/23
- CPC H04L5/0053
- H04N19/114
- H04N19/154
- CPC H04N19/114
- H04N19/159
- G06N3/084
- H04N19/176
- H04N19/179
- H04N19/30
- H04N19/70
- CPC H04N19/159
- H04W60/02
- H04W36/00
- H04W76/23
- CPC H04W60/02
- H04W64/00
- H04W24/10
- H04W56/00
- CPC H04W64/00
- H04W74/00
- H04W74/0808
- CPC H04W74/006