Intel Corporation patent applications on April 24th, 2025
Patent Applications by Intel Corporation on April 24th, 2025
Intel Corporation: 21 patent applications
Intel Corporation has applied for patents in the areas of H01L23/538 (2), H01L23/522 (2), H10D62/10 (2), H10D30/01 (2), H10D84/85 (2) B23K35/262 (1), H01L23/5226 (1), H10D84/853 (1), H10D64/691 (1), H05K7/20336 (1)
With keywords such as: material, device, gate, layer, example, service, dielectric, apparatus, conductive, and structure in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Rui Zhang of Chandler AZ US for intel corporation, Jiaqi Wu of Chandler AZ US for intel corporation, Brian Franco of Portland OR US for intel corporation, Xiao Lu of Chandler AZ US for intel corporation, Mukul Renavikar of North Plains OR US for intel corporation
IPC Code(s): B23K35/26, B23K35/02, B23K103/08, C22C13/02
CPC Code(s): B23K35/262
Abstract: solder materials and microelectronic devices and systems deploying the solder materials are discussed. the solder material includes a bulk material of tin and bismuth and particles interspersed in the tin and bismuth bulk material. the particles are a metal other than tin and bismuth, and an intermetallic compound is formed around the particles. the intermetallic compound includes the metal of the particles and tin or bismuth. the solder materials are deployed as interconnect structures to interconnect components, such as electrically coupling an integrated circuit package to a motherboard.
Inventor(s): Javier Felix Rendon of Zapopan MX for intel corporation, Leobardo Campos Macias of Guadalajara MX for intel corporation, Javier Felip Leon of Hillsboro OR US for intel corporation, David Gonzalez Aguirre of Hillsboro OR US for intel corporation, Julio Zamora Esquivel of West Sacramento CA US for intel corporation
IPC Code(s): B60G17/0165, G01S17/08, G01S17/931, G05D1/65, G05D109/10
CPC Code(s): B60G17/0165
Abstract: a transport system, including: a plurality of self-lifting wheel units individually controllable and mounted to a transport platform; one or more sensors mounted to the transport platform and configured to detect a floor obstacle, floor elevation change, or floor surface irregularity; a control system operatively connected to the plurality of self-lifting wheel units and the one or more sensors, wherein the control system is configured to: receive floor obstacle, elevation change, or surface irregularity detection data from the one or more sensors; plan and control the plurality of self-lifting wheel units to selectively lift or lower to maintain stability of the transport platform when traversing the floor obstacle, the floor elevation change, or the floor surface irregularity; and regulate movement of the transport platform to traverse the floor obstacle, the floor elevation change, or the floor surface irregularity based the plan and control.
Inventor(s): Vesh Raj Sharma Banjade of Portland OR US for intel corporation, S M Iftekharul Alam of Hillsboro OR US for intel corporation, Arvind Merwaday of Beaverton OR US for intel corporation, Satish Chandra Jha of Portland OR US for intel corporation, Kathiravetpillai Sivanesan of Portland OR US for intel corporation, Kuilin Clark Chen of Portland OR US for intel corporation, Francesc Guim Bernat of Barcelona ES for intel corporation, Kshitij Arun Doshi of Tempe AZ US for intel corporation, Leonardo Gomes Baltar of Muenchen DE for intel corporation, Suman A. Sehra of Folsom CA US for intel corporation, Soo Jin Tan of Shanghai CN for intel corporation, Markus Dominik Mueck of Unterhaching DE for intel corporation
IPC Code(s): B60W30/06, B60L53/36, B60L53/63, B60L55/00, G06Q20/40, G06Q30/0283, G08G1/0967, G08G1/14
CPC Code(s): B60W30/06
Abstract: systems and techniques for location management are described herein. in an example, a system may include at least one processor and at least one memory with instructions stored thereon that when executed by the processor, cause the processor to obtain data originating from one or more sensors proximate to the location. a trained activity-based detection model may identify an activity at the location and perform a determination of a service to be offered at the location based on the detected activity. the system may then send a message to a user offering the service to the user, and in response to receiving an authorization accepting the service from the user, cause the service to be implemented at the location, which may include classifying the service as a service type, matching the service type to a service provider, and sending a notification to the service provider.
Inventor(s): Thomas Martin Counihan of Fermoy IE for intel corporation, Adrian Christopher Hoban of Cratloe IE for intel corporation, Francesc Guim Bernat of Barcelona ES for intel corporation
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/441
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to partition a boot drive for two or more processor circuits. an example apparatus includes at least one first processor circuit to determine at least one first parameter for a first namespace and at least one second parameter for a second namespace to be configured for a non-volatile memory (nvm) boot drive, cause a first controller of the nvm boot drive to create the first namespace based on the at least one first parameter, and cause the first controller to create the second namespace based on the at least one second parameter. also, the example at least one first processor circuit is to attach the first namespace to the first controller of the nvm boot drive, attach the second namespace to a second controller of the nvm boot drive, and attach the second controller to a bootloader of a second processor circuit.
Inventor(s): Vasanth Ranganathan of El Dorado Hills CA US for intel corporation, James Valerio of North Plains OR US for intel corporation, Joydeep Ray of Folsom CA US for intel corporation, Abhishek R. Appu of El Dorado Hills CA US for intel corporation, Alan Curtis of El Dorado Hills CA US for intel corporation, Prathamesh Raghunath Shinde of Folsom CA US for intel corporation, Brandon Fliflet of El Dorado Hills CA US for intel corporation, Ben J. Ashbaugh of Folsom CA US for intel corporation, John Wiegert of Aloha OR US for intel corporation
IPC Code(s): G06F9/48, G06F9/38, G06T1/20
CPC Code(s): G06F9/485
Abstract: an apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. the apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (tg) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (tg) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the tg, cause, by the thread of the tg having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the tg.
20250130874. MEMORY-BASED CROSS-DOMAIN I/O FRAMEWORK_simplified_abstract_(intel corporation)
Inventor(s): Akhilesh Thyagaturu of Ruskin FL US for intel corporation, Jason Howard of Portland OR US for intel corporation, Stanley T. Mo of Portland OR US for intel corporation, Nicholas G. Ross of Lake Forest CA US for intel corporation, Sanjaya Tayal of Portland OR US for intel corporation
IPC Code(s): G06F9/54
CPC Code(s): G06F9/544
Abstract: a cross-domain device includes a memory with a shared memory region. the device further includes a first interface to couple to a first device over a first interconnect, where the first device implements a first domain, and includes a second interface to couple to a second device over a second interconnect, where the second device implements a second domain, and the first domain is independent of the second domain. the cross-domain device is to create a buffer in the shared memory region to allow writes by a first software module in the first domain and reads by a second software module in the second domain, and use the buffer to implement a memory-based communication link between the first software module and the second software module.
Inventor(s): Anthony Sarah of San Diego CA US for intel corporation, Daniel Cummings of Austin TX US for intel corporation, Juan Pablo Munoz of Folsom CA US for intel corporation, Tristan Webb of San Diego CA US for intel corporation
IPC Code(s): G06F16/953, G06N5/02
CPC Code(s): G06F16/953
Abstract: the present disclosure is related to framework for automatically and efficiently finding machine learning (ml) architectures that are optimized to one or more specified performance metrics and/or hardware platforms. this framework provides ml architectures that are applicable to specified ml domains and are optimized for specified hardware platforms in significantly less time than could be done manually and in less time than existing ml model searching techniques. furthermore, a user interface is provided that allows a user to search for different ml architectures based on modified search parameters, such as different hardware platform aspects and/or performance metrics. other embodiments may be described and/or claimed.
Inventor(s): Eric Luk of Dublin IE for intel corporation, Mohamed Elmalaki of Chandler AZ US for intel corporation, Sara Almalih of Scottsdale AZ US for intel corporation, Cormac Brick of San Francisco CA US for intel corporation
IPC Code(s): G06N3/063, G06N3/04, G06N3/08
CPC Code(s): G06N3/063
Abstract: examples to determine a dynamic batch size of a layer are disclosed herein. an example apparatus to determine a dynamic batch size of a layer includes a layer operations controller to determine a layer ratio between a number of operations of a layer and weights of the layer, a comparator to compare the layer ratio to a number of operations per unit of memory size performed by a computation engine, and a batch size determination controller to, when the layer ratio is less than the number of operations per unit of memory size, determine the dynamic batch size of the layer.
Inventor(s): Rony Zatzarinni of Tel Aviv IL for intel corporation, Dor Barber of Herzliya IL for intel corporation, Andrey Semenjatshenco of Givataim IL for intel corporation
IPC Code(s): G06V10/84, G06T7/90, G06T11/60, G06V10/56
CPC Code(s): G06V10/84
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to implement personalized skin tone adaptation for images and video. an example apparatus disclosed herein obtains an initial skin tone group distribution for an identified user depicted in an input image. the example apparatus also determines, based on the input image, a plurality of skin tone measurements associated respectfully with a plurality of skin tone groups corresponding to the initial skin tone group distribution. the example apparatus further outputs a revised skin tone group distribution based on the skin tone measurements, the initial skin tone group distribution, and a transition model.
Inventor(s): Shruthi Sudhakar of Bangalore IN for intel corporation, Sumod Cherukkate of Bangalore IN for intel corporation, Praveen Kashyap Ananta Bhat of Bangalore IN for intel corporation, Prakash Kurma Raju of Bangalore IN for intel corporation, Prasanna Pichumani of Bangalore IN for intel corporation, A Ezekiel Poulose of Ernakulam IN for intel corporation
IPC Code(s): H01H13/7065, H04R1/02
CPC Code(s): H01H13/7065
Abstract: apparatus including speakers ported through keys of a keyboard are disclosed. an example electronic device includes a housing, and a keyboard carried by the housing. the keyboard includes a key having a keycap that covers an associated switch. the example electronic device further includes a speaker within the housing underneath the keyboard. the keycap includes an opening to define a port through which sound from the speaker is able to pass.
Inventor(s): Hongxia Feng of Chandler AZ US for intel corporation, Thomas Stanley Heaton of Gilbert AZ US for intel corporation, Shayan Kaviani of Phoenix AZ US for intel corporation, Yonggang Li of Chandler AZ US for intel corporation, Mahdi Mohammadighaleni of Phoenix AZ US for intel corporation, Bai Nie of Chandler AZ US for intel corporation, Dilan Seneviratne of Phoenix AZ US for intel corporation, Joshua James Stacey of Chandler AZ US for intel corporation, Hiroki Tanaka of Gilbert AZ US for intel corporation, Elham Tavakoli of Phoenix AZ US for intel corporation, Ehsan Zamani of Phoenix AZ US for intel corporation
IPC Code(s): H01L23/498
CPC Code(s): H01L23/49827
Abstract: porous liners for through-glass vias and associated methods are disclosed. an example apparatus includes a glass layer having a through-hole. the example apparatus further includes a conductive material within the through-hole. the example apparatus also includes a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.
20250132245. ELECTRICALLY SELF-INSULATED VIA_simplified_abstract_(intel corporation)
Inventor(s): Tofizur RAHMAN of Portland OR US for intel corporation, Conor P. Puls of Portland OR US for intel corporation, Payam Amin of Portland OR US for intel corporation, Santhosh Koduri of Portland OR US for intel corporation, Clay Mortensen of Portland OR US for intel corporation, Bozidar Marinkovic of Portland OR US for intel corporation, Shivani Falgun Patel of Hillsboro OR US for intel corporation, Richard Bonsu of Hillsboro OR US for intel corporation, Jaladhi Mehta of Beaverton OR US for intel corporation, Dincer Unluer of Hillsboro OR US for intel corporation
IPC Code(s): H01L23/522, H01L23/528, H01L23/532
CPC Code(s): H01L23/5226
Abstract: a fabrication method and associated integrated circuit (ic) structures and devices that include one or more self-insulated vias is described herein. in one example, an ic structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. in one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.
Inventor(s): Bernd Waidhas of Pettendorf DE for intel corporation, Carlton Hanna of Santa Jose CA US for intel corporation, Stephen Morein of San Jose CA US for intel corporation, Lizabeth Keser of San Diego CA US for intel corporation, Georg Seidemann of Landshut DE for intel corporation
IPC Code(s): H01L23/538, H01L23/50, H01L23/522
CPC Code(s): H01L23/5384
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; a first microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by an insulating material; a second microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by the insulating material and including a through-substrate via (tsv) electrically coupled to the first conductive pathway; and a redistribution layer (rdl), on the insulating material, including a second conductive pathway electrically coupling the tsv, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.
Inventor(s): Huong Thu Do of Chandler AZ US for intel corporation, Nicholas Steven Haehn of Scottsdale AZ US for intel corporation, Brandon Christian Marin of Gilbert AZ US for intel corporation, Mitchell Ian Page of Mesa AZ US for intel corporation, Erhan Atci of Maricopa AZ US for intel corporation
IPC Code(s): H01L23/538, H01L23/15, H01L25/18, H10D1/20
CPC Code(s): H01L23/5386
Abstract: glass cores with embedded power delivery components are disclosed. an example apparatus includes a glass layer including an opening, a dielectric material within the opening, a first cluster of inductors extending through the dielectric material, and a second cluster of inductors extending through the dielectric material, the second cluster spaced apart from the first cluster, the dielectric material extending continuously from around the first cluster to around the second cluster.
Inventor(s): Akhilesh Thyagaturu of Ruskin FL US for intel corporation, Jason Howard of Portland OR US for intel corporation, Stanley T. Mo of Portland OR US for intel corporation, Nicholas G. Ross of Lake Forest CA US for intel corporation, Sanjaya Tayal of Portland OR US for intel corporation
IPC Code(s): H04L67/10, H04W28/08
CPC Code(s): H04L67/10
Abstract: a cross-domain device includes a first interface to couple to a first device and a second interface to couple to a second device, where the first device is to implement a first component in a radio access network (ran) system in a first computing domain, and the second device is to implement a second component in the ran system in a second computing domain. the first component is to interface within the second component in a ran processing pipeline. the cross-domain device further comprises hardware to implement a communication channel between the first device and the second device to pass data from the first component to the second component, where the communication channel enforces isolation of the first computing domain from the second computing domain.
20250133495. SERVICE PERIOD BASED PARAMETER UPDATES_simplified_abstract_(intel corporation)
Inventor(s): Laurent CARIOU of Milizac FR for intel corporation
IPC Code(s): H04W52/02
CPC Code(s): H04W52/0216
Abstract: this disclosure describes systems, methods, and devices related to enhanced service period updates. a device may receive, from a station (sta), a negotiation request that identifies a service period and one or more transmission and reception (tx/rx) parameters to be updated during the service period. the device may define the service period based on the received negotiation request, wherein the service period is determined using a target wake time (twt) element. the device may adjust, based on the negotiation request, the one or more tx/rx parameters for operation during the service period, wherein the one or more tx/rx parameters include at least a maximum modulation and coding scheme (max mcs). the device may transmit a confirmation to the sta after updating the one or more tx/rx parameters. the device may revert the one or more tx/rx parameters to default values outside the service period.
Inventor(s): Christian Amoah-Kusi of Scappoose OR US for intel corporation, Chi-Hung Chuang of New Taipei City TW for intel corporation, Jing-Hua He of Portland OR US for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20254
Abstract: a cold plate comprises a plurality of fins. the individual fins have an opening, and the openings collectively define a first channel through the plurality of fins. during operation of an integrated circuit component attached to the cold plate, coolant is pumped through the cold plate. the coolant flows in a first direction through the first channel and then in a second through second channels located between the fins. the first direction is substantially orthogonal to the second direction. the first channel can comprise a tube that has openings that direct coolant to flow into the second channels. the first channel is located close to the base plate of the cold plate so that there is a high degree of heat transfer between an integrated circuit component attached to the cold plate and coolant flowing through the cold plate.
Inventor(s): Chi Chou Cheng of Taipei TW for intel corporation, Jeff Ku of Taipei TW for intel corporation, Chung Jen Ho of New Taipei TW for intel corporation, Chihtsung Hu of New Taipei TW for intel corporation, Tsung-Kai Lin of New Taipei TW for intel corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/20336
Abstract: an electronic device is provided that implements thermally conductive plastic supports that may replace the typical use of “feet” used in conventional electronic devices. the thermally conductive supports may extend through the bottom chassis cover (e.g. the “d cover”) of the electronic device, and be mechanically and thermally coupled to a heat pipe that is in turn coupled to a heat source for which thermal regulation is utilized. the thermally conductive plastic supports may provide a heat path from the heat source to the bottom chassis cover and, when the electronic device is disposed on a surface, an additional heat path may be provided from the heat source to this surface.
Inventor(s): Christine RADLINGER of Portland OR US for intel corporation, Tongtawee WACHARASINDHU of Hillsboro OR US for intel corporation, Andre BARAN of Portland OR US for intel corporation, Kiran CHIKKADI of Hillsboro OR US for intel corporation, Devin MERRILL of McMinnville OR US for intel corporation, Nilesh DENDGE of Hillsboro OR US for intel corporation, David J. TOWNER of Portland OR US for intel corporation, Christopher KENYON of Portland OR US for intel corporation
IPC Code(s): H10D64/68, H10D64/27, H10D84/83
CPC Code(s): H10D64/691
Abstract: self-aligned gate endcap (sage) architectures with improved caps, and methods of fabricating self-aligned gate endcap (sage) architectures with improved caps, are described. in an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. a second gate structure is over a second semiconductor fin. a gate endcap isolation structure is between the first gate structure and the second gate structure. the gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. the higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.
Inventor(s): Tahir GHANI of Portland OR US for intel corporation, Mohit K. HARAN of Hillsboro OR US for intel corporation, Mohammad HASAN of Aloha OR US for intel corporation, Biswajeet GUHA of Hillsboro OR US for intel corporation, Alison V. DAVIS of Portland OR US for intel corporation, Leonard P. GULER of Hillsboro OR US for intel corporation
IPC Code(s): H10D84/85, H10D30/01, H10D30/62, H10D62/10
CPC Code(s): H10D84/853
Abstract: integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. for example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (sti) structure. a gate dielectric material layer is over the protruding portion of the fin and over the sti structure. a conductive gate layer is over the gate dielectric material layer. a conductive gate fill material is over the conductive gate layer. a dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the sti structure. the gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.
Inventor(s): Nicole Thomas of Portland OR US for intel corporation, Eric Mattson of Portland OR US for intel corporation, Sudarat Lee of Hillsboro OR US for intel corporation, Scott B. Clendenning of Portland OR US for intel corporation, Tobias Brown-Heft of Portland OR US for intel corporation, I-Cheng Tung of Hillsboro OR US for intel corporation, Thoe Michaelos of Portland OR US for intel corporation, Gilbert Dewey of Beaverton OR US for intel corporation, Charles Kuo of Hillsboro OR US for intel corporation, Matthew Metz of Portland OR US for intel corporation, Marko Radosavljevic of Portland OR US for intel corporation, Charles Mokhtarzadeh of Portland OR US for intel corporation
IPC Code(s): H10D84/85, H01L21/02, H01L21/28, H10D30/01, H10D30/67, H10D30/69, H10D62/10, H10D84/01, H10D84/03
CPC Code(s): H10D84/856
Abstract: integrated circuitry comprising a ribbon or wire (row) transistor stack within which the transistors have different threshold voltages (v). in some examples, a gate electrode of the transistor stack may include only one workfunction metal. a metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). as diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of vwithin the stack. after diffusion, the metal oxide may be stripped as sacrificial, or retained.
- Intel Corporation
- B23K35/26
- B23K35/02
- B23K103/08
- C22C13/02
- CPC B23K35/262
- Intel corporation
- B60G17/0165
- G01S17/08
- G01S17/931
- G05D1/65
- G05D109/10
- CPC B60G17/0165
- B60W30/06
- B60L53/36
- B60L53/63
- B60L55/00
- G06Q20/40
- G06Q30/0283
- G08G1/0967
- G08G1/14
- CPC B60W30/06
- G06F9/4401
- CPC G06F9/441
- G06F9/48
- G06F9/38
- G06T1/20
- CPC G06F9/485
- G06F9/54
- CPC G06F9/544
- G06F16/953
- G06N5/02
- CPC G06F16/953
- G06N3/063
- G06N3/04
- G06N3/08
- CPC G06N3/063
- G06V10/84
- G06T7/90
- G06T11/60
- G06V10/56
- CPC G06V10/84
- H01H13/7065
- H04R1/02
- CPC H01H13/7065
- H01L23/498
- CPC H01L23/49827
- H01L23/522
- H01L23/528
- H01L23/532
- CPC H01L23/5226
- H01L23/538
- H01L23/50
- CPC H01L23/5384
- H01L23/15
- H01L25/18
- H10D1/20
- CPC H01L23/5386
- H04L67/10
- H04W28/08
- CPC H04L67/10
- H04W52/02
- CPC H04W52/0216
- H05K7/20
- CPC H05K7/20254
- G06F1/20
- CPC H05K7/20336
- H10D64/68
- H10D64/27
- H10D84/83
- CPC H10D64/691
- H10D84/85
- H10D30/01
- H10D30/62
- H10D62/10
- CPC H10D84/853
- H01L21/02
- H01L21/28
- H10D30/67
- H10D30/69
- H10D84/01
- H10D84/03
- CPC H10D84/856
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